JP3312395B2 - Inspection method of wire bonding - Google Patents

Inspection method of wire bonding

Info

Publication number
JP3312395B2
JP3312395B2 JP25719092A JP25719092A JP3312395B2 JP 3312395 B2 JP3312395 B2 JP 3312395B2 JP 25719092 A JP25719092 A JP 25719092A JP 25719092 A JP25719092 A JP 25719092A JP 3312395 B2 JP3312395 B2 JP 3312395B2
Authority
JP
Japan
Prior art keywords
wire
semiconductor chip
focus
camera
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP25719092A
Other languages
Japanese (ja)
Other versions
JPH0682226A (en
Inventor
喜久雄 後藤
久隆 伊沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP25719092A priority Critical patent/JP3312395B2/en
Publication of JPH0682226A publication Critical patent/JPH0682226A/en
Application granted granted Critical
Publication of JP3312395B2 publication Critical patent/JP3312395B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、ワイヤボンディングの
検査方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding inspection method.

【０００２】[0002]

【従来の技術】ワイヤボンディングの検査項目の中に
は、半導体チップのエッジ部とワイヤとのクリアランス
を検査する項目があり、この検査を行うことによってワ
イヤが半導体チップのエッジ部に接触して起こる、いわ
ゆるエッジショートや、モールド時にパッケージからワ
イヤがはみ出すなどの不良発生を未然に回避することが
できる。2. Description of the Related Art Among the inspection items for wire bonding, there is an item for inspecting a clearance between an edge portion of a semiconductor chip and a wire. By performing this inspection, the wire comes into contact with the edge portion of the semiconductor chip. Therefore, it is possible to prevent the occurrence of defects such as edge short-circuit and protrusion of wires from the package during molding.

【０００３】従来、この種のワイヤボンディングの検査
方法としては、作業者が実体顕微鏡を覗きながら半導体
チップのエッジ部とワイヤとのクリアランスを測定する
のが一般的であった。この方法では、顕微鏡に取り付け
られた目盛りを基準に上記クリアランスを測定し、その
測定値が所定範囲内にあるか否かによって良品、不良品
の判定をしていた。Conventionally, as a method of inspecting this kind of wire bonding, it has been general that an operator measures a clearance between an edge portion of a semiconductor chip and a wire while looking through a stereoscopic microscope. In this method, the clearance is measured based on a scale attached to a microscope, and a good product or a defective product is determined based on whether the measured value is within a predetermined range.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら上記従来
の目視による検査方法では、短時間で検査できるという
利点はあるものの、繰り返しによる測定誤差や作業者間
での判定基準のバラツキによって、半導体チップのエッ
ジ部とワイヤとのクリアランスを精度良く検査すること
ができず、信頼性に欠けるといった問題があった。However, the above-mentioned conventional visual inspection method has the advantage that the inspection can be performed in a short time, but the measurement error due to the repetition and the variation of the judgment criterion among the operators cause the edge of the semiconductor chip to be inadequate. There has been a problem that the clearance between the part and the wire cannot be inspected with high accuracy, resulting in a lack of reliability.

【０００５】本発明は、上記問題を解決するためになさ
れたもので、半導体チップのエッジ部とワイヤとのクリ
アランスを短時間でしかも精度良く検査することができ
るワイヤボンディングの検査方法を提供することを目的
とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and provides a wire bonding inspection method capable of inspecting the clearance between an edge portion of a semiconductor chip and a wire in a short time and with high accuracy. With the goal.

【０００６】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、半導体チップの上面に形
成された電極パッドと該半導体チップの周辺に配置され
たリードとをワイヤにて接続するワイヤボンディングに
おいて、前記半導体チップのエッジ部と前記ワイヤとの
クリアランスを検査するためのワイヤボンディングの検
査方法であって、前記半導体チップの上方に設置したカ
メラにより該半導体チップの上面とほぼ同じ高さに位置
であって前記カメラの焦点深度の範囲内でとらえられる
前記ワイヤの焦点画像を取り込む工程と、前記焦点画像
に画像処理を施して該焦点画像から焦点位置を抽出する
工程と、前記電極パッド上の予め求めておいたボンディ
ング位置から前記焦点位置までの距離を算出する工程と
からなるものである。また、前記半導体チップの上面に
焦点を合わせたカメラで前記ワイヤを映し出すことによ
り前記焦点画像を取り込み可能としたものである。さら
に、被測定物に光源から光が照射されており、前記カメ
ラにより取り込まれた前記焦点画像の中で最も輝度の高
い位置を前記焦点位置として抽出するようにしたもので
ある。SUMMARY OF THE INVENTION The present invention has been made to achieve the above-mentioned object. An electrode pad formed on an upper surface of a semiconductor chip and leads arranged around the semiconductor chip are connected to wires. A wire bonding inspection method for inspecting a clearance between an edge portion of the semiconductor chip and the wire in the wire bonding, wherein a camera installed above the semiconductor chip substantially contacts an upper surface of the semiconductor chip. Capturing a focus image of the wire at the same height and captured within the range of the depth of focus of the camera, and performing image processing on the focus image to extract a focus position from the focus image; Calculating a distance from a previously determined bonding position on the electrode pad to the focal position. . Further, the focus image can be captured by projecting the wire with a camera focused on the upper surface of the semiconductor chip. Further, light is emitted from a light source to the object to be measured, and a position having the highest luminance in the focal image captured by the camera is extracted as the focal position.

【０００７】[0007]

【作用】本発明のワイヤボンディングの検査方法におい
ては、半導体チップの上方に設置したカメラによってワ
イヤの焦点画像が取り込まれ、この焦点画像に画像処理
を施すことによって測定点となる焦点位置が抽出され
る。また、電極パッド上のボンディング位置から上記焦
点位置までの距離を算出することで、半導体チップのエ
ッジ部とワイヤとのクリアランスを割り出すことができ
る。In the wire bonding inspection method of the present invention, a focus image of a wire is captured by a camera installed above a semiconductor chip, and a focus position serving as a measurement point is extracted by performing image processing on the focus image. You. Also, by calculating the distance from the bonding position on the electrode pad to the focal position, the clearance between the edge of the semiconductor chip and the wire can be determined.

【０００８】[0008]

【実施例】以下、本発明の実施例を図１〜図３に基づい
て詳細に説明する。まず、図１において、１は半導体チ
ップであり、この半導体チップ１はダイパッド２上に搭
載されている。半導体チップ１の上面にはその周縁に沿
って複数（図では一個だけ表示）の電極パッド３が形成
されている。また、これらの電極パッド３に対応して半
導体チップ１の周辺には複数のリード４が近接して配置
されている。そして、半導体チップ１上の電極パッド３
とリード４とはそれぞれワイヤ５によって接続されてい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. First, in FIG. 1, reference numeral 1 denotes a semiconductor chip, and the semiconductor chip 1 is mounted on a die pad 2. A plurality of (only one is shown in the figure) electrode pads 3 are formed on the upper surface of the semiconductor chip 1 along the periphery. Further, a plurality of leads 4 are arranged close to the periphery of the semiconductor chip 1 corresponding to the electrode pads 3. Then, the electrode pads 3 on the semiconductor chip 1
And the leads 4 are connected by wires 5 respectively.

【０００９】本発明に係わるワイヤボンディングの検査
方法は、半導体チップ１のエッジ１ａとワイヤ５とのク
リアランスＧを検査するための方法であり、この検査方
法について工程順に説明する。The wire bonding inspection method according to the present invention is a method for inspecting the clearance G between the edge 1a of the semiconductor chip 1 and the wire 5, and this inspection method will be described in the order of steps.

【００１０】はじめに第１の工程では、図１（ａ）に示
すように半導体チップ１の上方に設置したカメラ６によ
ってその半導体チップ１の上面とほぼ同じ高さに位置す
るワイヤ５の焦点画像を取り込む。ここで本実施例にお
いては、１００倍以上の高倍率レンズを備えしかもその
レンズ系に絞り機能を持たせたカメラ６を採用してお
り、このカメラ６の絞り機能によって焦点深度（焦点が
合っている範囲）を調整できるようになっている。因み
に、カメラ６の焦点深度を深く設定するとそれだけ明確
に映し出される画像の範囲が広くなり、反対に焦点深度
を浅く設定するとその分明確な画像の範囲は狭くなる。
このカメラ６の焦点深度は後述する画像処理や検出精度
を考慮して適宜設定するとよい。First, in a first step, as shown in FIG. 1A, a camera 6 installed above the semiconductor chip 1 forms a focused image of the wire 5 located at substantially the same height as the upper surface of the semiconductor chip 1. take in. In this embodiment, a camera 6 having a high-magnification lens of 100 times or more and having an aperture function in the lens system is employed. Range) can be adjusted. By the way, if the depth of focus of the camera 6 is set deeper, the range of the image projected clearly becomes wider, and if the depth of focus is set shallower, the range of the clear image becomes narrower accordingly.
The depth of focus of the camera 6 may be appropriately set in consideration of image processing and detection accuracy described later.

【００１１】上述したワイヤ５の焦点画像を取り込むた
めの具体的手段としては次のような方法が考えられる。
すなわち、カメラ６の焦点をまず半導体チップ１の上面
に正確に合わせ、続いてカメラ６とチップ上面との距離
を一定に保持したまま、そのカメラ６でもってワイヤ５
を映し出す。このとき明確に映し出される画像が、半導
体チップ１の上面とほぼ同じ高さに位置するワイヤ５の
焦点画像となる。The following method can be considered as a specific means for capturing the focus image of the wire 5 described above.
That is, the camera 6 is first focused accurately on the upper surface of the semiconductor chip 1, and then the camera 6 and the wire 5
Project. The image clearly projected at this time is the focus image of the wire 5 located at substantially the same height as the upper surface of the semiconductor chip 1.

【００１２】ワイヤ５の焦点画像はワイヤ５自体のルー
プ形状から図１（ｂ）のＳで示すように映し出される。
すなわち、半導体チップ１の上面と同一高さに位置する
部分が最も幅広に映し出され、この高さから上下方向に
離れるにしたがって徐々に像の幅が狭くなり、全体的に
は図のような菱形をなすようになる。このワイヤ５の焦
点画像Ｓはカメラ６の焦点深度Ｈの範囲内でとらえられ
るものであり、この範囲から外れた部分はカメラ６が高
倍率であることから像としては現れない。The focus image of the wire 5 is projected from the loop shape of the wire 5 itself as shown by S in FIG.
That is, the portion located at the same height as the upper surface of the semiconductor chip 1 is projected the widest, and the width of the image gradually decreases as the distance from the height in the vertical direction decreases, and the diamond shape as a whole Will be made. The focus image S of the wire 5 is captured within the range of the depth of focus H of the camera 6, and a portion outside this range does not appear as an image because the camera 6 has a high magnification.

【００１３】なお、図１（ａ）ではカメラ６を移動させ
てそれぞれの位置で半導体チップ１の上面とワイヤ５の
表面を映し出すようにしているが、被測定物に対してカ
メラ６が十分に大きい場合はいちいちカメラ６を移動さ
せなくてもワイヤ５の焦点画像Ｓを取り込むことができ
る。In FIG. 1A, the camera 6 is moved to project the upper surface of the semiconductor chip 1 and the surface of the wire 5 at each position. If it is large, the focus image S of the wire 5 can be captured without moving the camera 6 each time.

【００１４】次いで第２の工程では、ワイヤ５の焦点画
像Ｓに画像処理を施して、その焦点画像Ｓから焦点位置
Ｐ２を抽出する。被測定物である半導体チップ１やワイ
ヤ５には図示せぬ光源から光が照射されているため、ワ
イヤ５の表面を断面的に見た場合には図３に示すように
ワイヤ頂点Ｒに近いほど輝度が高くなる。また、カメラ
６の焦点は半導体チップ１の上面に合わせてあるので、
これと同一面上の箇所が最も輝度は高くなる。これらの
事実を踏まえて本実施例では、カメラ６により取り込ま
れた焦点画像Ｓの中で最も輝度が高い位置を焦点位置Ｐ
２として抽出している。これをワイヤ５の焦点画像Ｓで
説明すると、像の最も広い部分に位置するワイヤ５の頂
点が焦点位置Ｐ２となる。Next, in a second step, image processing is performed on the focus image S of the wire 5 and a focus position P2 is extracted from the focus image S. Since light is emitted from a light source (not shown) to the semiconductor chip 1 and the wire 5 as the device under test, when the surface of the wire 5 is viewed in cross section, it is close to the wire vertex R as shown in FIG. The higher the brightness, the higher the brightness. Since the camera 6 is focused on the upper surface of the semiconductor chip 1,
A portion on the same plane has the highest luminance. Based on these facts, in the present embodiment, the position having the highest luminance in the focus image S captured by the camera 6 is defined as the focus position P.
2 is extracted. This will be described with reference to the focus image S of the wire 5. The vertex of the wire 5 located at the widest part of the image is the focus position P2.

【００１５】続いて第３の工程では、電極パッド３上の
ボンディング位置Ｐ１から上述した焦点位置Ｐ２までの
距離Ｌを算出する。電極パッド３上のボンディング位置
Ｐ１については、例えばＸＹテーブル上に取り付けたカ
メラ６を移動させて半導体チップ１上のパターンを読み
取み、これに画像処理を施して予め個々のボンディング
位置Ｐ１を求めておく。こうして求めておいたボンディ
ング位置Ｐ１を基準にして、上述のように抽出されるワ
イヤ５の焦点位置Ｐ２までの距離Ｌをコンピュータにて
算出する。Subsequently, in a third step, a distance L from the bonding position P1 on the electrode pad 3 to the above-mentioned focal position P2 is calculated. For the bonding position P1 on the electrode pad 3, for example, the camera 6 mounted on an XY table is moved to read a pattern on the semiconductor chip 1, and image processing is performed on the pattern to obtain individual bonding positions P1 in advance. deep. Based on the bonding position P1 obtained in this way, the distance L to the focal position P2 of the wire 5 extracted as described above is calculated by a computer.

【００１６】このようにして求められる距離Ｌは半導体
チップ１のエッジ部１ａとワイヤ５とのクリアランスＧ
に対応する値である。すなわち、図１（ｂ）および図２
に示すようにワイヤ５のループ形状の違いによって電極
パッド３上のボンディング位置Ｐ１からワイヤ５の焦点
位置Ｐ２までの距離Ｌが小さくなると、それに準じて半
導体チップ１のエッジ部１ａとワイヤ５とのクリアラン
スＧも小さくなる。したがって本実施例の検査方法によ
りボンディング位置Ｐ１から焦点位置Ｐ２までの距離Ｌ
を求めることで、半導体チップ１のエッジ部１ａとワイ
ヤ５とのクリアランスＧを割り出すことができる。The distance L obtained in this way is the clearance G between the edge 1a of the semiconductor chip 1 and the wire 5.
Is the value corresponding to. That is, FIG. 1B and FIG.
When the distance L from the bonding position P1 on the electrode pad 3 to the focal position P2 of the wire 5 decreases due to the difference in the loop shape of the wire 5 as shown in FIG. 5, the edge 1a of the semiconductor chip 1 and the wire 5 The clearance G also becomes smaller. Therefore, according to the inspection method of this embodiment, the distance L from the bonding position P1 to the focal position P2 is determined.
, The clearance G between the edge portion 1a of the semiconductor chip 1 and the wire 5 can be determined.

【００１７】またこれ以外にも、ボンディング位置Ｐ１
から半導体チップ１のエッジ部１ａまでの距離とワイヤ
５の外形寸法とを予めコンピュータに入力しておき、上
述の検査方法により求めた距離Ｌからそれらの入力値を
減算することによってクリアランスＧを割り出すことも
可能である。In addition, the bonding position P1
Of the wire 5 to the edge 1a of the semiconductor chip 1 and the external dimensions of the wire 5 are input to a computer in advance, and the clearance G is calculated by subtracting these input values from the distance L obtained by the above-described inspection method. It is also possible.

【００１８】なお、本発明のワイヤボンディングの検査
方法は、ボールボンドやウエッジボンドなどの接続方式
に係わらず、いずれの場合おいても適用できることは言
うまでもない。It goes without saying that the wire bonding inspection method of the present invention can be applied in any case regardless of the connection method such as ball bonding or wedge bonding.

【００１９】[0019]

【発明の効果】以上、説明したように本発明のワイヤボ
ンディングの検査方法によれば、従来のように作業者の
目視に頼ることなく、画像処理や演算によって半導体チ
ップのエッジ部とワイヤとのクリアランスを割り出すこ
とができるため、繰り返しによる測定誤差や作業者間で
の判定基準のバラツキが解消されて検査精度の向上が図
られるとともに、半導体チップのエッジ部とワイヤとの
クリアランスを従来よりも短時間で検査することができ
るようになる。As described above, according to the wire bonding inspection method of the present invention, the edge portion of the semiconductor chip and the wire can be connected to each other by image processing or calculation without relying on the visual inspection of the operator as in the prior art. Since the clearance can be calculated, measurement errors due to repetition and variations in judgment standards among operators are eliminated, and inspection accuracy is improved.The clearance between the edge of the semiconductor chip and the wire is shorter than before. You will be able to inspect in time.

【図面の簡単な説明】[Brief description of the drawings]

【図１】検査方法の工程を説明するための図である。FIG. 1 is a view for explaining steps of an inspection method.

【図２】ループ形状の違いによる焦点位置の変動を説明
する図である。FIG. 2 is a diagram illustrating a change in a focal position due to a difference in a loop shape.

【図３】ワイヤ表面での輝度分布を説明する図である。FIG. 3 is a diagram illustrating a luminance distribution on a wire surface.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ３ 電極パッド ４ リード ５ ワイヤ ６ カメラ Ｇ クリアランス Ｌ 距離 Ｐ１ ボンディング位置 Ｐ２ 焦点位置 Reference Signs List 1 semiconductor chip 3 electrode pad 4 lead 5 wire 6 camera G clearance L distance P1 bonding position P2 focal position

フロントページの続き (56)参考文献 特開 平２−247510（ＪＰ，Ａ) 特開 昭61−59845（ＪＰ，Ａ) 特開 平２−82366（ＪＰ，Ａ) 特開 平４−277645（ＪＰ，Ａ) 特開 昭63−304144（ＪＰ，Ａ) 特開 昭61−148828（ＪＰ，Ａ) 特開 平５−312531（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) G01B 11/00 - 11/30 Continuation of the front page (56) References JP-A-2-247510 (JP, A) JP-A-61-59845 (JP, A) JP-A-2-82366 (JP, A) JP-A-4-277645 (JP) , A) JP-A-63-304144 (JP, A) JP-A-61-148828 (JP, A) JP-A-5-312531 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB G01B 11/00-11/30

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体チップの上面に形成された電極パ
ッドと該半導体チップの周辺に配置されたリードとをワ
イヤにて接続するワイヤボンディングにおいて、前記半
導体チップのエッジ部と前記ワイヤとのクリアランスを
検査するためのワイヤボンディングの検査方法であっ
て、 前記半導体チップの上方に設置したカメラにより該半導
体チップの上面とほぼ同じ高さに位置であって前記カメ
ラの焦点深度の範囲内でとらえられる前記ワイヤの焦点
画像を取り込む工程と、 前記焦点画像に画像処理を施して該焦点画像から焦点位
置を抽出する工程と、 前記電極パッド上の予め求めておいたボンディング位置
から前記焦点位置までの距離を算出する工程とからなる
ことを特徴とするワイヤボンディングの検査方法。In a wire bonding for connecting an electrode pad formed on an upper surface of a semiconductor chip to a lead arranged around the semiconductor chip by a wire, a clearance between an edge portion of the semiconductor chip and the wire is reduced. A method for inspecting wire bonding for inspection, wherein the camera is positioned at substantially the same height as the upper surface of the semiconductor chip by a camera installed above the semiconductor chip, and is captured within a depth of focus of the camera. Capturing a focus image of the wire; performing image processing on the focus image to extract a focus position from the focus image; and determining a distance from the previously determined bonding position on the electrode pad to the focus position. Calculating the wire bonding. 【請求項２】 前記半導体チップの上面に焦点を合わせ
たカメラで前記ワイヤを映し出すことにより前記焦点画
像を取り込み可能としたことを特徴とする請求項１記載
のワイヤボンディングの検査方法。2. The wire bonding inspection method according to claim 1, wherein the focus image can be captured by projecting the wire with a camera focused on the upper surface of the semiconductor chip. 【請求項３】 被測定物に光源から光が照射されてお
り、前記カメラにより取り込まれた前記焦点画像の中で
最も輝度の高い位置を前記焦点位置として抽出すること
を特徴とする請求項１記載のワイヤボンディングの検査
方法。3. An object to be measured is irradiated with light from a light source, and a position having the highest luminance in the focus image captured by the camera is extracted as the focus position. The inspection method of the wire bonding described in the above.
JP25719092A 1992-08-31 1992-08-31 Inspection method of wire bonding Expired - Lifetime JP3312395B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25719092A JP3312395B2 (en) 1992-08-31 1992-08-31 Inspection method of wire bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25719092A JP3312395B2 (en) 1992-08-31 1992-08-31 Inspection method of wire bonding

Publications (2)

Publication Number Publication Date
JPH0682226A JPH0682226A (en) 1994-03-22
JP3312395B2 true JP3312395B2 (en) 2002-08-05

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Application Number Title Priority Date Filing Date
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JP (1) JP3312395B2 (en)

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US8244145B2 (en) 2007-08-29 2012-08-14 Ricoh Company, Ltd. Image forming apparatus including image processing member determined by method of evaluating distribution of adhesion forces of toner thereto

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