JPH0682226A - Inspection method of wire bonding - Google Patents

Inspection method of wire bonding

Info

Publication number
JPH0682226A
JPH0682226A JP4257190A JP25719092A JPH0682226A JP H0682226 A JPH0682226 A JP H0682226A JP 4257190 A JP4257190 A JP 4257190A JP 25719092 A JP25719092 A JP 25719092A JP H0682226 A JPH0682226 A JP H0682226A
Authority
JP
Japan
Prior art keywords
wire
semiconductor chip
focus
camera
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4257190A
Other languages
Japanese (ja)
Other versions
JP3312395B2 (en
Inventor
Kikuo Goto
喜久雄 後藤
Hisataka Izawa
久隆 伊沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP25719092A priority Critical patent/JP3312395B2/en
Publication of JPH0682226A publication Critical patent/JPH0682226A/en
Application granted granted Critical
Publication of JP3312395B2 publication Critical patent/JP3312395B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Image Analysis (AREA)

Abstract

PURPOSE:To obtain an inspection method of a wire bonding which allows clearance between an edge part of a semiconductor chip and a wire to be accurately inspected in a short time. CONSTITUTION:This inspection method of a wire bonding is for inspection of a clearance G between an edge part 1a of a semiconductor chip 1 and a wire 5. A focus image S of the wire 5 which is located at a height almost the same as the top surface of a semiconductor chip 1 is picked up with a camera 6 set above the semiconductor chip 1. The focus image S under-goes an image processing to extract a focus position P2 from the focus image S to calculate a distance to the focus position P2 from a bonding position on an electrode pad 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ワイヤボンディングの
検査方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding inspection method.

【０００２】[0002]

【従来の技術】ワイヤボンディングの検査項目の中に
は、半導体チップのエッジ部とワイヤとのクリアランス
を検査する項目があり、この検査を行うことによってワ
イヤが半導体チップのエッジ部に接触して起こる、いわ
ゆるエッジショートや、モールド時にパッケージからワ
イヤがはみ出すなどの不良発生を未然に回避することが
できる。2. Description of the Related Art Among wire bonding inspection items, there is an item for inspecting a clearance between an edge portion of a semiconductor chip and a wire. This inspection causes the wire to come into contact with the edge portion of the semiconductor chip. It is possible to avoid occurrence of defects such as so-called edge short-circuiting and wires protruding from the package during molding.

【０００３】従来、この種のワイヤボンディングの検査
方法としては、作業者が実体顕微鏡を覗きながら半導体
チップのエッジ部とワイヤとのクリアランスを測定する
のが一般的であった。この方法では、顕微鏡に取り付け
られた目盛りを基準に上記クリアランスを測定し、その
測定値が所定範囲内にあるか否かによって良品、不良品
の判定をしていた。Conventionally, as a method for inspecting this kind of wire bonding, it has been general for an operator to measure a clearance between an edge portion of a semiconductor chip and a wire while looking through a stereoscopic microscope. In this method, the clearance is measured with reference to a scale attached to a microscope, and whether the measured value is within a predetermined range or not is used to determine whether the product is a good product or a defective product.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら上記従来
の目視による検査方法では、短時間で検査できるという
利点はあるものの、繰り返しによる測定誤差や作業者間
での判定基準のバラツキによって、半導体チップのエッ
ジ部とワイヤとのクリアランスを精度良く検査すること
ができず、信頼性に欠けるといった問題があった。However, although the above-mentioned conventional visual inspection method has the advantage that it can be inspected in a short time, the edge of the semiconductor chip may be damaged due to repeated measurement errors and variations in judgment criteria among workers. There is a problem in that the clearance between the wire and the wire cannot be inspected with high precision, resulting in lack of reliability.

【０００５】本発明は、上記問題を解決するためになさ
れたもので、半導体チップのエッジ部とワイヤとのクリ
アランスを短時間でしかも精度良く検査することができ
るワイヤボンディングの検査方法を提供することを目的
とする。The present invention has been made to solve the above problems, and provides a wire bonding inspection method capable of accurately inspecting the clearance between the edge portion of a semiconductor chip and a wire in a short time. With the goal.

【０００６】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、半導体チップの上面に形
成された電極パッドと該半導体チップの周辺に配置され
たリードとをワイヤにて接続するワイヤボンディングに
おいて、半導体チップのエッジ部とワイヤとのクリアラ
ンスを検査するためのワイヤボンディングの検査方法で
あって、半導体チップの上方に設置したカメラにより該
半導体チップの上面とほぼ同じ高さに位置するワイヤの
焦点画像を取り込む工程と、この焦点画像に画像処理を
施して該焦点画像から焦点位置を抽出する工程と、電極
パッド上のボンディング位置から焦点位置までの距離を
算出する工程とからなるものである。また、半導体チッ
プの上面に焦点を合わせたカメラでワイヤを映し出すこ
とにより上記焦点画像を取り込み可能としたものであ
る。さらに、カメラにより取り込まれた焦点画像の中で
最も輝度の高い位置を焦点位置として抽出するようにし
たものである。SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, in which electrode pads formed on the upper surface of a semiconductor chip and leads arranged around the semiconductor chip are connected to wires. A wire bonding inspection method for inspecting a clearance between an edge portion of a semiconductor chip and a wire in wire bonding for connection by using a camera installed above the semiconductor chip so that the height is substantially the same as the upper surface of the semiconductor chip. A step of capturing a focus image of the wire positioned at, a step of performing image processing on the focus image to extract a focus position from the focus image, and a step of calculating a distance from the bonding position on the electrode pad to the focus position. It consists of Further, the focus image can be captured by projecting a wire with a camera focused on the upper surface of the semiconductor chip. Furthermore, the position with the highest brightness in the focus image captured by the camera is extracted as the focus position.

【０００７】[0007]

【作用】本発明のワイヤボンディングの検査方法におい
ては、半導体チップの上方に設置したカメラによってワ
イヤの焦点画像が取り込まれ、この焦点画像に画像処理
を施すことによって測定点となる焦点位置が抽出され
る。また、電極パッド上のボンディング位置から上記焦
点位置までの距離を算出することで、半導体チップのエ
ッジ部とワイヤとのクリアランスを割り出すことができ
る。According to the wire bonding inspection method of the present invention, the focus image of the wire is captured by the camera installed above the semiconductor chip, and the focus position serving as the measurement point is extracted by performing image processing on the focus image. It Further, by calculating the distance from the bonding position on the electrode pad to the focal position, the clearance between the edge portion of the semiconductor chip and the wire can be calculated.

【０００８】[0008]

【実施例】以下、本発明の実施例を図１〜図３に基づい
て詳細に説明する。まず、図１において、１は半導体チ
ップであり、この半導体チップ１はダイパッド２上に搭
載されている。半導体チップ１の上面にはその周縁に沿
って複数（図では一個だけ表示）の電極パッド３が形成
されている。また、これらの電極パッド３に対応して半
導体チップ１の周辺には複数のリード４が近接して配置
されている。そして、半導体チップ１上の電極パッド３
とリード４とはそれぞれワイヤ５によって接続されてい
る。Embodiments of the present invention will be described below in detail with reference to FIGS. First, in FIG. 1, 1 is a semiconductor chip, and this semiconductor chip 1 is mounted on a die pad 2. A plurality of (only one is shown in the figure) electrode pads 3 are formed on the upper surface of the semiconductor chip 1 along the periphery thereof. Further, a plurality of leads 4 are arranged in proximity to the periphery of the semiconductor chip 1 so as to correspond to these electrode pads 3. Then, the electrode pad 3 on the semiconductor chip 1
And the lead 4 are connected by a wire 5, respectively.

【０００９】本発明に係わるワイヤボンディングの検査
方法は、半導体チップ１のエッジ１ａとワイヤ５とのク
リアランスＧを検査するための方法であり、この検査方
法について工程順に説明する。The wire bonding inspection method according to the present invention is a method for inspecting the clearance G between the edge 1a of the semiconductor chip 1 and the wire 5, and this inspection method will be described in the order of steps.

【００１０】はじめに第１の工程では、図１（ａ）に示
すように半導体チップ１の上方に設置したカメラ６によ
ってその半導体チップ１の上面とほぼ同じ高さに位置す
るワイヤ５の焦点画像を取り込む。ここで本実施例にお
いては、１００倍以上の高倍率レンズを備えしかもその
レンズ系に絞り機能を持たせたカメラ６を採用してお
り、このカメラ６の絞り機能によって焦点深度（焦点が
合っている範囲）を調整できるようになっている。因み
に、カメラ６の焦点深度を深く設定するとそれだけ明確
に映し出される画像の範囲が広くなり、反対に焦点深度
を浅く設定するとその分明確な画像の範囲は狭くなる。
このカメラ６の焦点深度は後述する画像処理や検出精度
を考慮して適宜設定するとよい。First, in the first step, as shown in FIG. 1A, a camera 6 installed above the semiconductor chip 1 is used to obtain a focus image of the wire 5 positioned substantially at the same height as the upper surface of the semiconductor chip 1. take in. Here, in the present embodiment, a camera 6 having a high magnification lens of 100 times or more and having a lens system having a diaphragm function is employed. The range) can be adjusted. By the way, if the depth of focus of the camera 6 is set deep, the range of the image clearly displayed is widened, and conversely, if the depth of focus is set shallow, the range of the clear image is narrowed accordingly.
The depth of focus of the camera 6 may be set appropriately in consideration of image processing and detection accuracy described later.

【００１１】上述したワイヤ５の焦点画像を取り込むた
めの具体的手段としては次のような方法が考えられる。
すなわち、カメラ６の焦点をまず半導体チップ１の上面
に正確に合わせ、続いてカメラ６とチップ上面との距離
を一定に保持したまま、そのカメラ６でもってワイヤ５
を映し出す。このとき明確に映し出される画像が、半導
体チップ１の上面とほぼ同じ高さに位置するワイヤ５の
焦点画像となる。The following method can be considered as a specific means for capturing the above-mentioned focus image of the wire 5.
That is, the focus of the camera 6 is first accurately adjusted to the upper surface of the semiconductor chip 1, and then the wire 5 is held by the camera 6 while keeping the distance between the camera 6 and the upper surface of the chip constant.
Is projected. The image clearly displayed at this time is a focus image of the wire 5 positioned at substantially the same height as the upper surface of the semiconductor chip 1.

【００１２】ワイヤ５の焦点画像はワイヤ５自体のルー
プ形状から図１（ｂ）のＳで示すように映し出される。
すなわち、半導体チップ１の上面と同一高さに位置する
部分が最も幅広に映し出され、この高さから上下方向に
離れるにしたがって徐々に像の幅が狭くなり、全体的に
は図のような菱形をなすようになる。このワイヤ５の焦
点画像Ｓはカメラ６の焦点深度Ｈの範囲内でとらえられ
るものであり、この範囲から外れた部分はカメラ６が高
倍率であることから像としては現れない。The focus image of the wire 5 is projected from the loop shape of the wire 5 itself as indicated by S in FIG. 1 (b).
That is, the portion located at the same height as the upper surface of the semiconductor chip 1 is projected widest, and the width of the image gradually narrows as it goes away from this height in the vertical direction. Will come to The focus image S of the wire 5 is captured within the range of the depth of focus H of the camera 6, and a portion outside this range does not appear as an image because the camera 6 has a high magnification.

【００１３】なお、図１（ａ）ではカメラ６を移動させ
てそれぞれの位置で半導体チップ１の上面とワイヤ５の
表面を映し出すようにしているが、被測定物に対してカ
メラ６が十分に大きい場合はいちいちカメラ６を移動さ
せなくてもワイヤ５の焦点画像Ｓを取り込むことができ
る。In FIG. 1 (a), the camera 6 is moved so that the upper surface of the semiconductor chip 1 and the surface of the wire 5 are projected at each position, but the camera 6 is sufficient for the object to be measured. If it is large, the focus image S of the wire 5 can be captured without moving the camera 6 one by one.

【００１４】次いで第２の工程では、ワイヤ５の焦点画
像Ｓに画像処理を施して、その焦点画像Ｓから焦点位置
Ｐ２を抽出する。被測定物である半導体チップ１やワイ
ヤ５には図示せぬ光源から光が照射されているため、ワ
イヤ５の表面を断面的に見た場合には図３に示すように
ワイヤ頂点Ｒに近いほど輝度が高くなる。また、カメラ
６の焦点は半導体チップ１の上面に合わせてあるので、
これと同一面上の箇所が最も輝度は高くなる。これらの
事実を踏まえて本実施例では、カメラ６により取り込ま
れた焦点画像Ｓの中で最も輝度が高い位置を焦点位置Ｐ
２として抽出している。これをワイヤ５の焦点画像Ｓで
説明すると、像の最も広い部分に位置するワイヤ５の頂
点が焦点位置Ｐ２となる。Next, in the second step, the focus image S of the wire 5 is subjected to image processing, and the focus position P2 is extracted from the focus image S. Since the semiconductor chip 1 or the wire 5 as the DUT is irradiated with light from a light source (not shown), when the surface of the wire 5 is viewed in cross section, it is close to the wire vertex R as shown in FIG. The higher the brightness, the higher the brightness. Further, since the focus of the camera 6 is aligned with the upper surface of the semiconductor chip 1,
The brightness is highest in the same plane. In consideration of these facts, in the present embodiment, the position of the highest brightness in the focus image S captured by the camera 6 is set to the focus position P.
It is extracted as 2. Explaining this with the focus image S of the wire 5, the vertex of the wire 5 located in the widest part of the image is the focus position P2.

【００１５】続いて第３の工程では、電極パッド３上の
ボンディング位置Ｐ１から上述した焦点位置Ｐ２までの
距離Ｌを算出する。電極パッド３上のボンディング位置
Ｐ１については、例えばＸＹテーブル上に取り付けたカ
メラ６を移動させて半導体チップ１上のパターンを読み
取み、これに画像処理を施して予め個々のボンディング
位置Ｐ１を求めておく。こうして求めておいたボンディ
ング位置Ｐ１を基準にして、上述のように抽出されるワ
イヤ５の焦点位置Ｐ２までの距離Ｌをコンピュータにて
算出する。Then, in a third step, the distance L from the bonding position P1 on the electrode pad 3 to the above-mentioned focal position P2 is calculated. Regarding the bonding position P1 on the electrode pad 3, for example, the camera 6 mounted on the XY table is moved to read the pattern on the semiconductor chip 1, and image processing is performed on this to obtain the individual bonding position P1 in advance. deep. With the bonding position P1 thus obtained as a reference, the distance L to the focus position P2 of the wire 5 extracted as described above is calculated by the computer.

【００１６】このようにして求められる距離Ｌは半導体
チップ１のエッジ部１ａとワイヤ５とのクリアランスＧ
に対応する値である。すなわち、図１（ｂ）および図２
に示すようにワイヤ５のループ形状の違いによって電極
パッド３上のボンディング位置Ｐ１からワイヤ５の焦点
位置Ｐ２までの距離Ｌが小さくなると、それに準じて半
導体チップ１のエッジ部１ａとワイヤ５とのクリアラン
スＧも小さくなる。したがって本実施例の検査方法によ
りボンディング位置Ｐ１から焦点位置Ｐ２までの距離Ｌ
を求めることで、半導体チップ１のエッジ部１ａとワイ
ヤ５とのクリアランスＧを割り出すことができる。The distance L thus obtained is the clearance G between the edge portion 1a of the semiconductor chip 1 and the wire 5.
Is a value corresponding to. That is, FIG. 1 (b) and FIG.
When the distance L from the bonding position P1 on the electrode pad 3 to the focal position P2 of the wire 5 becomes small due to the difference in the loop shape of the wire 5 as shown in FIG. The clearance G also becomes smaller. Therefore, according to the inspection method of this embodiment, the distance L from the bonding position P1 to the focus position P2 is L.
The clearance G between the edge portion 1a of the semiconductor chip 1 and the wire 5 can be calculated by obtaining

【００１７】またこれ以外にも、ボンディング位置Ｐ１
から半導体チップ１のエッジ部１ａまでの距離とワイヤ
５の外形寸法とを予めコンピュータに入力しておき、上
述の検査方法により求めた距離Ｌからそれらの入力値を
減算することによってクリアランスＧを割り出すことも
可能である。In addition to this, the bonding position P1
The distance from the semiconductor chip 1 to the edge portion 1a of the semiconductor chip 1 and the external dimensions of the wire 5 are input to the computer in advance, and the clearance G is calculated by subtracting those input values from the distance L obtained by the above-described inspection method. It is also possible.

【００１８】なお、本発明のワイヤボンディングの検査
方法は、ボールボンドやウエッジボンドなどの接続方式
に係わらず、いずれの場合おいても適用できることは言
うまでもない。Needless to say, the wire bonding inspection method of the present invention can be applied in any case regardless of the connection method such as ball bonding or wedge bonding.

【００１９】[0019]

【発明の効果】以上、説明したように本発明のワイヤボ
ンディングの検査方法によれば、従来のように作業者の
目視に頼ることなく、画像処理や演算によって半導体チ
ップのエッジ部とワイヤとのクリアランスを割り出すこ
とができるため、繰り返しによる測定誤差や作業者間で
の判定基準のバラツキが解消されて検査精度の向上が図
られるとともに、焦点合わせのための時間が短縮される
ことから従来よりも検査時間が短時間で済むようにな
る。As described above, according to the wire bonding inspection method of the present invention, the edge portion of the semiconductor chip and the wire can be processed by image processing and calculation without relying on the operator's visual inspection as in the prior art. Since the clearance can be calculated, measurement errors due to repetition and variations in judgment criteria between workers are eliminated, and inspection accuracy is improved, and the time for focusing is shortened. Inspection time will be short.

【図面の簡単な説明】[Brief description of drawings]

【図１】検査方法の工程を説明するための図である。FIG. 1 is a diagram for explaining steps of an inspection method.

【図２】ループ形状の違いによる焦点位置の変動を説明
する図である。FIG. 2 is a diagram illustrating a change in focus position due to a difference in loop shape.

【図３】ワイヤ表面での輝度分布を説明する図である。FIG. 3 is a diagram illustrating a luminance distribution on a wire surface.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ３ 電極パッド ４ リード ５ ワイヤ ６ カメラ Ｇ クリアランス Ｌ 距離 Ｐ１ ボンディング位置 Ｐ２ 焦点位置 1 semiconductor chip 3 electrode pad 4 lead 5 wire 6 camera G clearance L distance P1 bonding position P2 focus position

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップの上面に形成された電極パ
ッドと該半導体チップの周辺に配置されたリードとをワ
イヤにて接続するワイヤボンディングにおいて、 前記半導体チップのエッジ部と前記ワイヤとのクリアラ
ンスを検査するためのワイヤボンディングの検査方法で
あって、 前記半導体チップの上方に設置したカメラにより該半導
体チップの上面とほぼ同じ高さに位置する前記ワイヤの
焦点画像を取り込む工程と、 前記焦点画像に画像処理を施して該焦点画像から焦点位
置を抽出する工程と、 前記電極パッド上のボンディング位置から前記焦点位置
までの距離を算出する工程とからなることを特徴とする
ワイヤボンディングの検査方法。1. In wire bonding for connecting an electrode pad formed on an upper surface of a semiconductor chip and a lead arranged around the semiconductor chip with a wire, a clearance between an edge portion of the semiconductor chip and the wire is provided. A method of inspecting wire bonding for inspecting, comprising the step of capturing a focus image of the wire located at substantially the same height as the upper surface of the semiconductor chip by a camera installed above the semiconductor chip, A wire bonding inspection method comprising: a step of performing image processing to extract a focus position from the focus image; and a step of calculating a distance from the bonding position on the electrode pad to the focus position. 【請求項２】 前記半導体チップの上面に焦点を合わせ
たカメラで前記ワイヤを映し出すことにより前記焦点画
像を取り込み可能としたことを特徴とする請求項１記載
のワイヤボンディングの検査方法。2. The method for inspecting wire bonding according to claim 1, wherein the focus image can be captured by projecting the wire with a camera focused on the upper surface of the semiconductor chip. 【請求項３】 前記カメラにより取り込まれた前記焦点
画像の中で最も輝度の高い位置を前記焦点位置として抽
出することを特徴とする請求項１記載のワイヤボンディ
ングの検査方法。3. The method for inspecting wire bonding according to claim 1, wherein a position having the highest brightness in the focus image captured by the camera is extracted as the focus position.
JP25719092A 1992-08-31 1992-08-31 Inspection method of wire bonding Expired - Lifetime JP3312395B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25719092A JP3312395B2 (en) 1992-08-31 1992-08-31 Inspection method of wire bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25719092A JP3312395B2 (en) 1992-08-31 1992-08-31 Inspection method of wire bonding

Publications (2)

Publication Number Publication Date
JPH0682226A true JPH0682226A (en) 1994-03-22
JP3312395B2 JP3312395B2 (en) 2002-08-05

Family

ID=17302933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25719092A Expired - Lifetime JP3312395B2 (en) 1992-08-31 1992-08-31 Inspection method of wire bonding

Country Status (1)

Country Link
JP (1) JP3312395B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8244145B2 (en) 2007-08-29 2012-08-14 Ricoh Company, Ltd. Image forming apparatus including image processing member determined by method of evaluating distribution of adhesion forces of toner thereto

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8244145B2 (en) 2007-08-29 2012-08-14 Ricoh Company, Ltd. Image forming apparatus including image processing member determined by method of evaluating distribution of adhesion forces of toner thereto

Also Published As

Publication number Publication date
JP3312395B2 (en) 2002-08-05

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