JP3297962B2 - Active matrix display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device. More specifically, the present invention relates to a technique for removing an oblate defect appearing at a lateral end of a screen of an active matrix display device driven in a dot-sequential manner.

[0002]

2. Description of the Related Art A general structure of a conventional active matrix display device will be briefly described with reference to FIG. The active matrix display device has a plurality of gate lines X arranged in rows, a plurality of data lines Y arranged in columns, and a plurality of pixels PXL provided at respective intersections of the two. The pixels PXL are composed of, for example, fine liquid crystal cells and arranged in a matrix to form a display area. Individual pixel PXL
In order to drive this, a thin film transistor Tr is integrally formed. Further, a vertical scanning circuit 101 is provided, which sequentially scans each gate line X vertically and selects one row of pixels PXL every horizontal period. Further, the horizontal scanning circuit 10
2 and sequentially scans each data line Y within one horizontal period, samples the video signal Vsig, and writes the video signal Vsig in the dot-sequentially to the selected one row of pixels PXL. More specifically, each data line Y is connected to a video line 103 via a horizontal switch HSW, and receives a video signal Vsig from outside. The horizontal scanning circuit 102 sequentially performs sampling pulses φ _H1 , φ _H2 , φ _H3 ,
.., Φ _HN are output, and the horizontal switches HSW are sequentially driven to open and close to sample the video signal Vsig on each data line Y.

[0003]

FIG. 9 shows waveforms of sampling pulses sequentially output from the horizontal scanning circuit 102 shown in FIG. The sampling pulse width τ _H is determined according to the sampling time assigned to each data line Y. As the definition of the active matrix display device is advanced, the number of pixels is significantly increased, and the writing time per dot is significantly reduced.
Also, in an active matrix display device compatible with HDTV, the writing time per dot is similarly shortened in order to speed up line scanning. Correspondingly, the sampling pulse width τ _H becomes extremely narrow. For example, horizontal 470
In an NTSC half-line type active matrix display device for pixels, the sampling pulse width is τ _H = 50.
μs / 470/3 (RGB) = about 320 nsec.
When this becomes 800 pixels horizontally, τ _H = 188 nsec. Further, when driving at double speed with a full line configuration, τ _H = 9
The sampling time is as short as 4 nsec. When the sampling pulse width is reduced in this manner, it becomes difficult to shape the waveform, and the configuration of the horizontal scanning circuit is complicated and the design margin is narrowed. In addition, since a sufficient writing time of the video signal cannot be obtained, a burden is imposed on the liquid crystal panel side, and various restrictions are imposed on the design.

[0004] In order to cope with the shortening of the sampling pulse width τ _H , for example, a method disclosed in Japanese Patent Publication No. 1-37911 has been proposed. As shown in FIG. 10, the sampling pulses φ _H1 , φ _H2 , φ _H3 , φ _H4,. That is, a method of shifting while simultaneously selecting a plurality of data lines. For example, FIG.
As shown in (1), when four data lines are simultaneously selected, the sampling pulse width is τ _H = 4 × 188 nsec = 750 nsec in the case of 800 horizontal pixels. This method can reduce the design burden on the driving side of the horizontal scanning circuit and the like and on the liquid crystal panel side.

However, the method of sequentially shifting a plurality of data lines while simultaneously selecting a plurality of data lines has a problem that an oblate defect 105 is generated at the end of the display area 104 constituting the screen in the horizontal scanning direction, as shown in FIG. is there. For example, in the normally white mode, the obi-like defect 10
5 appears darker than the normal part. The obscured defect 105 is caused by the fact that the overlapping of the sampling pulse is released at the end of the horizontal scanning, and the driving conditions are different from those of other normal regions.

[0006]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to eliminate an obviate defect appearing at the end in the horizontal scanning direction in the dot sequential driving of an active matrix display device. The following measures were taken to achieve this purpose. That is, the active matrix display device according to the present invention has a basic configuration in which a plurality of gate lines wired in a row, a plurality of data lines wired in a column, and a display area provided at each intersection of the two. And a plurality of pixels. Further, a vertical scanning circuit and a horizontal scanning circuit are provided as peripheral portions. The vertical scanning circuit sequentially vertically scans each gate line and selects one row of pixels every horizontal period. On the other hand, the horizontal scanning circuit sequentially scans each data line within one horizontal period, samples a video signal, and writes the video signal to the selected pixels of one row in a dot-sequential manner. As a characteristic feature of the present invention, the data line is divided into a real data line wired in the display area and a dummy data line wired outside the display area and intersecting the end side of the gate line. The horizontal scanning circuit performs horizontal scanning at a sampling timing overlapping a plurality of actual data lines over a plurality of lines, and further adds horizontal scanning to a dummy data line at an overlapping sampling timing continuously.
In this case, the dummy data lines are wired at least for the number of lines that are simultaneously horizontally scanned at the overlapped sampling timing. Dummy pixels are also assigned to this dummy data line. Alternatively, the pixels may be removed from the dummy data line.

[0007]

According to the present invention, a dummy data line is added outside the display area adjacent to the last part of the actual data line wired in the display area. The horizontal scanning circuit performs horizontal scanning continuously over the actual data lines and the dummy data lines. Therefore, even when reaching the end of the display area, the overlapping sampling timing over a plurality of lines with respect to the actual data line is maintained as it is, and a normal image display is performed, so that no obi defect occurs. Further, when the horizontal scanning reaches the dummy data line, the overlapped sampling timing is released, and the display state changes in some cases. However, since the dummy data lines are arranged outside the display area, they do not appear on the screen.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the active matrix display device according to the present invention. As shown, the present active matrix display device includes a plurality of gate lines X arranged in rows and a plurality of data lines Y arranged in columns. Further, pixels PXL are arranged in a matrix at the intersection of the two to form a display area 1. The pixel PXL is composed of, for example, a liquid crystal cell having a fine structure. In this embodiment, a thin film transistor Tr is provided to drive a pixel PXL constituted by a liquid crystal cell. Each thin film transistor Tr has a source electrode connected to the corresponding data line Y, a gate electrode connected to the corresponding gate line X, and a drain electrode connected to the corresponding pixel PXL.
Connected to.

A vertical scanning circuit 2 and a horizontal scanning circuit 3 are provided around the display area 1 described above. The vertical scanning circuit 2 sequentially vertically scans each gate line Y, conducts the thin film transistors Tr described above, and selects one row of pixels PXL every horizontal period. On the other hand, the horizontal scanning circuit 3 sequentially scans each data line Y within one horizontal period, samples the video signal Vsig, and writes the video signal Vsig to the selected one row of pixels PXL in dot sequence. Specifically, each data line Y is connected to the video line 4 via the horizontal switch HSW and receives the supply of the video signal Vsig.
The horizontal scanning circuit 3 sequentially outputs the sampling pulse φ and its inverted pulse, controls the opening and closing of each horizontal switch HSW, and performs the sampling of the video signal Vsig described above. Video signal V sampled on each data line Y
The sig is written to one row of pixels PXL via the thin-film transistor Tr in the ON state. Thereafter, the thin film transistor Tr is turned off and the written video signal Vs
ig are held until the next frame.

As a feature of the present invention, the data lines are the actual data lines Y1, Y2,.
YL and a dummy data line Y arranged outside the display area 1
D1, YD2, YD3, and YD4. These dummy data lines cross the end side of the gate line X. In this embodiment, the pixel PXL and the thin film transistor Tr are omitted from the dummy data line.
However, the present invention is not limited to this,
In order to completely equalize the driving conditions, a dummy pixel and a thin film transistor may be assigned to a dummy data line. On the other hand, the horizontal scanning circuit 3 scans not only the actual data lines but also the dummy data lines. That is, the horizontal scanning circuit 3 performs horizontal scanning with respect to the actual data lines Y1, Y2,..., YL at a sampling timing overlapping a plurality of lines (four in this example). Further, the dummy data lines YD1, YD2, YD3, Y
Horizontal scanning is added to D4 at the same overlapping sampling timing. In this case, the dummy data lines are wired at least for the number of horizontal scans simultaneously performed at the overlapped sampling timing. That is, in this embodiment, at least four dummy data lines are provided. More specifically, the horizontal scanning circuit 3 includes actual data lines Y1, Y2,.
The sampling pulses φ ₁ , φ ₂ ,..., Φ _L and their inverted pulses are sequentially output to the horizontal switch HSW connected to YL. Further continuously, the dummy data line YD
1, YD2, YD3, and YD4, the sampling pulses φ _D1 , φ _D2 ,.
φ _D3 , φ _D4 and their inversion pulses are sequentially applied. In this example, since a transmission gate made of CMOS is used as the horizontal switch HSW, an inversion pulse is also applied.

Next, the operation of the active matrix display device shown in FIG. 1 will be described in detail with reference to FIG. As shown in the timing chart of the figure, a sampling pulse is output at a sampling timing overlapping four lines with respect to the actual data line, and the horizontal scanning (actual scanning) is performed on the display area 1. In the timing chart, only five pulses until the final actual sampling pulse φ _L are shown for easy understanding. In the present embodiment, the dummy sampling pulses φ _D1 , φ _D2 , φ _D3 , φ _D4 are sequentially output at a timing following the rising of the sampling pulse φ _{L and} also overlapping the dummy data line, and the outside of the display area 1 is output. Perform horizontal scanning (dummy scanning). When the sampling pulse φ is sequentially output at the overlapping timing as described above, the potential fluctuation of the gate line Y occurs due to the capacitive coupling generated at the intersection of the gate line Y and the data line X. Since the capacitance coupling is continuously received in accordance with the rise of each sampling pulse φ, the potential of the gate line X continues to fluctuate until the final dummy sampling pulse _φD4 rises. After the last dummy sampling pulse φ _D4 rises, the capacitance of the gate line Y is attenuated toward the ground level because the capacitance coupling is not received.

On the other hand, when each sampling pulse φ falls, the horizontal switch HSW shifts from the on state to the off state. When the HSW is closed, the potential fluctuation of the gate line jumps into each signal line Y due to the above-described capacitance coupling. As a result, when attenuation starts after the potential fluctuation of the gate line has subsided, this affects the potential of the signal line X through the capacitive coupling, and the attenuation also occurs. As understood from the timing chart of FIG. 2, the potentials V _L-4 , V _L-3 , V _L-2 ,
Since the corresponding HSWs of _VL-1 and _VL are already in the OFF state, the potential fluctuations of the gate lines are alleviated after the potential fluctuations of the gate lines have subsided, and finally a voltage drop occurs by ΔV0.
Therefore, the voltage drop ΔV is applied to all the actual data lines.
Since 0 is equal, unevenness of the display density does not occur. In contrast,
For example the corresponding dummy sampling pulse phi _D1 falls with a delay by one clock cycle after the potential fluctuation of the gate line subsided for the first dummy data line YD1. Since the potential V _D1 of the dummy data lines YD1 in synchronization with the time falling the trailing starts attenuation, final voltage drop ΔV1 is smaller than Delta] V0. Similarly, since the potential V _D2 of the second dummy data line YD ₂ is delayed by one more clock and starts to decay, the final voltage drop ΔV 2 is further reduced. As described above, the voltage drops of the dummy data lines are different from each other, and the display density fluctuates. However, since the dummy data line is located outside the display area 1, it does not affect the actual image. As described above, the horizontal scanning circuit 3 performs horizontal scanning by four pixels more than the effective display area 1. Also, four dummy data lines are provided in the same arrangement as the effective display area 1 including the HSW. By providing four dummy data lines, the potential fluctuation of the gate line continues for four pixels even after passing the effective display area 1. Therefore, the swing of the signal line included in the display area 1 does not change abruptly only at the end portion. In this embodiment, four signal lines are scanned horizontally at the same time.
When simultaneously scanning the signal lines, the number of dummy data lines may be N or more. Pixels and driving transistors are not necessarily required for the dummy data line, and even if they are omitted, the effect of reducing the obscuration defects is sufficient.

Finally, referring to FIGS. 3 to 7, the generation mechanism of the oblate defect will be described for reference. FIG. 3 shows a configuration of a general active matrix display device. The configuration is the same as that of the circuit shown in FIG. 8, and corresponding portions are denoted by corresponding reference numerals to facilitate understanding. Here, reference numerals used in the following description are particularly referred to.
The potential of the video line 103 to which the video signal Vsig is supplied is represented by VA. The potential of each data line Y is represented by VB. Further, the potential of each gate line X is represented by VC. Parasitic capacitance Ch is interposed at the intersection of each gate line X and data line Y, causing the above-described capacitance coupling. Each gate line X also includes a resistance component.

FIG. 4 shows the potentials VA and V of each line described above.
B and VC represent changes over time. As shown in the figure, a sampling pulse φ _H is output from the horizontal scanning circuit 102, and the video signal Vsig is sampled and held on the corresponding data line. The potential VB of the sampled and held data line and the potential VC of the gate line are flat at first glance, but when the sampling timing is expanded before and after, fluctuations appear due to the above-described capacitance coupling. That is, a signal having a differential wave shape is constantly superimposed on the gate potential VC. The data potential VB is attenuated (decayed) from the level once sampled and held.

FIG. 5 shows an equivalent circuit of this part. Each data line crosses all the gate lines after the corresponding HSW. Therefore, the equivalent circuit includes an equivalent capacitance C _H corresponding to the sum of the parasitic capacitances Ch shown in FIG.
In the equivalent circuit, C _G is the sum of the capacitances of the gate lines themselves, and R _G is the equivalent gate line resistance. In such a circuit, the data potential VB rises and the gate potential VC rises accordingly. Also, HSW
Is closed, the attenuation of the gate potential VC is directly reflected on the data potential VB as it is.

FIG. 6 is a timing chart showing what happens when, for example, four lines are scanned simultaneously. Here, for the sake of simplicity, the final sampling pulse φ
_{H, LAST} to five sampling pulses are shown. The charging and discharging of the signal line are repeated until the last sampling pulse φ _{H, LAST} . Therefore, the gate potential VC
Continue to receive the capacitive coupling at the rising edge of each φ _H. When the rise of φH _{, LAST} is completed, the gate potential VC stops receiving the capacitive coupling, and thus attenuates toward the ground level. On the other hand, each signal line has a corresponding HSW
Since closed, jump shakes the gate potential via a capacitive component C _H shown in the equivalent circuit of FIG. At the timing before φ _{H, LAST-4} , VB _LAST-4
Changes by ΔV0 as shown by. However, φ _{H, LAST-3} ,
.., the level at which the attenuation of the gate potential VC jumps into the signal line decreases as φH _{, LST-2} , φH _{, LST-1,.}
That is, the potentials of the last four signal lines VB _LAST-3 ,.
Voltage drop ΔV1 of VB _LAST, ..., ΔV4 is reduced.

FIG. 7 schematically shows this ΔV. Last 4
The ΔV of the main signal line is smaller than that of all the previous signal lines. The degree of the decrease increases as approaching the final signal line. For this reason, the obscured defect occurs in the last four lines.

[0018]

As described above, according to the present invention, dummy data lines wired outside the display area are provided in addition to actual data lines wired inside the display area. Horizontal scanning is performed on the actual data line with multiple overlapping sampling timings, and further horizontal scanning is added on the dummy data line with overlapping sampling timing, eliminating obi defects. As a result, the effect of improving the image quality can be obtained. In particular, the present invention is extremely effective when performing dot sequential driving in a large active matrix display device or the like in which the number of pixels is extremely increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an active matrix display device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the active matrix display device shown in FIG. 1;

FIG. 3 is a reference circuit diagram for explaining an oblate defect.

FIG. 4 is also a reference timing chart.

FIG. 5 is a reference equivalent circuit diagram.

FIG. 6 is also a reference timing chart.

FIG. 7 is also a reference graph.

FIG. 8 is a circuit diagram showing a general configuration of a conventional active matrix display device.

FIG. 9 is a timing chart for explaining the operation of the active matrix display device shown in FIG. 8;

FIG. 10 is a timing chart for explaining the operation.

FIG. 11 is a schematic diagram showing an obi defect appearing in a display area.

[Explanation of symbols]

 Reference Signs List 1 display area 2 vertical scanning circuit 3 horizontal scanning circuit 4 video line X signal line Y data line HSW horizontal switch PXL pixel Tr thin film transistor

Claims (4)

(57) [Claims] 1. A plurality of gate lines wired in a row,
A plurality of data lines wired in a column, a plurality of pixels provided at each intersection of the two and constituting a display area, and a vertical line for sequentially scanning each gate line and selecting one row of pixels every one horizontal period An active matrix display device comprising: a scanning circuit; and a horizontal scanning circuit that sequentially scans each data line within one horizontal period, samples a video signal, and writes a video signal in a dot-sequential manner to selected pixels of one row. The data line is divided into a real data line wired in the display area and a dummy data line wired outside the display area and intersecting the end side of the gate line. Horizontal scanning is performed on the data lines at overlapping sampling timings over a plurality of lines, and furthermore, overlapping is performed continuously on the dummy data lines. An active matrix display device, characterized in that to add a horizontal scanning at the sampling timing. 2. The active matrix display device according to claim 1, wherein the dummy data lines are wired by at least the number of lines that are simultaneously scanned horizontally at overlapping sampling timings. 3. The active matrix display device according to claim 1, wherein a dummy pixel is also assigned to said dummy data line. 4. The active matrix display device according to claim 1, wherein pixels are excluded from said dummy data lines.