JP3890950B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device, and more particularly to a dot sequential drive type active matrix display device in which a clock drive method is applied to a divided sample hold type horizontal drive circuit.
[0002]
[Prior art]
An active matrix display device includes a row-shaped gate line, a column-shaped signal line, and a panel having pixels arranged in a matrix at a portion where both lines intersect. For example, a thin film transistor (TFT) is formed in each pixel as an active element. Further, a vertical drive circuit and a horizontal drive circuit are provided. The vertical drive circuit is connected to each gate line and sequentially selects a row of pixels. The horizontal drive circuit is connected to each signal line and writes a video signal to the pixels in the selected row. At that time, in the dot sequential driving method, video signals are written in the dot sequential order to the pixels in the selected row.
[0003]
In the active matrix display device, parasitic capacitance exists between the source / drain electrodes of the TFT and each of the signal lines. Due to this parasitic capacitance, an image defect such as a vertical stripe may occur due to a potential change at the time of writing a video signal through a certain signal line jumping into an adjacent signal line. This vertical streak defect is particularly noticeable when a checkered pattern is displayed by the line inversion driving method. Or, when the horizontal line corresponding to one dot (one pixel) is displayed by the dot line inversion driving method, vertical stripes are likely to occur.
[0004]
In order to prevent the jump of the video signal between the signal lines, so-called divided sample hold driving has been proposed, and is disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-267616. The divided sample and hold method is a method in which when an input video signal is divided into two systems and the video signal is written in a dot sequential method, the two systems of video signals are written while being overlapped between adjacent pixels.
[0005]
FIG. 7 is a schematic diagram illustrating an example of a display device that employs the divided sample hold driving described above. As shown in the figure, the display device includes a row-shaped gate line 113, a column-shaped signal line 112, pixels 111 arranged in a matrix at the intersection of both lines, and a video signal Video1 divided into two systems with a predetermined phase relationship. , Video2 is composed of a panel having two video lines 125 and 126 for supplying Video2. A sampling switch group 123 is arranged corresponding to each signal line 112, and is connected between each of the two video lines in units of two signal lines. Specifically, the first signal line is connected to one video line 125 via a sampling switch, and the second signal line is connected to the other video line 126 via a sampling switch. Hereinafter, the third and subsequent signal lines are alternately connected to the two video lines 125 and 126 via the sampling switches. A vertical driving circuit 116 and a horizontal driving circuit 117 are further formed on the panel. The vertical drive circuit 116 is connected to each gate line 113 and sequentially selects rows of the pixels 111. In other words, the pixels 111 arranged in a matrix are sequentially selected in units of rows. The horizontal drive circuit 117 operates based on a clock signal having a predetermined period, and does not overlap the switches connected to the same video line among the switches of the sampling switch group 123, and does not overlap the adjacent switches. .. Are sequentially generated to sequentially open and close the respective switches, and the video signals are written to the pixels 111 of the selected row in a dot-sequential manner. The display device further includes a clock generation circuit 189, which supplies a start pulse HST in addition to a clock signal HCK serving as an operation reference of the horizontal drive circuit 117. The horizontal drive circuit 117 is composed of a multi-stage connection of the shift register (S / R) 121 and sequentially generates the above-described sampling pulses A, B, C, D... By sequentially transferring HST according to HCK. Yes.
[0006]
The operation of the conventional display device shown in FIG. 7 will be briefly described with reference to the waveform diagram of FIG. As described above, the horizontal drive circuit operates in response to the clock signal HCK, and generates the sampling pulses A, B, C, D... By sequentially transferring the start pulse HST. As is apparent from the figure, the sampling pulses overlap each other between adjacent signal lines. That is, the sampling pulse A corresponding to the first signal line overlaps with the sampling pulse B corresponding to the second signal line. Similarly, the sampling pulse B corresponding to the second signal line and the sampling pulse C corresponding to the third signal line also overlap. Since video signals are supplied from different video lines to adjacent signal lines, they may be overlapped. By generating sampling pulses so as to overlap the sampling switches of adjacent signal lines, it is possible to prevent a vertical line defect that has been a problem in the past. That is, there is a parasitic capacitance between the source / drain electrodes of each pixel transistor and each of the signal lines, and even if a potential change of a certain signal line jumps into the adjacent signal line via this parasitic capacitance, Since the line has a low impedance due to overlap sampling, it is not affected by the jumping in of the video signal.
[0007]
In the illustrated example, in response to the sampling pulse A, the signal potential Sig1 is sampled and held in the corresponding first signal line. Subsequently, in response to the sampling pulse B, the signal potential Sig2 is sampled and held in the second signal line. At this time, a potential change occurs in the second signal line. This potential change also jumps into the first signal line due to the parasitic capacitance. At this time, since the corresponding sampling switch is still open, the first signal line has a low impedance and is affected by the signal jump. There is nothing.
[0008]
[Problems to be solved by the invention]
FIG. 9 schematically shows the sampling timing of the video signal for each signal line and the potential change of each video line. Basically, sampling pulses are generated so as not to overlap the sampling switches connected to the same video line. For example, the first signal line and the third signal line are connected to the same video line. Therefore, the circuit is designed so that the sampling pulse A and the sampling pulse C do not overlap in principle. However, in reality, in the pulse transmission process, a delay occurs due to wiring resistance, parasitic capacitance, etc., and the waveform becomes dull. As a result, the sampling pulse A and the sampling pulse C have a partial overlap. In this state, when the sampling pulse C rises, the corresponding sampling switch is opened and charging / discharging of the signal line occurs, so that the potential fluctuation occurs in the video signal Video1 on the video line as indicated by the solid line arrow. At this time, since the preceding sampling pulse A has not yet fallen, the potential fluctuation (charge / discharge noise) of the video line is picked up as indicated by the dotted arrow. As a result, the sampled potential varies in the signal line and becomes vertical stripes on the screen, thereby degrading the image quality. In addition, a ghost or the like may be caused on the screen due to such interference of the video signal between the signal lines connected to the same video line.
[0009]
[Means for Solving the Problems]
In view of the above-described problems of the conventional technology, the present invention suppresses the interference of video signals generated between signal lines connected to the same video line in an active matrix display device adopting a so-called divided sample and hold method. The object is to suppress image defects such as vertical stripes and ghosts. The following measures were taken in order to achieve this purpose. That is, the display device according to the present invention includes row-shaped gate lines, column-shaped signal lines, pixels arranged in a matrix at the intersection of both lines, and video signals divided into at least two systems with a predetermined phase relationship. A panel having at least two video lines to be supplied, a vertical driving circuit connected to the gate line and sequentially selecting a row of pixels, and arranged corresponding to each signal line, the at least two signal lines being A sampling switch group connected between each of the two video lines as a unit, and operates based on a clock signal of a predetermined cycle, and is connected to the same video line among the switches of the sampling switch group The overlapped sampling pulses are not generated for the adjacent switches, and the overlapping sampling pulses are generated sequentially for adjacent switches. Are sequentially driven, and a horizontal driving circuit for sequentially writing video signals to pixels in a selected row, and a first clock signal as an operation reference of the horizontal driving circuit are generated, and the first clock signal Clock generating means for generating two systems of second clock signals having the same period and a long pulse width, and the horizontal drive circuit includes the first clock signal In synchronization with both rising and falling timings of the first clock signal and the inverted clock signal. The shift register performs a shift operation in synchronization with the shift register and sequentially outputs shift pulses from each shift stage, and is turned on in response to the shift pulses sequentially output from the shift register, to each system of the second clock signal. A sampling switch group that sequentially generates the sampling pulses by extracting the included pulses, and the clock generation means is arranged outside the panel and supplies the first clock signal from the outside to the horizontal driving circuit. And an external clock generation circuit that is formed inside the panel and supplies the second clock signal from the inside of the panel to the horizontal driving circuit. The internal clock generation circuit is divided into the external clock generation circuit and the external clock generation circuit. The first clock signal is generated in order to process the first clock signal supplied from the clock generation circuit and generate the second clock signal. A delay circuit that delays the first clock signal before the delay processing and the first clock signal after the delay processing generate the second clock signal. And
[0010]
Preferably, the delay circuit includes an even number of inverters connected in series. The internal clock generation circuit generates a second clock signal by NOR-combining the first clock signal before the delay process and the first clock signal after the delay process. It has a NOR circuit.
According to another aspect of the invention, the clock generation means includes the first clock signal. The phase of the second clock signal is determined in synchronization with the rise or fall of As a result, the sampling pulses that are not completely overlapped with respect to the switches connected to the same video line but are overlapped with the adjacent switches are sequentially generated.
[0011]
According to the present invention, in a display device that employs divided sample hold driving, the shift pulse output from the horizontal driving circuit is extracted with another clock signal to generate a sampling pulse. By introducing such a clock drive system, sampling pulses between adjacent signal lines maintain an overlap, while every other signal line connected to the same video line has a complete non-overlap of sampling pulses. Is realized.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing an embodiment of a display device according to the present invention. As shown in the figure, this display device includes a row-shaped gate line 13, a column-shaped signal line 12, a pixel 11 arranged in a matrix at the intersection of both lines, and a video signal divided into two systems according to a predetermined phase relationship. It is comprised by the panel which has the two video lines 25 and 26 which supply Video1 and Video2 separately. In this embodiment, two video signals are used, but in general, n video signals having a predetermined phase relationship can be used. In this case, n video lines may be provided. However, n is an integer of 2 or more. The display device includes a vertical drive circuit 16, a horizontal drive circuit 17, and a clock generation means 89 in addition to the panel described above. Preferably, the vertical drive circuit 16 and the horizontal drive circuit 17 are built in the panel. A sampling switch group 23 is also formed on the panel. Each switch of the sampling switch group 23 is arranged corresponding to each signal line 12, and is connected between each of the two video lines in units of two signal lines. Specifically, the switch corresponding to the first signal line is connected to one video line 25, and the switch corresponding to the second signal line is connected to the other video line 26. In this way, each signal line 12 is connected to the two video lines 25 and 26 alternately. In general, the sampling switch group 23 is connected to each of n video lines in units of n signal lines.
[0013]
The vertical drive circuit 16 is connected to each gate line 13 and sequentially selects the pixels 11 in units of rows. The horizontal drive circuit 17 operates based on a clock signal having a predetermined period, and does not overlap the switches connected to the same video line among the switches of the sampling switch group 23, but with respect to adjacent switches. .. Are sequentially generated to sequentially drive the respective switches, and the video signals Video1, Video2 are sequentially written to the pixels 11 in the selected row.
[0014]
As a feature of the present invention, the clock generation unit 89 generates a first clock signal HCK that is an operation reference of the horizontal drive circuit 17, and a second pulse having a longer pulse width than the first clock signal HCK. Clock signals DCK1 and DCK2 are generated. On the other hand, the horizontal drive circuit 17 includes a shift register 21 and a sampling switch group 22. Each stage of the shift register 21 is represented by S / R. The shift register 21 performs a shift operation of the horizontal start pulse HST in synchronization with the first clock signal HCK, and sequentially outputs shift pulses A, B, C, D... From each shift stage S / R. The start pulse HST is supplied from the clock generation means 89. Each switch of the sampling switch group 22 extracts the second clock signals DCK1, DCK2 in response to the shift pulses A, B, C, D... Sequentially output from the shift register 21, and the sampling pulse A ′ described above. , B ′, C ′, D ′. In this way, the horizontal drive circuit 17 does not overlap the switches connected to the same video line among the switches of the sampling switch group 23, but overlaps the adjacent switches. Pulses are sequentially generated to drive each switch in turn. For example, sampling pulses A ′ and B ′ overlap while A ′ and C ′ are completely non-overlapping.
[0015]
The operation of the display device shown in FIG. 1 will be described with reference to FIG. The horizontal drive circuit 17 operates in response to a first clock signal HCK (hereinafter sometimes referred to as an HCK pulse), and generates shift pulses A, B, C, and D by sequentially transferring a start pulse HST. ing. In addition to the HCK pulse, the clock generation unit 89 supplies the second clock signals DCK1 and DCK2 (hereinafter sometimes referred to as DCK pulses) to the horizontal drive circuit 17. As is clear from the timing chart of FIG. 2, the DCK pulse has the same period as the HCK pulse, but the pulse width is large. Also, DCK1 and DCK2 are 180 degrees out of phase with each other.
[0016]
The horizontal drive circuit 17 shown in FIG. 1 opens and closes the extraction switch group 22 with each shift pulse A, B, C, D... To extract a DCK pulse. Thereby, sampling pulses A ′, B ′, C ′, D ′... Are generated. Specifically, the sampling pulse A ′ is generated by extracting the DCK1 pulse with the shift pulse A. Similarly, the sampling pulse B ′ is obtained by extracting the DCK2 pulse with the shift pulse B. Similarly, sampling pulses C ′, D ′,... Are obtained by extracting DCK pulses with shift pulses. By introducing such a clock drive system, adjacent sampling pulses are kept overlapping, and every other signal line connected to the same video line is completely non-overlapping. . For example, sampling pulses A ′ and B ′ overlap, and A ′ and C ′ are completely non-overlapping.
[0017]
By adopting complete non-overlap, it is possible to cope with vertical stripes, ghosts, and the like peculiar to the dot matrix drive type active matrix display device. For example, in the example of FIG. 2, as indicated by the dotted arrow, the video signal Video1 is correctly sampled on the corresponding signal line when the sampling pulse A ′ falls. Thereafter, when the sampling pulse C ′ rises as indicated by the solid line arrow, the signal line is charged and discharged, so that the potential of the video signal Video1 fluctuates downward and noise is placed. However, when this noise is generated, the sampling pulse A ′ has already fallen, so there is no effect.
[0018]
As described above, in the present invention, the clock drive method using the DCK pulse is introduced for the divided sample hold drive. In order to correspond to the divided sample hold drive, a DCK pulse having a long pulse width and a different duty ratio is used as a pulse extracted by the clock drive. By extracting this DCK pulse by the shift pulse output from each stage of the shift register, the sampling pulses corresponding to the same video line are non-overlapping while the adjacent sampling pulses are kept overlapping. In this way line It is possible to remove vertical stripes in specific patterns such as a checkered pattern in inversion driving and a one-dot horizontal line pattern in dot line inversion driving, and simultaneously eliminate vertical stripes and ghosts peculiar to a dot sequential active matrix display device.
[0019]
FIG. 3 is a schematic block diagram showing a specific configuration example of the display device according to the present invention. As shown in the figure, this display device is composed of a panel 33 in which a pixel array section 15, a vertical drive circuit 16, a horizontal drive circuit 17 and the like are formed in an integrated manner. The pixel array unit 15 is composed of row-like gate lines 13, column-like signal lines 12, and pixels 11 arranged in a matrix at the intersection of both. The vertical drive circuit 16 is arranged separately on the left and right, and is connected to both ends of the gate line 13 to sequentially select the rows of the pixels 11. The horizontal driving circuit 17 is connected to the signal line 12 and operates based on an HCK pulse having a predetermined period, and sequentially writes video signals to the pixels 11 in the selected row. The display device includes a clock generation unit, which generates an HCK pulse that is an operation reference of the horizontal drive circuit 17, and generates a DCK pulse having the same period and a large pulse width with respect to the HCK pulse. The HCK pulse includes a clock signal HCK and its inverted signal HCKX. The DCK pulse includes clock signals DCK1, DCK1X, DCK2, and DCK2X. DCK1X is an inverted signal of DCK1, and DCK2X is an inverted signal of DCK2. DCK1 and DCK2 are 180 degrees out of phase with each other. In order to simplify the illustration, the video line and the sampling switch group are omitted from the panel 33. In addition, a precharge circuit 20 is connected to each signal line 12, and a predetermined level of potential is applied to each signal line 12 in advance before sampling a video signal from the horizontal drive circuit 17 side to display quality. We are trying to improve.
[0020]
As a feature of the present embodiment, the clock generation means is divided into an external clock generation circuit 18 and an internal clock generation circuit 19. The external clock generation circuit 18 is mounted on a drive system board (not shown) outside the panel 33 and supplies the first clock signals HCK and HCKX from the outside to the internal horizontal drive circuit 17. On the other hand, the internal clock generation circuit 19 is formed inside the panel 33 together with the vertical drive circuit 16 and the horizontal drive circuit 17. The internal clock generation circuit 19 internally generates the second clock signals DCK 1, DCK 1 X, DCK 2, and DCK 2 X to the horizontal drive circuit 17. Supply. The internal clock generation circuit 19 processes the HCK pulse supplied from the external clock generation circuit 18 to generate a DCK pulse. In this way, by generating the DCK pulse inside the panel, an increase in the number of input pads formed on the panel 33 can be prevented. If all the HCK pulse and DCK pulse are supplied from the outside, six input pads are required. Input by creating DCK pulse inside the panel pad Can be reduced by four.
[0021]
FIG. 4 is a block diagram showing a specific configuration example of the internal clock generation circuit 19 shown in FIG. Focusing on the first system (1), the first clock signal HCK supplied from the external clock generation circuit is divided into two. One is supplied to one input terminal of the NOR circuit 55 as it is. The other is supplied to a delay circuit composed of four inverters 51 to 54 connected in series. The output of this delay circuit is supplied to the other input terminal of the NOR circuit 55. The NOR circuit 55 performs NOR synthesis on the HCK that has not been subjected to the delay process and the HCK ′ that has been subjected to the delay process. The signal output from the NOR circuit 55 is inverted by the inverter 56 and then output through the buffer 57 as the clock signal DCK1. The signal output from the output terminal of the NOR circuit 55 is branched and output as DCK1X through the buffer 58 and sent to the horizontal drive circuit side. In general, it is known that a pulse signal is delayed every time it passes through an inverter. Therefore, in this example, the clock signal HCK ′ that has passed through a plurality of inverters is delayed by several tens of nsec compared to the clock signal HCK that does not pass through the inverters. By subjecting these two clock signals HCK and HCK ′ to NOR synthesis, target clock signals DCK1 and DCK1X having a pulse width longer than that of HCK can be generated. Similarly, DCK2 and DCK2X are generated in the system (2).
[0022]
FIG. 5 is a waveform diagram for explaining the operation of the internal clock generation circuit shown in FIG. (1) represents the operation of the first system (1) shown in FIG. 4, and (2) represents the operation of the second system (2) shown in FIG. Focusing on (1), HCK ′ is delayed by a predetermined time compared to HCK. This delay amount can be optimally set according to the number of inverter stages connected in series. DCK1X having a wide pulse width is obtained by performing NOR processing on HCK and HCK ′ whose phases are shifted from each other by the delay processing. When DCK1X is inverted by the output inverter, DCK1 is obtained. Similarly, as shown in (2), DCK2 is obtained by logically processing HCKX that has not been subjected to delay processing and HCKX ′ that has been subjected to delay processing. When this DCK2 is inverted, DCK2X is obtained.
[0023]
FIG. 6 is a circuit diagram showing a configuration example of an active matrix liquid crystal display device of a dot sequential drive system according to an embodiment of the present invention using, for example, a liquid crystal cell as a pixel display element (electro-optical element). Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example. In an active matrix liquid crystal display device, a thin film transistor (TFT) is usually used as a switching element for each pixel.
[0024]
In FIG. 6, each of the pixels 11 of 4 rows and 4 columns arranged in a matrix includes a thin film transistor TFT which is a pixel transistor, a liquid crystal cell LC having a pixel electrode connected to the drain electrode of the thin film transistor TFT, and a thin film transistor TFT. And a storage capacitor Cs having one electrode connected to the drain electrode. For each of these pixels 11, signal lines 12-1 to 12-4 are wired for each column along the pixel arrangement direction, and gate lines 13-1 to 13-4 are arranged for each row in the pixel arrangement direction. It is wired along.
[0025]
In each pixel 11, the source electrode (or drain electrode) of the thin film transistor TFT is connected to the corresponding signal line 12-1 to 12-4. The gate electrodes of the thin film transistors TFT are connected to the gate lines 13-1 to 13-4, respectively. The counter electrode of the liquid crystal cell LC and the other electrode of the storage capacitor Cs are connected to the Cs line 14 in common between the pixels. A predetermined DC voltage is applied to the Cs line 14 as a common voltage Vcom.
[0026]
As described above, the pixels 11 are arranged in a matrix, and signal lines 12-1 to 12-4 are wired for each column and gate lines 13-1 to 13-4 are wired for each row. The pixel array unit 15 is configured. In the pixel array unit 15, one end of each of the gate lines 13-1 to 13-4 is connected to an output terminal of each stage of the vertical drive circuit 16 disposed on the left side of the pixel array unit 15, for example.
[0027]
The vertical drive circuit 16 performs a process of sequentially selecting each pixel 11 connected to the gate lines 13-1 to 13-4 in units of rows by scanning in the vertical direction (row direction) every field period. That is, when the scanning pulse Vg1 is applied to the gate line 13-1 from the vertical drive circuit 16, the pixel in each column of the first row is selected, and the scanning pulse Vg2 is applied to the gate line 13-2. Sometimes the pixels in each column of the second row are selected. Similarly, scanning pulses Vg3 and Vg4 are sequentially applied to the gate lines 13-3 and 13-4.
[0028]
A horizontal drive circuit 17 is disposed, for example, on the upper side of the pixel array unit 15. In addition, an external clock generation circuit (timing generator) 18 for providing various clock signals to the vertical drive circuit 16 and the horizontal drive circuit 17 is provided. In this external clock generation circuit 18, a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, a vertical start pulse HST for instructing the start of horizontal scanning, and horizontal scanning The horizontal clocks HCK and HCKX having opposite phases to each other are generated.
[0029]
In addition to the external clock generation circuit 18, an internal clock generation circuit 19 is provided. In the internal clock generation circuit 19, a pair of clocks DCK1 and DCK2 having the same period and a long pulse width with respect to the horizontal clocks HCK and HCKX are generated.
[0030]
The horizontal driving circuit 17 sequentially samples the video signals Video1 and Video2 input from the two video lines 25 and 26 every 1H (H is a horizontal scanning period), and is selected by the vertical driving circuit 16 in units of rows. In this example, the clock drive method is employed, and the shift register 21, the clock extraction switch group 22, and the sampling switch group 23 are used.
[0031]
The shift register 21 includes four shift stages (S / R) 21-1 to 21-4 corresponding to the pixel columns (four columns in this example) of the pixel array unit 15, and is supplied with a horizontal start pulse HST. The shift operation is performed in synchronization with the horizontal clocks HCK and HCKX having opposite phases. As a result, shift pulses A to D having the same pulse width as the cycles of the horizontal clocks HCK and HCKX are sequentially output from the shift stages 21-1 to 21-4 of the shift register 21, respectively.
[0032]
The clock extraction switch group 22 includes four switches 22-1 to 22-4 corresponding to the pixel columns of the pixel array unit 15, and one end of each of the switches 22-1 to 22-4 is connected to the internal clock generation circuit 19. Are alternately connected to clock lines 24-1 and 24-2 for transmitting clocks DCK2 and DCK1. That is, one end of each of the switches 22-1 and 22-3 is connected to the clock line 24-1, and one end of each of the switches 22-2 and 22-4 is connected to the clock line 24-2.
[0033]
Shift pulses A to D sequentially output from the shift stages 21-1 to 21-4 of the shift register 21 are given to the switches 22-1 to 22-4 of the clock extraction switch group 22, respectively. The switches 22-1 to 22-4 of the clock extracting switch group 22 respond to the shift pulses A to D when the shift pulses A to D are given from the shift stages 21-1 to 21-4 of the shift register 21, respectively. Then, the clocks DCK2 and DCK1 having opposite phases are alternately extracted by sequentially turning on.
[0034]
The sampling switch group 23 includes four switches 23-1 to 23-4 corresponding to the pixel columns of the pixel array unit 15, and one end of each of these switches 23-1 to 23-4 inputs the video signal Video1. The video lines 25 and the video lines 26 for inputting Video 2 are alternately connected. In the switches 23-1 to 23-4 of the sampling switch group 23, clocks DCK2 and DCK1 extracted by the switches 22-1 to 22-4 of the clock extraction switch group 22 are used as sampling pulses A ′ to D ′. Given.
[0035]
When the sampling pulses A ′ to D ′ are given from the switches 22-1 to 22-4 of the clock extraction switch group 22, the switches 23-1 to 23-4 of the sampling switch group 23 receive the sampling pulses A ′ to D, respectively. By sequentially turning on in response to D ′, the video signals Video1 and Video2 input through the video lines 25 and 26 are sampled alternately and sequentially to the signal lines 12-1 to 12-4 of the pixel array unit 15. Supply.
[0036]
In the horizontal drive circuit 17 according to this embodiment having the above-described configuration, the shift pulses A to D sequentially output from the shift register 21 are not used as they are as the sampling pulses A ′ to D ′, but are synchronized with the shift pulses A to D. Thus, a pair of clocks DCK2 and DCK1 are alternately extracted, and these clocks DCK2 and DCK1 are used as sampling pulses A ′ to D ′. Thereby, the dispersion | variation in sampling pulse A'-D 'can be suppressed. As a result, ghosts caused by variations in the sampling pulses A ′ to D ′ can be removed.
[0037]
【The invention's effect】
As described above, according to the present invention, clock driving is performed using DCK pulses having a long pulse width and a different duty ratio with respect to the HCK pulse serving as the operation reference of the horizontal drive circuit. As a result, complete non-overlapping sampling corresponding to the divided sample hold drive is achieved, and the occurrence of vertical stripes and ghosts is suppressed. At the same time, by overlapping the sampling pulses assigned to adjacent signal lines in the divided sample hold drive, when displaying a specific pattern such as a dot checkered pattern during line inversion drive or a 1-dot horizontal line pattern during dot line inversion drive It is also possible to remove the vertical streak. In addition, an increase in the number of input pads and the number of input wirings can be prevented by synthesizing a DCK pulse inside the panel based on an HCK pulse supplied from outside.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a basic configuration of a display device according to the present invention.
FIG. 2 is a waveform diagram for explaining the operation of the display device shown in FIG.
3 is a block diagram illustrating a specific configuration example of the display device illustrated in FIG. 1;
4 is a block diagram illustrating a specific configuration example of an internal clock generation circuit incorporated in the display device illustrated in FIG. 3;
FIG. 5 is a timing chart for explaining the operation of the internal clock generation circuit shown in FIG. 4;
FIG. 6 is a circuit diagram showing a configuration example of a dot sequential driving type active matrix liquid crystal display device according to an embodiment of the present invention;
FIG. 7 is a block diagram illustrating an example of a conventional display device.
FIG. 8 is a waveform diagram for explaining the operation of the conventional display device shown in FIG. 7;
FIG. 9 is a waveform diagram for explaining the operation of the conventional display device shown in FIG. 7;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Pixel, 12 ... Signal line, 13 ... Gate line, 15 ... Pixel array part, 16 ... Vertical drive circuit, 17 ... Horizontal drive circuit, 18 ... External clock Generating circuit, 19 ... internal clock generating circuit, 21 ... shift register, 22 ... sampling switch group, 23 ... sampling switch group, 89 ... clock generating means

Claims (4)

Row-shaped gate lines, column-shaped signal lines, pixels arranged in a matrix at the intersection of both lines, and at least two video lines for supplying video signals divided into at least two systems with a predetermined phase relationship A panel,
A vertical drive circuit connected to the gate line and sequentially selecting a row of pixels;
Based on a sampling switch group arranged corresponding to each signal line and connected between each of the two video lines in units of at least two signal lines, and a clock signal having a predetermined period Each of the switches in the sampling switch group is not overlapped with respect to the switches connected to the same video line, and overlapped sampling pulses are sequentially generated with respect to adjacent switches. A horizontal drive circuit for sequentially driving the switches and sequentially writing video signals to the pixels in the selected row;
Clock generating means for generating a first clock signal as an operation reference of the horizontal drive circuit and generating two systems of second clock signals having the same period and a long pulse width with respect to the first clock signal; Consists of
The horizontal driving circuit performs a shift operation in synchronization with both the rising and falling timings of the first clock signal, or in synchronization with the first clock signal and the clock signal with the polarity reversed. A shift register that sequentially outputs shift pulses from the stage, and is turned on in response to the shift pulses that are sequentially output from the shift register, and the sampling pulses are extracted by extracting pulses included in each system of the second clock signal. A sampling switch group that sequentially generates,
The clock generation means is arranged outside the panel and supplies the first clock signal to the horizontal drive circuit from the outside of the panel, and the second clock signal formed inside the panel is supplied to the panel. Is divided into an internal clock generation circuit that supplies the horizontal drive circuit from the inside,
The internal clock generation circuit includes a delay circuit that delays the first clock signal in order to process the first clock signal supplied from the external clock generation circuit and generate the second clock signal. And a second clock signal generated from the first clock signal before the delay process and the first clock signal after the delay process.   The display device according to claim 1, wherein the delay circuit includes an even number of inverters connected in series.   The internal clock generation circuit NOR-combines the first clock signal before the delay process and the first clock signal after the delay process with each other to generate the second clock signal. The display device according to claim 2, further comprising: Row-shaped gate lines, column-shaped signal lines, pixels arranged in a matrix at the intersection of both lines, and at least two video lines for supplying video signals divided into at least two systems with a predetermined phase relationship A panel,
A vertical drive circuit connected to the gate line and sequentially selecting a row of pixels;
Based on a sampling switch group arranged corresponding to each signal line and connected between each of the two video lines in units of at least two signal lines, and a clock signal having a predetermined period Each of the switches in the sampling switch group is not overlapped with respect to the switches connected to the same video line, and overlapped sampling pulses are sequentially generated with respect to adjacent switches. A horizontal drive circuit for sequentially driving the switches and sequentially writing video signals to the pixels in the selected row;
Clock generating means for generating a first clock signal as an operation reference of the horizontal drive circuit and generating two systems of second clock signals having the same period and a long pulse width with respect to the first clock signal; Consists of
The horizontal driving circuit performs a shift operation in synchronization with both the rising and falling timings of the first clock signal, or in synchronization with the first clock signal and the clock signal with the polarity reversed. A shift register that sequentially outputs shift pulses from the stage, and is turned on in response to the shift pulses that are sequentially output from the shift register, and the sampling pulses are extracted by extracting pulses included in each system of the second clock signal. A sampling switch group that sequentially generates,
The clock generation means determines the phase of the second clock signal in synchronization with the rise or fall of the first clock signal, and completely overlaps the switches connected to the same video line. A display device characterized in that overlapping sampling pulses are sequentially generated for adjacent switches.

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