JP2005309283A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which generates no longitudinal belt at a unit boundary when horizontal high-speed driving is performed. <P>SOLUTION: Different common potentials Vcom1 and Vcom2 are connected to odd-numbered(odd) and even-numbered (even) units and a difference in pixel potential VP due to an error in pulse width among sampling pulses Vh1 to Vh4 are absorbed by their difference ΔV. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a dot sequential drive type active matrix display device.

  As a driving method of a display device in which pixels are arranged in a matrix, for example, a liquid crystal display device (liquid crystal driver), individual pixel electrodes are arranged for each of the pixels, and each of these pixel electrodes is arranged. A dot-sequential driving type active matrix display device is known in which a switching element such as a thin film transistor (TFT) is connected to the pixel to selectively drive a pixel.

FIG. 3 is a circuit configuration example showing a display device 1 which is a conventional dot sequential drive type active matrix display device. As shown in FIG. 3, the display device 1 includes a pixel unit 15, a vertical drive circuit 16, and a horizontal drive circuit 17.
The pixel unit 15 includes row-like scanning lines 13, column-like signal lines 12, and pixels 11 arranged in a matrix at portions where both intersect.
The pixel 11 includes a thin film transistor TFT, which is a pixel transistor, and a storage capacitor Cs connected in parallel to a liquid crystal cell (not shown). One end (the drain terminal side of the TFT) of the storage capacitor Cs is connected to the pixel electrode (pixel potential VP), and the other end is connected to the common potential Vcom. As illustrated, all the pixels 11 are connected to a common common potential Vcom.

The vertical drive circuit 16 is connected to the scanning line 13 and sequentially selects the rows of the pixels 11.
The horizontal drive circuit 17 is connected to the signal line 12 and operates based on a predetermined clock signal, and sequentially writes video signals to the pixels 11 in the selected row. In this example, the video signal is divided into two systems, video-a and video-b, which is a two-pixel simultaneous drive system.

The horizontal drive circuit 17 includes a shift register 21, a shaping switch group 22, and a sampling switch group 23. The shift register 21 performs a shift operation in synchronization with a clock signal input from the outside, and sequentially outputs shift pulses from each shift stage. The shaping switch group 22 shapes the shift pulses sequentially output from the shift register 21 and sequentially outputs the sampling pulses Vh1 and Vh2.
In the illustrated example, the sampling pulse Vh1 is output from the N stage, and the sampling pulse Vh2 is output from the next N + 1 stage.

The sampling switch group 23 sequentially samples the input video signals video-a and video-b in response to the sampling pulses Vh1 and Vh2, and supplies them to the signal lines 12.
In the illustrated example, the sampling switch 23-1 samples the video signals video-a and video-b in response to the sampling pulse Vh1, and supplies them to the two signal lines 12-1 and 12-2, respectively. . The next sampling switch 23-2 samples the video signals video-a and video-b in response to the sampling pulse Vh2, and supplies them to the two signal lines 12-3 and 12-4, respectively.
Here, a plurality of pixels in the horizontal direction connected by a plurality of signal lines corresponding to each sampling pulse is referred to as a unit. In the example of FIG. 3, each sampling pulse Vh1, Vh2 controls a different unit.

FIG. 4 is a schematic block diagram showing a specific configuration of the horizontal drive circuit 17 included in the display device 1 shown in FIG. In this block diagram, a clock generation circuit 18 for supplying various clock pulses to the horizontal drive circuit 17 is also added.
The clock generation circuit 18 generates horizontal clock pulses HCK and HCKX having opposite phases as a reference for horizontal scanning, and supplies the horizontal clock pulses to the horizontal drive circuit 17. A horizontal start pulse HST is also supplied to the horizontal drive circuit 17.
Further, as shown in the timing chart of FIG. 5, the clock generation circuit 18 generates a pair of clocks DCK1 and DCK2 having the same period (T1 = T2) as the horizontal clock pulses HCK and HCKX and a small duty ratio. This is supplied to the horizontal drive circuit 17.

  The shift register 21 includes shift stages (S / R) 21-1 to 21-4 connected in multiple stages. When a horizontal start pulse HST is given, the shift register 21 is synchronized with horizontal clock pulses HCK and HCKX having opposite phases. To shift. As a result, the shift stages 21-1 to 21-4 of the shift register 21 are shifted from the shift pulses Vs1, Vs2, having the same pulse width as the period of the horizontal clock pulses HCK, HCKX, as shown in the timing chart of FIG. Vs3,... Are sequentially output.

Next, when the shift pulses Vs1 to Vs4 are given to the switches 22-1 to 22-4 of the shaping switch group 22, they are sequentially turned on in response to these shift pulses, so that clock pulses having opposite phases to each other. DCK2 and DCK1 are alternately extracted.
The clock pulses DCK2 and DCK1 extracted by the respective switches 22-1 to 22-4 of the shaping switch group 22 are supplied to the respective switches 23-1 to 23-4 of the sampling switch group 23 as sampling pulses Vh1 to Vh4. As given.

  As described above, the horizontal driving circuit 17 sequentially samples the video signals video-a and video-b input in two systems every 1H (H is a horizontal scanning period), and the vertical driving circuit 16 performs row sampling. Two-pixel simultaneous writing is performed for each pixel 11 selected in units.

By the way, in the display device 1 having the above-described configuration, for example, in the transmission process until the adjacent sampling pulses Vh1 and Vh2 of the horizontal drive circuit 17 are given, the pulses are delayed due to the presence of wiring resistance and parasitic capacitance. May occur.
Then, due to the delay of the pulse in this transmission process, the waveform of the sampling pulses Vh1 and Vh2 is rounded. As a result, waveform overlap occurs between the sampling pulses Vh1 and Vh2.

When the sampling pulse overlaps, charge / discharge noise due to the overlap is sampled, so that a ghost is likely to occur. Here, the ghost refers to an undesired disturbing image that is generated by overlapping and deviating from a normal image. In the conventional driving method in which overlap may occur, the ghost margin is small.
Therefore, conventionally, in order to improve the ghost margin, the pulse widths of the sampling pulses Vh1 and Vh2 are narrowed so that no overlap occurs (non-overlap width expansion).

However, as described above, a new problem arises by narrowing the pulse width of adjacent sampling pulses (for example, the sampling pulses Vh1 and Vh2). That is, when the pulse width of the adjacent sampling pulse is narrowed, there is a case where it cannot be compatible with the recent demand for high-speed driving (high-speed sampling).
In order to perform high-speed driving for the horizontal drive circuit 17, it is necessary to narrow the pulse width of the horizontal clock pulse HCK. For example, in the example shown in FIG. 6, the clocks DCK1, DCK2, that is, This means that it is necessary to further narrow the pulse width of the sampling pulses Vh1 and Vh2.

Normally, the pulse widths of the clocks DCK1 to DCK2 and the sampling pulses Vh1 to Vh2 have a difference of about 1 to 2 ns by design. There is an impact.
FIG. 7 is a waveform showing the state of charge of the pixel potential VP with the difference in pulse width. FIG. 7A shows a case where the sampling pulse width is relatively small, and FIG. Are shown respectively.
As shown in FIG. 7, even when the pulse width difference between the clocks DCK1 to DCK2 and the sampling pulses Vh1 to Vh2 is about the same (1 to 2 ns), if the pulse width itself is narrowed, the storage capacitor Since the change in the charging curve of Cs is held at a large portion, the difference in potential (pixel potential VP) written to the pixel in accordance with each pulse increases. In particular, the influence on the pixel potential VP is significant under the above-described recent high-speed driving environment.

  As described above, when the video signal is held at an early time, a difference in the pixel potential VP of each unit occurs, so that the vicinity of the boundary of each unit on the display screen as shown in FIG. A vertical band is generated in the image and the image quality is impaired.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a display device in which no vertical band is generated at a unit boundary when horizontal high-speed driving is performed.

  In order to achieve the above object, according to an aspect of the present invention, pixel circuits are arranged in a matrix, a signal line is wired for each column, a scanning line is wired for each row, and a reference potential is set for each pixel circuit. Connected to the scanning line to which the scanning pulse is given from the first driving means, the pixel part to which the common potential is set, the first driving means for giving the scanning pulse to each scanning line of the pixel part, A second driving means for supplying a video signal to the pixel circuit in synchronization with a driving pulse applied to each signal line group constituted by a predetermined number of units of the signal lines; and the common potential for the pixel circuit. And a common potential setting means for setting each signal line group connected to the display device.

  Preferably, the common potential setting means sets different common potentials for the pixel circuits connected to the odd-numbered and even-numbered signal line groups in the signal line group.

  Preferably, the common potential setting unit sets the common potential according to a width of a driving pulse given by the second driving unit.

  According to the present invention, when a scanning pulse is given to each scanning line of the pixel portion by the first driving means, the second driving means is connected to the scanning line to which the scanning pulse is given from the first driving means. A video signal is supplied to the pixel circuit in synchronization with a drive pulse applied to each signal line group constituted by a predetermined number of units of signal lines. Since the common voltage is set for each signal line group connected to the pixel circuit, the width of the drive pulse supplied to each signal line group is reduced, so that the pixels connected to each signal line group Even if a difference occurs in the pixel potential of the circuit, the difference between the pixel potential supplied to the pixel and the common potential is kept constant.

  According to the present invention, no vertical band is generated at the unit boundary when horizontal high-speed driving is performed, so that the image quality of the display device is improved.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a circuit configuration example showing a display device 1a which is a dot sequential drive type active matrix display device according to the present invention. As shown in FIG. 1, the display device 1a includes a pixel portion 15a, a vertical drive circuit 16 as a first drive unit, and a horizontal drive circuit 17 as a second drive unit.
The pixel portion 15a includes row-shaped scanning lines 13, column-shaped signal lines 12, and pixels 11 arranged in a matrix at portions where both intersect.
The pixel 11 includes a thin film transistor TFT, which is a pixel transistor, and a storage capacitor Cs connected in parallel to a liquid crystal cell (not shown). One end (the drain terminal side of the TFT) of the storage capacitor Cs is connected to the pixel electrode (pixel potential VP), and the other end is connected to the common potential Vcom.

In FIG. 1, the same components as those of the conventional display device 1 are denoted by the same reference numerals.
That is, the vertical drive circuit 16 is connected to the scanning line 13 and sequentially selects the rows of the pixels 11.
The horizontal drive circuit 17 is connected to the signal line 12 and operates based on a predetermined clock signal, and sequentially writes video signals to the pixels 11 in the selected row. In this example, the video signal is divided into two systems, video-a and video-b, which is a two-pixel simultaneous drive system.

The horizontal drive circuit 17 includes a shift register 21, a shaping switch group 22, and a sampling switch group 23. The shift register 21 performs a shift operation in synchronization with a clock signal input from the outside, and sequentially outputs shift pulses from each shift stage. The shaping switch group 22 shapes the shift pulses sequentially output from the shift register 21 and sequentially outputs the sampling pulses Vh1 and Vh2.
In the illustrated example, the sampling pulse Vh1 is output from the N stage, and the sampling pulse Vh2 is output from the next N + 1 stage.

The sampling switch group 23 sequentially samples the input video signals video-a and video-b in response to the sampling pulses Vh1 and Vh2, and supplies them to the signal lines 12.
In the illustrated example, the sampling switch 23-1 samples the video signals video-a and video-b in response to the sampling pulse Vh1, and supplies them to the two signal lines 12-1 and 12-2, respectively. . The next sampling switch 23-2 samples the video signals video-a and video-b in response to the sampling pulse Vh2, and supplies them to the two signal lines 12-3 and 12-4, respectively.
Here, a plurality of pixels in the horizontal direction connected by a plurality of signal lines corresponding to each sampling pulse is referred to as a unit. In the example of FIG. 1, each sampling pulse Vh1, Vh2 controls a different unit.

The difference between the conventional display device 1 described with reference to FIG. 3 and the display device 1a according to the present embodiment is in the pixel portion 15a. That is, as shown in FIG. 3, all of the conventional pixel portions 15 are connected to a common common potential Vcom. On the other hand, the pixel portion 15a according to the present embodiment includes each unit as shown in FIG. Each is connected to a different common potential Vcom1, Vcom2.
For example, the unit 15-1 that is controlled by the sampling pulse Vh1 and includes the pixel portion connected to the signal lines 12-1 and 12-2 is connected to the common potential Vcom1, and is supplied by the sampling pulse Vh2. The unit 15-2 configured by the pixel portion controlled and connected to the signal lines 12-3 and 12-4 is connected to the common potential Vcom2.

The horizontal drive circuit 17 has a configuration similar to that described with reference to FIG.
That is, horizontal clock pulses HCK and HCKX having opposite phases generated by the clock generation circuit 18 and a horizontal start pulse HST and a pair of clocks DCK1 and DCK2 are given, and the clocks DCK1 and DCK2 are sequentially extracted to obtain a sampling pulse Vh1. , Vh2.

Here, normally, the clock DCK1 and the clock DCK2 have an error of 1 to 2 ns, and this error causes a difference ΔV in the pixel potential VP charged by the storage capacitor Cs. Adjustment is made by the potentials Vcom1 and Vcom2.
That is, Vcom2 is set as in the following formula (1).

Vcom2 = Vcom1 ± ΔV (1)

  As described in (1) above, by setting the common potentials Vcom1 and Vcom2, the potential applied to the liquid crystal cell (pixel potential) even when a difference occurs in the pixel potential VP in each of the units 15-1 and 15-2. Since the difference [Delta] V is canceled and becomes constant, no vertical band is generated near the boundary between the units 15-1 and 15-2.

FIG. 2 is a diagram showing a common potential connected to each unit, and is a generalization of the above-described contents.
As described above, the horizontal drive circuit 17 supplies the sampling pulses Vh1 and Vh2 obtained by sequentially extracting the clocks DCK1 and DCK2 of opposite phases to each unit, so that the odd-numbered (odd) unit and the even-numbered (odd) unit ( Even) units are supplied with different sampling pulses.
Therefore, as described above, in order to absorb the difference (error) between the clocks DCK1 and DCK2, as shown in FIG. 2, the common potentials Vcom1 and Vcom2 are set to odd (even) and even (even), respectively. ) To be connected to the unit.

In the example shown in FIG. 2, the units 15-1 and 15-3 that are odd-numbered (odd) units are connected to the common potential Vcom1, and the units 15-2 and 15 that are even-numbered (even) units. -4 is connected to the common potential Vcom2.
Conversely, the common potentials Vcom1 and Vcom2 may be connected to the even-numbered (even) and odd-numbered (odd) units, respectively.

The above-mentioned difference ΔV is, for example, about 0.1 to 0.2 V when the design value of Vcom is 7.5 V.
Further, as the pulse width of the clocks DCK1 and DCK2 becomes smaller, the storage capacitor Cs of the pixel portion is not sufficiently charged, and the pixel potential VP is held in a portion where the change in the charging curve is large, the clock DCK1 and Since the difference in the pixel potential VP between the units due to the difference (error) in the clock DCK2 becomes large, it is necessary to set the difference ΔV to be large in order to absorb that amount. That is, the difference ΔV to be set may be adjusted according to the pulse widths of the clocks DCK1 and DCK2.

As described above, according to the display device 1a according to the present embodiment, different common potentials Vcom1 and Vcom2 are connected to the odd-numbered (odd) and even-numbered (even) units, and the clocks DCK1 to DCK1- Since the difference in the pixel potential VP due to the error of DCK2 is absorbed, a vertical band is not generated at the boundary of each unit.
In particular, even if the width of the sampling pulse is narrowed to improve the ghost margin, the accompanying vertical band is suppressed, so it is possible to improve both the ghost margin and the vertical band. It becomes.

The present embodiment is not limited to the above-described content, and various modifications can be made without departing from the scope of the present invention.
For example, in the above embodiment, different common potentials Vcom1 and Vcom2 are connected to the odd-numbered (odd) and even-numbered (even) units, but the common potential is set independently for each unit without being limited to this. You may comprise.

It is a block diagram which shows the structural example of the liquid crystal display device which concerns on embodiment. It is a figure which shows the application method of the common voltage for every unit of the liquid crystal display device which concerns on embodiment. It is a block diagram which shows the structural example of the conventional liquid crystal display device. It is a circuit diagram which shows the structural example of the horizontal drive circuit of the conventional liquid crystal display device. It is a figure which shows each pulse waveform supplied to a horizontal drive circuit. It is a timing chart which shows the production | generation of a sampling pulse. It is a waveform which shows the charge state of a pixel potential, (a) shows the case where a sampling pulse width is relatively small, and (b) shows the case where a sampling pulse width is relatively large, respectively. It is a figure which shows the vertical belt | band | zone generate | occur | produced in the boundary of each unit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a ... Display apparatus, 12 ... Signal line, 13 ... Scanning line, 15, 15a ... Pixel part, 15-1 to 15-4 ... Unit, 16 ... Vertical drive circuit, 17 ... Horizontal drive circuit.

Claims (4)

A pixel unit in which pixel circuits are arranged in a matrix, a signal line is wired for each column, a scanning line is wired for each row, and a common potential as a reference potential is set for each pixel circuit;
First driving means for applying a scanning pulse to each scanning line of the pixel portion;
In synchronism with the drive pulse given to each signal line group constituted by a predetermined number of units of the signal lines, to the pixel circuit connected to the scan line given the scan pulse from the first drive means, A second driving means for supplying a video signal;
And a common potential setting means for setting the common potential for each signal line group connected to the pixel circuit. The common potential setting means includes
The display device according to claim 1, wherein different common potentials are set for each of the pixel circuits connected to the odd-numbered and even-numbered signal line groups in the signal line group. The common potential setting means includes
The display device according to claim 2, wherein the common potential is set according to a width of a driving pulse given by the second driving unit. The display device according to claim 1, wherein the pixel circuit includes a liquid crystal cell.

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