JP2003122321A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress image defects such as a vertical line and a ghost in an active matrix type display device adopting a split sample hold mode. SOLUTION: A horizontal drive circuit 17 successively generates a sampling pulse which is not overlapped to sampling switches among the sampling switches 23 connected to the same video line 25, successively generates an overlapped sampling pulse to adjacent sampling switches, drives each switch, and successively writes a video signal on the pixel 11 of a selected row. For this purpose, a clock generating means 89 generates a clock signal HCK used as the operating reference of the horizontal drive circuit 17, and a clock signal DCK having a pulse wider than the HCK. The horizontal drive circuit 17 has shift registers 21 which carry out a shift action synchronizing with the HCK and successively output a shift pulse from each shift stage, and a sampling switch group 22 which samples the DCK in response to the shift pulse and successively generates a sampling pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a dot-sequential drive type active matrix display device in which a clock drive system is applied to a horizontal drive circuit of a divided sample hold system.

[0002]

2. Description of the Related Art An active matrix type display device is composed of a panel having row-shaped gate lines, column-shaped signal lines, and pixels arranged in a matrix at the intersection of both lines. For example, a thin film transistor (TFT) is formed as an active element in each pixel. Further, it has a vertical drive circuit and a horizontal drive circuit.
The vertical drive circuit is connected to each gate line and sequentially selects a row of pixels. The horizontal drive circuit is connected to each signal line,
The video signal is written to the pixels in the selected row. At that time, in the dot-sequential driving method, video signals are written in the pixels in the selected row in dot-sequential manner.

In an active matrix type display device,
Parasitic capacitance exists between the source / drain electrodes of the TFT and each of the signal lines. Due to this parasitic capacitance, a potential change when a video signal is written through a certain signal line jumps into an adjacent signal line, which may cause an image defect such as a vertical stripe. This vertical streak defect becomes remarkable especially when a checkerboard pattern is displayed by the line inversion drive method. Alternatively, when a horizontal line of 1 dot (1 pixel) in thickness is displayed by the dot line inversion driving method, vertical stripes are likely to occur.

In order to prevent the video signal from jumping in between the signal lines, so-called divided sample hold driving has been proposed, for example, Japanese Patent Laid-Open No. 2000-26761.
No. 6 publication. The divided sample-hold method is a method in which an input video signal is separated into two systems, and when the video signal is written by the dot-sequential method, the video signals of the two systems are overlapped and written between adjacent pixels.

FIG. 7 is a schematic diagram showing an example of a display device that employs the above-described divided sample hold drive. As shown in the figure, the display device includes row-shaped gate lines 113, column-shaped signal lines 112, pixels 111 arranged in a matrix at the intersection of both lines, and a video signal Video1 divided into two systems according to a predetermined phase relationship. , Video2 supply 2
The panel is composed of video lines 125 and 126. A sampling switch group 123 is arranged corresponding to each signal line 112, and is connected between each of the two video lines in units of two signal lines. Specifically, the first signal line is connected to one video line 125 via the sampling switch, and the second signal line is connected to the other video line 126 via the sampling switch. Hereinafter, also for the third and subsequent signal lines, the two video lines 125 and 126 are alternately passed through the sampling switch.
Connected to. A vertical drive circuit 116 and a horizontal drive circuit 117 are also formed on the panel. The vertical drive circuit 116 is connected to each gate line 113 and sequentially connected to the pixels 11
Select row 1. In other words, the pixels 111 arranged in a matrix are sequentially selected row by row. The horizontal drive circuit 117 operates based on a clock signal having a predetermined cycle, does not overlap the switches connected to the same video line among the switches of the sampling switch group 123, and does not overlap the adjacent switches. The overlapping sampling pulses A, B, C, D
... are sequentially generated to open and close each switch in sequence, and the video signals are written in the pixels 111 in the selected row in a dot-sequential manner. The display device further includes a clock generation circuit 189, and supplies a start pulse HST in addition to the clock signal HCK which is the operation reference of the horizontal drive circuit 117. The horizontal drive circuit 117 is a shift register (S / R) 1
It is composed of 21 multi-stage connection, and by sequentially transferring HST according to HCK, the sampling pulses A, B, and
C, D ... are sequentially generated.

The operation of the conventional display device shown in FIG. 7 will be briefly described with reference to the waveform chart of FIG. As mentioned above,
The horizontal drive circuit operates in response to the clock signal HCK, and sequentially transfers the start pulse HST to generate the sampling pulses A, B, C, D .... As is clear from the figure, the sampling pulses overlap each other between adjacent signal lines. That is, the first
Sampling pulse A corresponding to the signal line of
Of the sampling line B corresponding to the signal line of the above. Similarly, the sampling pulse B corresponding to the second signal line and the sampling pulse C corresponding to the third signal line also overlap. Since video signals are supplied to the signal lines adjacent to each other from different video lines, they may be overlapped. By generating the sampling pulses so that the sampling switches of the adjacent signal lines overlap each other, it is possible to prevent the vertical stripe defect, which has been a problem in the past. That is, even if there is a parasitic capacitance between the source / drain electrodes of each pixel transistor and each of the signal lines, and even if the potential change of a signal line via this parasitic capacitance jumps into the adjacent signal line, the signal Since the line has a low impedance due to overlap sampling, it is not affected by the jump of the video signal.

In the illustrated example, in response to the sampling pulse A, the signal potential Sig1 is applied to the corresponding first signal line.
Is sample-held. Then, in response to the sampling pulse B, the signal potential Sig2 is sampled and held on the second signal line. At this time, a potential change occurs in the second signal line. This potential change also jumps into the first signal line due to the parasitic capacitance. At this time, however, the corresponding sampling switch is still open in the first signal line, so the impedance is low impedance and is affected by the signal jump. Never.

[0008]

FIG. 9 schematically shows the sampling timing of a video signal for each signal line and the potential change of each video line. Basically, sampling pulses are generated so that the sampling switches connected to the same video line do not overlap each other. For example, the first signal line and the third signal line are connected to the same video line. Therefore, the circuit is designed so that the sampling pulse A and the sampling pulse C do not overlap in principle.
However, in reality, delay occurs due to wiring resistance, parasitic capacitance, etc. in the pulse transmission process, and the waveform becomes dull. As a result, the sampling pulse A and the sampling pulse C partially overlap each other. In such a state, when the sampling pulse C rises, the corresponding sampling switch is opened and the signal line is charged / discharged, so that the potential fluctuation occurs in the video signal Video1 on the video line as indicated by the solid arrow. This time,
Since the preceding sampling pulse A has not yet fallen, the potential fluctuation (charging / discharging noise) of the video line is picked up as shown by the dotted arrow. As a result, the potentials sampled on the signal lines vary, which causes vertical stripes on the screen to impair the image quality. Further, such interference of video signals between signal lines connected to the same video line may cause a ghost or the like on the screen.

[0009]

In view of the above-mentioned problems of the prior art, the present invention occurs between signal lines connected to the same video line in an active matrix type display device adopting a so-called divided sample hold method. An object of the present invention is to suppress the interference of video signals and thus suppress image defects such as vertical stripes and ghosts. The following measures have been taken to achieve this purpose. That is, the display device according to the present invention has a row-shaped gate line, a column-shaped signal line, pixels arranged in a matrix at a portion where both lines intersect, and n lines (n is an integer of 2 or more) in a predetermined phase relationship. ), A panel having n video lines for supplying video signals, a vertical drive circuit connected to the gate lines to sequentially select pixel rows, and arranged corresponding to each signal line.
A sampling switch group connected between each of the n video lines and each of the n video lines as a unit, and operating based on a clock signal of a predetermined cycle, and among the switches of the sampling switch group, Pixels in the row selected by sequentially generating sampling pulses that do not overlap switches that are connected to the same video line but overlap adjacent switches and drive each switch in order. A horizontal drive circuit that sequentially writes video signals to the first clock signal, and a first clock signal that serves as an operation reference for the horizontal drive circuit, and a second clock signal that has a longer pulse width than the first clock signal. The horizontal drive circuit performs a shift operation in synchronization with the first clock signal. A shift register for sequentially outputting the shift pulse; and a sampling switch group for sampling the second clock signal in response to the shift pulse sequentially output from the shift register to sequentially generate the sampling pulse. And

Preferably, the clock generating means is arranged outside the panel and externally supplies the first clock signal to the horizontal drive circuit, and the second clock is formed inside the panel. Is internally divided into an internal clock generating circuit for supplying the clock signal to the horizontal drive circuit. In this case, the internal clock generation circuit processes the first clock signal supplied from the external clock generation circuit to generate the second clock signal. Specifically, the internal clock generation circuit includes a delay circuit that delays the first clock signal, and the first clock signal before the delay processing and the first clock signal after the delay processing are performed. And the second clock signal. In this case, the delay circuit includes an even number of inverters connected in series. The internal clock generation circuit NORs the first clock signal before the delay processing and the first clock signal after the delay processing with each other.
It has a NOR circuit which synthesize | combines and produces | generates this 2nd clock signal.

According to the present invention, in the display device employing the divided sample hold drive, the shift pulse output from the horizontal drive circuit is extracted by another clock signal to generate the sampling pulse. By introducing such a clock drive method, the sampling pulse between adjacent signal lines can be kept 1
Every non-overlapping sampling pulse is realized between the signal lines connected to the same video line every other line.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic block diagram showing an embodiment of a display device according to the present invention. As shown in the figure, this display device includes row-shaped gate lines 13, column-shaped signal lines 12, pixels 11 arranged in a matrix at the intersection of both lines, and video signals divided into two systems in a predetermined phase relationship. 2 to supply Video1 and Video2 separately
It is composed of a panel having video lines 25 and 26 of a book. It should be noted that although two systems of video signals are used in the present embodiment, generally, n systems of video signals having a predetermined phase relationship can be used. In this case, n video lines may be provided. However, n is an integer of 2 or more.
This display device has a vertical drive circuit 1 in addition to the panel described above.
6, a horizontal drive circuit 17 and a clock generation means 89 are included. Preferably, the vertical drive circuit 16 and the horizontal drive circuit 17 are built in the panel. A sampling switch group 23 is also formed on the panel. Each switch of the sampling switch group 23 is arranged in correspondence with each signal line 12, and two signal lines are used as a unit.
Connected to each of the video lines of the book. Specifically, the switch corresponding to the first signal line is connected to one video line 25, and the switch corresponding to the second signal line is connected to the other video line 26.
In this way, the signal lines 12 are alternately connected to the two video lines 25 and 26. Generally, the sampling switch group 23 has n signal lines as a unit, and
It will be connected between each of the video lines of the book.

The vertical drive circuit 16 is connected to each gate line 13 and sequentially selects the pixels 11 in row units. The horizontal drive circuit 17 operates based on a clock signal having a predetermined cycle,
Of the switches of the sampling switch group 23, the sampling pulses A, B, C, D ... Which are not overlapped with the switches connected to the same video line but are overlapped with the adjacent switches. Are sequentially generated to sequentially drive the respective switches, and the video signals Video1 and Video are sequentially supplied to the pixels 11 in the selected row.
Write o2.

As a feature of the present invention, the clock generating means 89 generates a first clock signal HCK which is an operation reference of the horizontal drive circuit 17, and has a pulse width longer than that of the first clock signal HCK. The second clock signals DCK1 and DCK2 are generated. On the other hand, the horizontal drive circuit 17 includes a shift register 21 and a sampling switch group 22. Each stage of the shift register 21 is S
It is represented by / R. The shift register 21 synchronizes with the first clock signal HCK and outputs the horizontal start pulse HST.
, And the shift pulses A, B, C, D ... Are sequentially output from each shift stage S / R. The start pulse HST is supplied from the clock generation means 89. Each switch of the sampling switch group 22 has shift pulses A, B, C, D sequentially output from the shift register 21.
In response to the second clock signals DCK1, DCK
2 is extracted and the sampling pulse A ′,
B ', C', D '... are sequentially generated. In this way, the horizontal drive circuit 17 does not overlap the switches connected to the same video line among the switches of the sampling switch group 23, but does not overlap the adjacent switches. Pulses are sequentially generated to drive each switch in sequence. For example,
The sampling pulses A ′ and B ′ overlap, while A ′ and C ′ are completely non-overlapping.

The operation of the display device shown in FIG. 1 will be described with reference to FIG. The horizontal drive circuit 17 operates in response to a first clock signal HCK (hereinafter sometimes referred to as an HCK pulse), and sequentially transfers a start pulse HST to generate shift pulses A, B, C, and D. ing. The clock generation means 89 supplies the second clock signals DCK1 and DCK2 (hereinafter sometimes referred to as DCK pulse) to the horizontal drive circuit 17 in addition to the HCK pulse. As is clear from the timing chart of FIG. 2, the DCK pulse has the same period as the HCK pulse, but the pulse width is large. Also, DCK1 and DCK2 are out of phase with each other by 180 degrees.

The horizontal drive circuit 17 shown in FIG. 1 drives the sampling switch group 22 to open and close with each shift pulse A, B, C, D, ... And extracts the DCK pulse. As a result, the sampling pulses A ', B', C ', D' ...
Is being generated. Specifically, the sampling pulse A ′ is generated by extracting the pulse of DCK1 with the shift pulse A. Similarly, the sampling pulse B ′ is obtained by extracting the pulse of DCK2 with the shift pulse B. Similarly, by sampling the DCK pulse with the shift pulse, the sampling pulse C ′,
I'm getting D '... By introducing such a clock drive system, adjacent sampling pulses are kept overlapping, and every other signal line connected to the same video line is completely non-overlapped. . For example, the sampling pulses A ′ and B ′ overlap and A ′ and C ′ completely non-overlap.

By adopting the complete non-overlap, it is possible to deal with vertical stripes and ghosts which are peculiar to the dot-sequential drive type active matrix type display device. For example, in the example of FIG. 2, the video signal Video1 is correctly sampled on the corresponding signal line when the sampling pulse A ′ falls, as indicated by the dotted arrow. After that, when the sampling pulse C ′ rises as shown by the solid arrow, charging and discharging of the signal line occurs,
The electric potential of the video signal Video1 fluctuates downward, and noise is added. However, since the sampling pulse A'has already fallen at the time when this noise occurs, it has no effect.

As described above, in the present invention, the clock drive system using the DCK pulse is introduced for the divided sample hold drive. In order to support the divided sample hold drive, DCK pulses having a longer pulse width and different duty ratios are used as the pulses extracted by the clock drive. This DCK is generated by the shift pulse output from each stage of the shift register.
By extracting the pulses, adjacent sampling pulses are kept overlapping, while sampling pulses corresponding to the same video line are non-overlapping. In this way, vertical stripes in a specific pattern such as a checkered pattern in dot line inversion drive or a 1-dot horizontal line pattern in dot line inversion drive can be removed, and vertical stripes and ghosts peculiar to a dot-sequential active matrix display device can be eliminated at the same time. It is possible.

FIG. 3 is a schematic block diagram showing a specific structural example of the display device according to the present invention. As shown in the figure, the display device includes a pixel array section 15 and a vertical drive circuit 16.
And the panel 3 in which the horizontal drive circuit 17 and the like are integrated
It is composed of three. The pixel array section 15 is composed of row-shaped gate lines 13, column-shaped signal lines 12, and pixels 11 arranged in a matrix at the intersections of the two. The vertical drive circuit 16 is divided into left and right,
The rows of the pixels 11 are sequentially selected by connecting to both ends of the gate line 13. The horizontal drive circuit 17 is connected to the signal line 12 and operates based on the HCK pulse having a predetermined cycle to sequentially write the video signal to the pixels 11 in the selected row. This display device is provided with a clock generation means, and generates an HCK pulse which is an operation reference of the horizontal drive circuit 17 and also generates a DCK pulse which has the same cycle and a large pulse width with respect to this HCK pulse. HCK
The pulse is a clock signal HCK and its inverted signal HCKX.
Is included. The DCK pulse is the clock signal DC
It includes K1, DCK1X, DCK2 and DCK2X. DCK1X is an inverted signal of DCK1, and DCK2
X is an inverted signal of DCK2. DCK1 and DCK2 are 180 degrees out of phase with each other. For simplicity of illustration, the video lines and the sampling switch group are omitted from the panel 33. In addition, a precharge circuit 20 is connected to each signal line 12, and a potential of a predetermined level is applied to each signal line 12 in advance before sampling a video signal from the horizontal drive circuit 17 side.
We are trying to improve the display quality.

As a feature of this embodiment, the clock generating means is divided into an external clock generating circuit 18 and an internal clock generating circuit 19. The external clock generation circuit 18 is mounted on a driving system board (not shown) outside the panel 33, and the first clock signal HCK,
HCKX is supplied to the internal horizontal drive circuit 17 from the outside. On the other hand, the internal clock generation circuit 19 is formed inside the panel 33 together with the vertical drive circuit 16 and the horizontal drive circuit 17, and the second clock signals DCK1 and DCK1.
X, DCK2, DCK2X are internally generated and supplied to the horizontal drive circuit 17. The internal clock generation circuit 19 processes the HCK pulse supplied from the external clock generation circuit 18 to generate a DCK pulse. Like this, D
By creating the CK pulse inside the panel, it is possible to prevent an increase in the number of input pads formed on the panel 33. If all the HCK and DCK pulses are supplied from the outside, six input pads are required. By creating the DCK pulse inside the panel, four input pads can be reduced.

FIG. 4 is a block diagram showing a specific configuration example of the internal clock generation circuit 19 shown in FIG. First
Focusing on the system (1), the first clock signal HCK supplied from the external clock generation circuit is divided into two. One is directly supplied to one input terminal of the NOR circuit 55. The other is supplied to a delay circuit composed of four inverters 51 to 54 connected in series. The output of this delay circuit is supplied to the other input terminal of the NOR circuit 55. In this way, the HCK that has not been subjected to the delay processing and the HCK ′ that has been subjected to the delay processing are NORed by the NOR circuit 55.
Is synthesized. The signal output from the NOR circuit 55 is inverted by the inverter 56 and then output via the buffer 57 as the clock signal DCK1. Also, NO
The signal output from the output terminal of the R circuit 55 is branched and output as DCK1X via the buffer 58 and is sent to the horizontal drive circuit side. It is generally known that the pulse signal is delayed every time it passes through the inverter. Therefore, in this example, the clock signal HCK ′ that has passed through the plurality of inverters is not the clock signal HCK that has not passed through the inverters.
It is delayed by several tens of nanoseconds as compared with. By synthesizing these two clock signals HCK and HCK ′ by NOR, HCK
Target clock signals DCK1, DC with longer pulse width
K1X can be created. DCK2, DCK2X
Is similarly generated in the system (2).

FIG. 5 is a waveform diagram for explaining the operation of the internal clock generation circuit shown in FIG. (1) represents the operation of the first system (1) shown in FIG. 4, and (2) represents the operation of the second system (2) also shown in FIG. Focusing on (1), HCK 'is delayed by a predetermined time compared to HCK. This delay amount can be optimally set depending on the number of inverters connected in series. HCK and HCK 'that are out of phase with each other due to the delay processing are set to N
DCK1X with wider pulse width by OR processing
Is obtained. When DCK1X is inverted by the output inverter, DCK1 is obtained. Similarly, as shown in (2), DCK is performed by logically processing HCKX that has not been subjected to delay processing and HCKX ′ that has been subjected to delay processing.
2 is obtained. If this DCK2 is inverted, DCK2
X is obtained.

FIG. 6 is a circuit diagram showing a structural example of a dot-sequential drive type active matrix type liquid crystal display device according to an embodiment of the present invention in which a liquid crystal cell is used as a display element (electro-optical element) of a pixel, for example. is there. Here, for simplification of the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example. In an active matrix type liquid crystal display device, a thin film transistor (TFT) is usually used as a switching element for each pixel.

In FIG. 6, 4 rows 4 arranged in a matrix.
Each of the pixels 11 for columns includes a thin film transistor TFT which is a pixel transistor, and a liquid crystal cell LC in which the pixel electrode is connected to the drain electrode of the thin film transistor TFT,
One of the electrodes is connected to the drain electrode of the thin film transistor TFT, and the storage capacitor Cs is formed. For each of these pixels 11, signal lines 12-1 to 12-4 are arranged in columns along the pixel arrangement direction, and gate lines 13-1 to 13-4 are arranged in each row in the pixel arrangement direction. Is routed along.

In each of the pixels 11, the source electrode (or drain electrode) of the thin film transistor TFT is connected to the corresponding signal line 12-1 to 12-4. The gate electrodes of the thin film transistors TFT are connected to the gate lines 13-1 to 13-4, respectively. Liquid crystal cell L
The counter electrode of C and the other electrode of the storage capacitor Cs are commonly connected to the Cs line 14 between the pixels. This Cs
A predetermined DC voltage is applied to the line 14 by the common voltage Vcom.
Given as.

As described above, the pixels 11 are arranged in a matrix, and the signal lines 12-1 to 12-4 for the pixels 11 are arranged.
Are wired for each column and gate lines 13-1 to 13-4
The pixel array section 15 is formed by wiring each row. In the pixel array section 15, one end of each of the gate lines 13-1 to 13-4 is connected to the output terminal of each stage of the vertical drive circuit 16 arranged on the left side of the pixel array section 15, for example.

The vertical drive circuit 16 scans in the vertical direction (row direction) every one field period to scan the gate line 13-1.
Processing for sequentially selecting the pixels 11 connected to 13-4 in units of rows is performed. That is, when the scanning pulse Vg1 is applied from the vertical drive circuit 16 to the gate line 13-1, the pixel in each column of the first row is selected and the gate line 1 is selected.
2 when scan pulse Vg2 is applied to 3-2
Pixels in each column of the row are selected. Similarly, the scan pulses Vg3 and Vg are applied to the gate lines 13-3 and 13-4.
g4 is given in order.

A horizontal drive circuit 17 is arranged, for example, above the pixel array section 15. In addition, the vertical drive circuit 1
6 and an external clock generation circuit (timing generator) for supplying various clock signals to the horizontal drive circuit 17
18 is provided. This external clock generation circuit 18
Then, a vertical start pulse V for instructing the start of vertical scanning
ST, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, a vertical start pulse HST for instructing the start of horizontal scanning, and horizontal clocks HCK and HCKX having opposite phases as a reference for horizontal scanning are generated.

An internal clock generating circuit 19 is provided separately from the external clock generating circuit 18. In this internal clock generation circuit 19, the horizontal clocks HCK, HCKX
, A pair of clocks DCK1 and DCK2 having the same cycle and a long pulse width are generated.

The horizontal drive circuit 17 includes two video lines 2
Video signals Video1 and Vid input from 5, 26
eo2 is sequentially sampled for each 1H (H is a horizontal scanning period) and is written in each pixel 11 selected by the vertical drive circuit 16 in units of rows. In this example, the clock drive method is used. This is adopted and has a configuration including a shift register 21, a clock sampling switch group 22 and a sampling switch group 23.

The shift register 21 includes a pixel array section 15
Of four shift columns (S / R) 21-1 to 21-4 corresponding to the pixel columns (4 columns in this example), and when the horizontal start pulse HST is applied, the horizontal clocks H having opposite phases to each other.
The shift operation is performed in synchronization with CK and HCKX. Thus, the shift stages 21-1 to 21-4 of the shift register 21 sequentially output shift pulses A to D having the same pulse width as the period of the horizontal clocks HCK and HCKX.

The clock extraction switch group 22 includes four switches 22-1 corresponding to the pixel columns of the pixel array section 15.
22 to 22-4, one end of each of the switches 22-1 to 22-4 is supplied from the internal clock generation circuit 19 to the clock DCK.
2, clock lines 24-1, 24-2 for transmitting DCK1
Alternately connected to. That is, the switch 22-1,
22-3 has one end connected to the clock line 24-1 and the switch 2
One end of each of 2-2 and 22-4 is connected to the clock line 24-2.

A shift pulse A sequentially output from each shift stage 21-1 to 21-4 of the shift register 21 is applied to each switch 22-1 to 22-4 of the clock sampling switch group 22.
~ D is given. The switches 22-1 to 22-4 of the clock sampling switch group 22 respond to the shift pulses A to D when the shift pulses 21 to 21-4 of the shift register 21 receive the shift pulses A to D, respectively. Then, the clocks DCK having opposite phases to each other are sequentially turned on.
2. Take out DCK1 alternately.

The sampling switch group 23 includes four switches 23-1 to 23-2 corresponding to the pixel columns of the pixel array section 15.
3-4, one end of each of these switches 23-1 to 23-4 is alternately connected to a video line 25 for inputting a video signal Video1 and a video line 26 for inputting Video2. The clocks DCK2 and DCK1 extracted by the respective switches 22-1 to 22-4 of the clock extracting switch group 22 are input to the respective switches 23-1 to 23-4 of the sampling switch group 23 as sampling pulses A '.
Given as ~ D '.

The switches 23-1 to 23-4 of the sampling switch group 23 are connected to the sampling pulses A'from the switches 22-1 to 22-4 of the clock sampling switch group 22, respectively.
~ D ', these sampling pulses A'
The video signals Vide input through the video lines 25 and 26 are sequentially turned on in response to ~ D '.
o1 and 2 are sequentially sampled alternately, and the pixel array unit 1
5 signal lines 12-1 to 12-4.

In the horizontal drive circuit 17 according to the present embodiment having the above-described structure, the shift pulses A to D sequentially output from the shift register 21 are directly sampled from the sampling pulses A'to.
Instead of being used as D ′, a pair of clocks DCK2 and DCK1 are alternately extracted in synchronization with the shift pulses A to D, and these clocks DCK2 and DCK1 are used as sampling pulses A ′ to D ′. As a result, variations in the sampling pulses A ′ to D ′ can be suppressed. As a result, it is possible to remove the ghost caused by the variation of the sampling pulses A ′ to D ′.

[0037]

As described above, according to the present invention, the clock drive is performed using the DCK pulse having a long pulse width and a different duty ratio with respect to the HCK pulse which is the operation reference of the horizontal drive circuit. . As a result, complete non-overlap sampling compatible with divided sample hold driving is achieved, and vertical stripes and ghosts are suppressed. At the same time, when sampling pulses assigned to adjacent signal lines are overlapped by divided sample hold driving, a specific pattern such as a dot checkerboard pattern during line inversion driving or a 1-dot horizontal line pattern during dot line inversion driving is displayed. It is also possible to remove the vertical streaks in. In addition, by combining DCK pulses inside the panel based on HCK pulses supplied from the outside, it is possible to prevent an increase in the number of input pads and the number of input wirings.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a display device according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the display device shown in FIG.

FIG. 3 is a block diagram showing a specific configuration example of the display device shown in FIG.

FIG. 4 is a block diagram showing a specific configuration example of an internal clock generation circuit incorporated in the display device shown in FIG.

5 is a timing chart provided for explaining the operation of the internal clock generation circuit shown in FIG.

FIG. 6 is a circuit diagram showing a configuration example of a dot-sequential driving type active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a conventional display device.

8 is a waveform diagram provided for explaining the operation of the conventional display device shown in FIG.

9 is a waveform diagram for explaining the operation of the conventional display device shown in FIG.

[Explanation of symbols]

11 ... Pixel, 12 ... Signal line, 13 ... Gate line, 15 ... Pixel array section, 16 ... Vertical drive circuit, 17 ... Horizontal drive circuit, 18 ... External clock Generation circuit, 19 ... Internal clock generation circuit, 2
1 ... shift register, 22 ... sampling switch group,
23 ... Sampling switch group, 89 ... Clock generating means

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 623M 623R F term (reference) 2H093 NA42 NB07 NB25 NC23 NC34 ND49 5C006 AC09 AC11 AC18 AC21 AF43 AF50 AF71 BB16 BC11 BC16 BF07 BF11 BF24 BF27 FA01 FA16 FA36 FA42 5C080 AA10 BB05 DD10 DD23 FF11 JJ02 JJ03 JJ04

Claims (6)

[Claims] 1. A line-shaped gate line, a column-shaped signal line, pixels arranged in a matrix at the intersection of both lines, and an image divided into n systems (n is an integer of 2 or more) according to a predetermined phase relationship. A panel having n video lines for supplying signals, a vertical drive circuit connected to the gate lines to sequentially select pixel rows, and arranged corresponding to each signal line. A sampling switch group connected between each of the n video lines as a unit and operating based on a clock signal of a predetermined cycle, and connected to the same video line among the switches of the sampling switch group. Selected switches are sequentially driven by sequentially generating sampling pulses that do not cause the overlapped switches to overlap and adjacent switches to overlap. A horizontal drive circuit that sequentially writes video signals to pixels in a row, and a second clock that generates a first clock signal that serves as an operation reference of the horizontal drive circuit and has a pulse width that is longer than the first clock signal. A horizontal drive circuit that performs a shift operation in synchronization with the first clock signal and sequentially outputs a shift pulse from each shift stage; and a sequential sequence from the shift register. And a sampling switch group for sampling the second clock signal in response to the output shift pulse and sequentially generating the sampling pulses. 2. The clock generating means is an external clock generating circuit arranged outside the panel to externally supply the first clock signal to the horizontal drive circuit, and the clock generating means formed inside the panel. The display device according to claim 1, wherein the display device is divided into an internal clock generation circuit that internally supplies a clock signal to the horizontal drive circuit. 3. The display according to claim 2, wherein the internal clock generation circuit processes the first clock signal supplied from the external clock generation circuit to generate the second clock signal. apparatus. 4. The internal clock generation circuit includes a delay circuit that delays the first clock signal, and the first clock signal before the delay processing and the first clock signal after the delay processing are performed. The display device according to claim 3, wherein the second clock signal is generated by the second clock signal. 5. The display device according to claim 4, wherein the delay circuit includes an even number of inverters connected in series. 6. The internal clock generation circuit NOR-synthesizes the first clock signal before being subjected to the delay processing and the first clock signal after being subjected to the delay processing with each other to perform the second synthesis.
6. The display device according to claim 5, further comprising a NOR circuit that generates the clock signal.