KR100337851B1 - Active Matrix Display - Google Patents

Abstract

An object of the present invention is to eliminate the band-like defects appearing in the horizontal end portion of the screen when the active matrix display device is driven in a sequential order.

The configuration of the active matrix display device includes a plurality of gate lines X wired in a row, a plurality of data lines Y wired in a column, and a plurality of pixels PXL provided at respective intersections thereof. Have. The pixels PXL arranged in a matrix constitute the display area 1. The vertical scanning furnace 2 sequentially scans each gate line X, and selects the pixels PXL of one row at every horizontal period. The horizontal scanning furnace 3 sequentially scans each data line Y within one horizontal period, samples the image signal Vsig, and writes the image signal Vsig in the dot sequence to the selected pixel PXL. . The data line (Y) is a dummy data line (Y1, Y2, ..., YL) wired in the display area (1), and dummy data arranged outside the display area (1) and intersecting with an end portion of the gate line (X). It is divided into lines YD1, YD2, YD3, and YD4. The horizontal scanning furnace 3 performs horizontal scanning in a plurality of overlapping sampling timings of the actual data lines Y1, Y2, ..., YL, and then sequentially piles the dummy data lines YD1, YD2, YD3, and YD4. ), Horizontal scanning is continued at the overlapping sampling timing.

Description

Active matrix display

The present invention relates to an active matrix display. More specifically, the present invention relates to a stripping defect elimination technique that appears in the longitudinal direction of the screen of an active matrix display device driven in a sequential manner.

Referring to FIG. 8, a general configuration of a conventional active matrix display device will be described briefly. The active matrix display device has a plurality of gate lines X wired in a row, a plurality of data lines Y wired in a column, and a plurality of pixels PXL provided at respective intersections thereof. The pixel PXL is, for example, a fine liquid crystal cell and is arranged in a matrix to form a display area. The thin film transistor Tr is integrally formed to drive it corresponding to the individual pixels PXL. Further, a vertical scanning path 101 is provided, and each gate line X is sequentially vertically scanned to select one row of pixels PXL every one horizontal period. In addition, each data line (Y) is sequentially scanned within a horizontal period having the horizontal scanning channel (102), the image signal (Vsig) is sampled, and the image signal (Vsig) is provided in a sequential order to the pixels PXL selected. ). Specifically, each data line Y is connected to the video line 103 via a horizontal switch HSW and externally supplied with a video signal Vsig. Pyeongju Social Furnace 102 outputs the sampling pulses (Ø _H1 , Ø _H2 , Ø _H3 , ..., Ø _HN ) in sequence, and sequentially opens and closes each horizontal switch (HSW) to display the image signal ( Vsig).

9 shows waveforms of sampling pulses sequentially output from the horizontal scanning furnace 102 shown in FIG. The sampling pulse width [tau] _H is determined corresponding to the sampling time allocated to the individual data lines (Y). As the high-precision miniaturization of the active matrix display device proceeds, the number of pixels is significantly greater and the writing time per dot is significantly shortened. In addition, in an active matrix display device compatible with HDTV, the write time per one dot is shortened to speed up line scanning. Corresponding to this, the sampling pulse width tau _H becomes extremely narrow. For example, in an NTSC-compatible half-line active matrix display device having a horizontal 470 pixels, the sampling pulse width is about τ _H = 50 Hz / 470/3 (RGB) = 320 nsec. When this becomes 800 pixels horizontally, τ _H = 188 nsec. In addition, double-speed drive in a full-line configuration significantly shortens the sampling time at τ _H = 94 nsec. As the sampling pulse width is reduced in this manner, there is a strain on the waveform shaping point, which complicates the configuration of the horizontal scan and at the same time narrows the design margin. In addition, since a sufficient writing time of the video signal cannot be obtained, a burden is placed on the liquid crystal panel side, and various proposals are made in design.

In order to cope with shortening of the sampling pulse width τ _H , for example, a method disclosed in Japanese Patent Application Laid-Open No. 1-37911 has been proposed. As shown in FIG. 10, the pulse widths of the sampling pulses Ø _H1 , Ø _H2 , Ø _H3 , and Ø ₄ . In other words, the method shifts while selecting a plurality of data lines at the same time. For example, as shown in FIG. 10, when four data lines are selected simultaneously, the sampling pulse width becomes τ _H = 4 x 188 nsec = 750 nsec in the case of horizontal 800 pixels.

This method also reduces the design burden on the driving side and the liquid crystal panel side of the horizontal scanning lamp.

However, as a method of sequentially shifting a plurality of data lines simultaneously, there is a problem that a band-like defect 105 occurs at the horizontal scanning direction end portion of the display region 104 constituting the screen as shown in FIG. .

For example, in the normally white mode, the band defect 105 appears darker than the normal part. This band defect 105 is caused by the fact that the overlapping of the sampling pulses is released at the end side of the horizontal scanning so that the driving conditions are different from other normal areas.

In view of the above-described problems of the prior art, the present invention aims to eliminate the band-like defects appearing at the end portions of the horizontal scanning direction in the point-sequential driving of the active matrix display device. In order to achieve this object, the following measures have been taken. In other words, the active matrix display device according to the present invention has a basic configuration in which a plurality of gate lines wired in a row form, a plurality of data lines wired in a column form, and a plurality of intersecting portions are formed at each intersection to form a display area. Equipped with pixels. It also has vertical and horizontal chamber furnaces as the periphery. In the vertical scanning, each gate line is sequentially vertically scanned to select one row of pixels every horizontal period. On the other hand, in the horizontal scanning, each data line is sequentially scanned within one horizontal period, the image signal is sampled, and the image signals are written in dot order to the pixels of the selected row. As a feature of the present invention, the data line is divided into a real data line wired in the display area and a dummy data line wired outside the display area and intersecting the terminal side of the gate line. In the horizontal scanning, horizontal scanning is performed at a plurality of overlapping sampling timings with respect to actual data lines, and horizontal scanning is further added at overlapping sampling timings with respect to the dummy data lines. In this case, the dummy data lines are wired at least as many as horizontal scanning at the same time at the overlapping sampling timing. The dummy pixel is also assigned to this dummy data line. Alternatively, the pixel may be removed from the dummy data line.

According to the present invention, a dummy data line is added outside the display area adjacent to the last part of the real data line wired in the display area. In the horizontal scanning, horizontal scanning is continuously performed over the real data line and the dummy data line. Therefore, even when the display region reaches the end portion, the overlapping sampling timing is maintained over a plurality of real data lines, and since the normal image display is performed, no band-shaped defects occur. When the horizontal scan reaches the dummy data line, the overlapping sampling timing is released and the display form changes in some cases. However, since the dummy data line is disposed outside the display area, the dummy data line does not appear on the screen.

(Example)

Best Mode for Carrying Out the Invention The most preferred embodiment of the present invention will now be described in detail with reference to the drawings. 1 is a circuit diagram showing an embodiment of an active matrix display device related to the present invention. As shown in the drawing, the active matrix display device includes a plurality of gate lines X wired in a row and a plurality of data lines Y wired in a column. In addition, the pixels PXL are arranged in a matrix at the intersections of the two to form the display area 1. In addition, the pixel PXL is formed of, for example, a liquid crystal cell having a microstructure. In the present embodiment, the thin film transistor Tr is provided because the pixel PXL composed of the liquid crystal cell is driven. The source electrode of each thin film transistor Tr is connected to the corresponding data line Y, the gate electrode is connected to the corresponding gate line X, and the drain electrode is connected to the corresponding pixel PXL.

A vertical scanning furnace 2 and a horizontal scanning furnace 3 are provided around the display area 1 described above. The vertical scanning furnace 2 sequentially scans each gate line X and conducts the above-described thin film transistor Tr to select one row of pixels PXL every one horizontal period. On the other hand, the horizontal scanning furnace 3 sequentially scans each data line Y in one horizontal period, samples the image signal Vsig, and writes the image signal Vsig in the dot sequence to the selected pixel PXL. do. Specifically, each data line Y is connected to the video line 4 via a horizontal switch HSW to receive the video signal Vsig. The horizontal scanning furnace 3 sequentially outputs the sampling pulse Ø and its inverted pulse to open and control the individual horizontal switches HSW and to sample the above-described video signal Vsig. The image signal Vsig sampled on each data line Y is written in one row of pixels PXL via the thin film transistor Tr in an on state. Since the thin film transistor Tr is turned off, the written image signal Vsig is maintained until the next frame.

As a feature of the present invention, the data lines are real data lines Y1, Y2, ..., YL arranged in the display area 1, and dummy data lines YD1, YD2, YD3 arranged outside the display area 1; , YD4). These dummy data lines intersect the terminal side of the gate line X. In the present embodiment, the pixel PXL and the thin film transistor Tr are removed from the dummy data line. However, the present invention is not limited to this, and dummy pixels and thin film transistors may also be allocated to the dummy data lines to completely equalize the driving conditions. On the other hand, the horizontal scanning furnace 3 scans not only the actual data line but also the dummy data line. In other words, the horizontal scanning furnace 3 performs horizontal scanning with overlapping sampling timings over the actual data lines Y1, Y2, ..., YL over a plurality (four in this example). Again, horizontal scanning is added at the same sampling timing for the dummy data lines YD1, YD2, YD3, and YD4 successively. In this case, only the number of dummy data lines that are horizontally scanned at the same time at least at overlapping sampling timings is wired. That is, in this embodiment, at least four dummy data lines are provided. More specifically, the horizontal scanning furnace 3 is connected to the sampling pulses Ø ₁ , Ø ₂ , and Ø _L with respect to the horizontal switch HSW connected to the actual data lines Y1, Y2, ..., YL. The inverted pulses are output sequentially. The sampling pulses Ø _D1 , Ø _D2 , Ø _D3 , and Ø _D4 are sequentially applied to the horizontal switches HSW connected to the dummy data lines YD1, YD2, YD3, and YD4 sequentially. In this example, since the transmission gate made of CMOS is used as the horizontal switch HSW, an inverted pulse is also applied.

Next, referring to FIG. 2, the operation of the active matrix display shown in FIG. 1 will be described in detail. As shown in the timing chart of the figure, sampling pulses are output at four sampling timings overlapped with the real data lines, and horizontal scanning (real scanning) is performed on the display area 1. The timing chart shows only five parts to the final real sampling pulse (Ø _L ) for ease of understanding. In this embodiment, after the sampling pulse Ø _L rises, the dummy sampling pulses Ø _D1 , Ø _D2 , Ø _D3 , and Ø _D4 are sequentially output at the overlapping timing with respect to the dummy data line, and the display area ( 1) Perform another horizontal scan (dummy scan). When the sampling pulses Ø are sequentially output at the overlapping timings as described above, the potential shaking of the gate line Y is caused by the capacitive coupling occurring at the intersection between the gate line Y and the data line X. Since the capacitive coupling continues to be received as each sampling pulse Ø rises, the potential of the gate line X continues to shake until the final dummy sampling pulse Ø _D4 rises. After the final dummy sampling pulse Ø _D4 rises, the capacitive coupling is not received, so the potential of the gate line Y is attenuated toward the point level.

On the other hand, at the time when each sampling pulse Ø is lowered, the horizontal switch HSW shifts from the on state to the off state. When the HSW is closed, the potential shake of the gate line jumps to each signal line Y by the above-described capacitive coupling.

As a result, if the potential shake of the gate line is started after attenuation, it affects and also attenuates the potential of the signal line X through capacitive coupling. As understood from the timing chart of FIG. ₂ , the gate line is applied to the potential _VL-4 , V _L-3 , V _L-2 , V _L1 , V _L of the real data line because the corresponding HSW is already off. After the potential fluctuations of, the attenuation starts simultaneously, and finally, the voltage drop occurs for ΔV 0. Therefore, since the voltage drop ΔV0 is the same for all the real data lines, the display density does not appear uneven.

On the other hand, for example, after the potential fluctuation of the gate line is cured with respect to the first dummy data line YD1, only one clock delay is delayed so that the corresponding dummy sampling pulse Ø _D1 falls. In synchronism with this descending time point, the potential V _D1 of the dummy data line YD1 starts attenuation so that the final voltage drop? V1 becomes smaller than? V0. Similarly, since the potential V _D2 of the second dummy data line YD2 starts to attenuate by one more clock delay, the final voltage drop ΔV2 becomes smaller. In this way, the voltage drops of the dummy data lines are different and the display concentration is varied. However, since the dummy data line is located outside the display area 1, it does not affect the actual image. As described above, the horizontal scanning furnace 3 performs horizontal scanning with an extra four pixels more than the effective display area 1. In addition, four dummy data lines are provided in the same array as the effective display area 1 including the HSW. Since four dummy data lines are provided, the potential fluctuations of the gate lines continue in the same manner as the four pixels even after passing through the effective display area 1. For this reason, the shaking of the signal line included in the display area 1 does not change suddenly at only the terminal portion. In the present embodiment, four signal lines are simultaneously scanned horizontally, but in general, when scanning N signal lines at the same time, there may be N or more dummy data lines. The dummy data line does not necessarily require a pixel or a driving transistor, and even if omitted, a band-shaped defect can be sufficiently reduced.

Finally, the mechanism of occurrence of band-shaped defects will be described for reference with reference to FIGS. 3 to 7. FIG. 3 shows the configuration of a general active matrix display device, which is the same as the circuit shown in FIG. 8, and corresponding parts are labeled with corresponding reference numerals for easy understanding. Reference is made particularly to the reference numerals used in the following description. The potential of the video line 103 to which the image signal Vsig is supplied is represented by VA. The potential of each data line Y is represented by VB. In addition, the potential of each gate line X is represented by VC. The parasitic capacitance Ch is interposed at the intersection of each gate line X and the data line Y, which causes the capacitive coupling described above. Each gate line X also includes a resistance component.

4 shows the change over time of the potentials VA, VB, and VC of each line described above. As shown in the drawing, the sampling pulse Ø _H is output from the horizontal scanning furnace 102 so that the image signal Vsig is sampled and maintained on the corresponding data line. The potential VB of the sampled data line and the potential VC of the gate line are flat at first glance, but the variation is caused by the above-described capacitive coupling when the sampling timing is expanded. In other words, the signal of the differential wave form is superimposed on the gate potential (VC). The data potential VB also has attenuation (degate) from the level once sampled and held.

5 shows an equivalent circuit of this part. The individual data lines intersect all gate lines since the corresponding HSW. For this reason, the equivalent circuit contains the equivalent capacitance C _H corresponding to the total of the parasitic capacitance Ch shown in FIG. In the equivalent circuit, C _G is the total capacity of the gate line itself, and R _G is the equivalent gate line resistance. In such a circuit, the data potential VB rises and the gate potential VC rises accordingly. When the HSW is closed, the attenuation of the gate potential VC is fully reflected in the data potential VB as it is.

This is shown in the timing chart of FIG. 6, for example, in the case of four-line simultaneous scanning. Here, the final sampling pulses (Ø _H , _LAST ) to the sampling pulses are shown for ease of explanation. Charging and discharging to the signal line is repeated until the final sampling pulses Ø _H and _LAST . As a result, the gate potential VC receives an increase in the angle Ø _H. After the rise of Ø _H and _LAST ends, the gate potential (VC) is not capacitively coupled and therefore attenuates toward the ground level. On the other hand, each signal line jumps the gate potential through the capacitance component C _H shown in the equivalent circuit of FIG. 5 after the corresponding HSW is closed. At the timing before Ø _H and _LAST-4 , go to the level of the signal line and change only ΔV0 as indicated by VB _LAST-4 . However, as Ø _H , _LAST-3 , Ø _H , and _LAST-1 ..., the level at which the attenuation of the gate potential VC jumps into the signal line is reduced. That is, the voltage drop (ΔV1, ..., _ΔV4 ) of the potentials VB _LAST-3 , ..., VB _LAST of the last four signal lines decreases.

This ΔV is shown schematically in FIG. For the last four signal lines, ΔV decreases as compared with all previous signal lines. The degree of reduction is increased as it approaches the final signal line. As a result, a band-like defect occurs in the last four lines.

As described above, according to the present invention, in addition to the actual data lines wired in the display area, dummy data lines wired outside the display area are provided. Horizontal scanning is performed at overlapping sampling timings over a plurality of real data lines, and horizontal scanning is further added at overlapping sampling timings for dummy data lines, thereby eliminating band defects, thereby improving image quality. Lose. In particular, the present invention is extremely effective when point sequential driving is performed in a large sized active matrix display device or the like in which the number of pixels is extremely increased.

1 is a circuit diagram showing the configuration of an active matrix display device according to the present invention.

FIG. 2 is a timing chart provided to explain the operation of the active matrix display shown in FIG.

3 is a reference circuit diagram for providing a description of the band defect.

4 is a reference timing chart showing the configuration of the active matrix display device according to FIG.

FIG. 5 is a reference equivalent circuit diagram showing the configuration of the active matrix display device of FIG.

FIG. 6 is a reference timing chart showing the configuration of the active matrix display device related to FIG.

FIG. 7 is a reference graph showing the configuration of the active matrix display device related to FIG.

8 is a circuit diagram showing a general configuration of a conventional active matrix display device.

9 is a timing chart used to explain the operation of the active matrix display shown in FIG.

FIG. 10 is a timing chart provided to explain the operation of the active matrix display shown in FIG.

11 is a schematic diagram showing a band-shaped defect appearing in the display area.

* Explanation of symbols on the main parts of the drawings

1. Display area 2. Vertically

3. Horizontally 4. Video Line

X. Gate Line Y. Data Line

HSW. Horizontal switch PXL. Pixel

Tr. Thin film transistor

Claims (4)

A plurality of gate lines wired in a row shape, a plurality of data lines wired in a column shape, a plurality of pixels provided at each intersection of the two to form a display area, and a vertical scan of each gate line sequentially and horizontally A vertical scanning path for selecting one row of pixels per period, and a horizontal scanning path for sequentially scanning each data line and sampling the video signal and writing the video signals in dot-sequential order to pixels of the selected row within a horizontal period. Active matrix display, The data line is divided into a real data line wired in the display area and a dummy data line wired outside the display area and intersecting the terminal side of the gate line. An active matrix display device configured to perform horizontal scanning on a plurality of overlapping sampling timings for a real data line, and then add horizontal scanning on overlapping sampling timings on a dummy data line consecutively; . The method of claim 1, And the dummy data line is configured such that only at least the number of horizontal scans is simultaneously wired at an overlapping sampling timing. The method of claim 1, And a dummy pixel is also assigned to the dummy data line. The method of claim 1, And a pixel is removed from the dummy data line.