JPH07261706A - Display driving device - Google Patents

Abstract

PURPOSE:To provide high resolution display by eliminating a color display failure. CONSTITUTION:A clock signal CLK having a 3/2 pixel period as a cycle and a start pulse SP for starting sampling are generated, based on these clock signal CLK and start pulse SP sampling pulses delayed by three pixel periods are sequentially generated by a pulse determining circuit and a column electrode driving circuit and by means of these sampling pulses pixel data of three adjacent red, green and blue colors are simultaneously sampled by a sampling circuit. Thus, since three dots of adjacent R, G and B are simultaneously sampled, color reproduction is improved and the structure of the column electrode driving circuit is made simple. Also, since a clock signal having a frequency 2/3 of a conventional clock frequency is inputted, occurences of unnecessary width projection and logic erroneous actions are prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention exhibits red (hereinafter referred to as R), green (hereinafter referred to as G), and blue (hereinafter referred to as B), such as a liquid crystal display device, an electroluminescence display device, and a plasma display. The present invention relates to a display drive device in which three adjacent pixels are arranged everywhere and each pixel is arranged in a matrix at positions where row electrodes and column electrodes intersect, and more particularly, to a display drive device for the column electrodes.

[0002]

2. Description of the Related Art An example of this type of display driving device is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-24770 (name: amorphous silicon thin film transistor liquid crystal panel driving method, international patent classification: H04N). In this prior art, when a certain point of a color image is displayed on the matrix type display device, there is no method of displaying a single pixel as a mixed color of three colors of R, G and B. , G and B are used to adjust the shading of each color of R, G, and B, and display the combined color of the three colors. For this reason, R, G, and
The three colors of B occupy the display screen over a wide area of 3 pixels instead of one point, and the image becomes considerably rough.
Therefore, the matrix of the display screen is made dense so that three pixels occupying the display screen correspond to one point, or the time for sampling the pixel signals to be given to the pixels exhibiting each color of R, G, B from the video signal, respectively. It is necessary to devise to shift the pixel according to the display position of each pixel on the screen.

Here, a TFT liquid crystal display device will be described as an example with reference to FIG. FIG. 9 is a block diagram of a conventional TFT liquid crystal display device having a display panel in which pixels are arranged in a matrix. In FIG. 9, dots as picture elements having a plurality of R, G, and B colors are arranged in a matrix, column electrode driving circuits 1 and 2 are alternately arranged, and odd-numbered column electrodes and even-numbered column electrodes are arranged. The column electrodes are scanned by separate drive circuits. TFTs that are thin film transistors in odd-numbered columns
Source S is connected to the column electrode drive circuit 1 via the source bus line SU, and the source S of the TFT in the even-numbered column is connected to the column electrode drive circuit 2 via the source bus line SD. . The drain D of the TFT is connected to the pixel electrode, and the gate G is connected to the row electrode drive circuit 3 via the gate bus line g.

As described above, each pixel is arranged at the intersection of the row electrode g and the column electrode s, and the transparent pixel electrode and the TFT are arranged.
It consists of Each of these pixels has R,
When the white light from the backlight, which has G and B filters, changes the transmittance of the liquid crystal according to the pixel signal applied to the pixel electrode and whose intensity is adjusted by the liquid crystal, passes through the filter. The color of the filter is shown in different shades. Here, the filter color that each pixel has is described as R, G, or B.

With the above structure, the row electrode drive circuit 3 applies an ON voltage to the row electrodes g in order from the first row electrode g1.
At this time, this on-voltage is simultaneously supplied to the gates G of the plurality of TFTs connected to one row electrode g, and simultaneously turns on the TFTs as analog switches. Further, the column electrode drive circuits 1 and 2 respectively include pixel signals VR, VG, and R, G, and B pixel signals included in the video signal during the sampling period (τ) based on the externally applied start pulse SP and clock signal CK. VB is sampled and the column electrodes SU1, S connected to the pixels exhibiting R, G, B, respectively.
It is given to D1 and SU2. Here, for example, when the TFT on the row electrode g1 is turned on, the source S and the drain D of the TFT are
The pixel electrodes VR1, VG and VB generated by the column electrode drive circuits 1 and 2 are electrically connected to each other and the column electrodes SU1, SD1 and
It is given to the pixel electrodes of R, G, and B pixels via SU2 and held.

The transmittance of the liquid crystal changes in accordance with the pixel signal applied to the pixel electrode, and when the white light from the backlight whose intensity is adjusted by the liquid crystal passes through the filter, the color of the filter becomes shaded. Will be presented. In this way, the mixed color that should be originally displayed at one point is displayed by the three primary colors R, G, and B at each of the three adjacent pixels, and when the user visually recognizes these composite colors, these pixels are displayed. Since the display position of is shifted by the length L (= τ), the pixel signals VR, VG, and VB given to these pixels must also be shifted by one pixel, and the sampling time must also be shifted by one dot period τ. There is. In this way, the three-point sequential sampling method is used in which the pixels of three adjacent points are individually sampled sequentially.

Such 3-point sequential sampling will be described with reference to the drawings. Column electrode drive circuit 1 in this case
FIG. 10 is a block diagram thereof, FIG. 11 is a block diagram of the column electrode drive circuit 2, and FIG. 12 is a timing chart of these. In FIGS. 9 to 12, pixel signal terminals VR, VG, and VB are respectively supplied with video signals VR, VG, and VB which are pixel signals. A start pulse SP and a clock signal CK having a period of 2dots 2τ are applied to the control terminals SP and CK, respectively. The pulse width determination circuit 4 of the column electrode drive circuit 1 receives the start pulse SP and outputs a pulse SPU having a predetermined pulse width.
To generate. Further, the pulse width determination circuit 5 of the column electrode drive circuit 2 receives the start pulse SP and generates a pulse SPD having a predetermined pulse width.

Next, the D flip-flops DU1, DU2, DU connected in series in the column driving circuit 1 shown in FIG.
.. take in the pulses SPU, QU1, QU2, QU3, .. given to the input terminal D when the clock signal CK given to the input terminal ck rises, and as shown in FIG. The pulses QU1, QU2, QU3, QU4, ...
These are supplied to each sampling circuit 6. For example, since the pulse periods of the pulses QU1, QU2, U3 are each shifted by a time 2τ, the pulses QU1, QU2,
Video signals VR, VB, V captured by each QU3
Each G pixel signal has a video signal that is shifted by two pixels. Therefore, the video information of the pixel signal supplied to the column electrode by the output buffer circuit 7 is shifted by two pixels, that is, by the length of 2L.

Similarly, serially connected D flip-flops DD1, DD2 in the column driving circuit 2 shown in FIG.
Since the input terminals ck of DD3, ... Are given to the input terminals ck via the inverter 8, the terminals CK
Pulses SPD, QD1, QD applied to the input terminal D when the clock signal CK applied to
, QD3, ..., and the pulses QD1, QD2, QD3, Q whose time is delayed by 2τ as shown in FIG.
D4, ... Are sequentially generated, and these are generated in each sampling circuit 9
Give to each. For example, pulses QD1, QD2, QD
Since the pulse periods of 3 are each shifted by time 2τ, the pixel signals of the video signals VG, VR, VB captured by the pulses QD1, QD2, QD3 are 2 respectively.
It will have video signals that are offset by pixels. Therefore, the video information of the pixel signal supplied to the column electrode by the output buffer circuit 10 is shifted by 2 pixels, that is, by the length of 2L.

As described above, since the output of the column electrode drive circuit 1 and the output of the column electrode drive circuit 2 are connected to the scan lines of the odd and even columns, respectively, the row electrodes for simultaneously taking in these pixel signals. Each pixel on g receives the pixel signal from the column electrode drive circuit 1 and the column electrode drive circuit 2 every other pixel. Therefore, since the pixel electrodes charged by the column electrode driving circuit on one side are displaced by a length of 2 L, no mismatch of images occurs at the time of visually recognizing the image.

Another conventional example of 3-point sequential sampling will be described in detail with reference to the drawings.

FIG. 13 shows a configuration diagram of a conventional matrix type liquid crystal display device of delta arrangement, and FIG. 14 shows a circuit diagram of a column electrode drive circuit for driving the matrix type liquid crystal display device of FIG. Further, FIG. 15 shows waveforms of the shift lock pulse and the sampling pulse when driving the matrix type liquid crystal display device of the delta arrangement of FIG. 13 to 15, the transistors Aa1, Ab1,
..., Aai, Abi, ... Aan, Abn, transistors Ba1, Bb1, ..., Bai, Bbi, ...
.., Ban, Bbn, and transistors Ca1, C
b1, ..., Cai, Cbi, ..., Can, Cb
The signal input to the gate g is n
At the h "level, the source s and the drain d are brought into conduction and turned on as an analog switch, and conversely, the gate g.
When the signal input to the source goes to "Low" level, the source s
The drain d becomes non-conducting and becomes an off state as an analog switch. In addition, each output buffer F1,
..., Fi, ... Fn amplify the video signals input from the Va and Vb terminals to appropriate values, and generate pixel signals VS1,
..., VSi, ... VSn are output. Further, the transistors Ca1, ..., Cai, ... Ca
An output switching signal CNTA is input to each of the gates g of n, and the transistors Cb1, ..., Cbi ,.
.., output switching signal CN to gates g of Cbn
TB is input. These output switching signals CNTA,
CNTB is inverted and is 1/2 of line period H
Since the "High" level and the "Low" level are repeated every time, first, the transistor C
, Cai is turned on, and transistors Cb1, ..., Cbi, ... Cbn are turned off, and transistors Ca1 ,. , ... Can are turned off, and transistors Cb1, ..., Cbi, ..., Cbn are turned on.

The shift registers 11 and 12 are supplied with shift clocks CK1 and CK2 having a period τ as shown in FIGS. 15a and 15b. Shift clock CK
The shift clock CK2 is delayed by τ / 2 with respect to 1 on the time axis, and the phase is shifted by τ / 2.
As shown in FIG. 15c, a start pulse SP is supplied to these shift registers 11 and 12 at the beginning of one line period. The shift register 11 starts the shift operation when the start pulse SP is input, and the timing of the shift operation is performed every cycle τ in synchronization with the rising edge of the shift clock CK1. Similarly, the shift register 12 starts the shift operation when the start pulse SP is input, and the timing of the shift operation is performed every cycle τ in synchronization with the rising edge of the shift clock CK2.

As a result, the shift register 11 has the transistors Aa1, ..., Aai, of the sample-hold circuit.
, Aan, the sampling pulses Sa1, ..., Sai ,.
As shown in FIGS. 5d to 15h, the pulse has a period of τ and is sequentially delayed by τ. Similarly, the shift register 12 supplies sampling pulses Sb1, ..., Sb to the gates g of the transistors Ab1, ..., Abi ,.
, i, ..., Sbn are sampling pulses Sa1, ..., Sai, ... As shown in FIGS.
The only difference is that it is shifted by τ / 2 from San.

As described above, the shift clock / CK2 is delayed from the shift clock CK1 by τ / 2 on the time axis and the phase thereof is shifted by π / 2.
The timing of starting the shift operation of each of the shift registers 11 and 12 is delayed by τ / 2 on the time axis. Therefore, the sampling period instructed by the sampling pulse Sb1 to the transistor Ab1 is delayed by τ / 2 on the time axis with respect to the sampling period instructed by the sampling pulse Sa1 to the transistor Aa1. Since the same applies to the following, the sampling period designated by each of the sampling pulses Sb1, ..., Sbi ,.
, ..., Sai, ... San are delayed by τ / 2 on the time axis with respect to the sampling period designated by each.

Further, the transistors Aa1, ..., A
The video signal Va is input to the sources s of ai, ..., Aan, and the transistors Ab1, ..., Abi ,.
The source s of Abn is supplied with the video signal Vb whose positive and negative polarities are reversed in correspondence with the video signal Va. The coordinates of the pixel in FIG. 13 are defined with reference to the intersection of the row electrode and the column electrode, and the column electrodes S1, S2, ...
2, ... Shown by the value of Gn. The video signal Va is applied to each pixel electrode 13 (1, j), 13 in time series for each period of τ with respect to the array of pixels arranged on one odd row electrode Gj.
, (Va1, ..., Van) applied to (2, j), ... 13 (n, j) are arranged. The video signal Vb corresponds to the array of pixels arranged on one even-row electrode G (j + 1) adjacent to the odd-row electrode line Gj, and the pixel electrode 13 of each pixel is time-series for each period of τ.
(1, (j + 1)), 13 (2, (j + 1)), ...
13 (n, (j + 1)) signal voltage Vb1, ...
.., Vbi, ... Vbn are arranged.

Therefore, the signal voltages Va1, ..., Vai, ... Van on the video signal Va can be sampled by the sampling pulses Sa1, ..., Sai, ... San, and similarly on the video signal Vb. , Vbi, ..., Vbn can be sampled by the sampling pulses Sb1, ..., Sbi ,. Further, the signal voltages Vb1, ..., Vbi, ... Vbn are delayed from the signal voltages Va1, ..., Vai, ... Van by .tau. / 2 corresponding to a half pixel on the time axis. It will be.

In each pixel connected to the odd-numbered row electrode G1 shown in FIG. 13, for example, the i-th pixel exhibits only G (green), and thus is applied to the pixel electrode 13 (i, 1) of this pixel. The signal voltage Vai is generated to reproduce the brightness of green, and the pixel electrode 13 is generated from the column electrode Si via the TFT 14 (i, 1) which is a transistor.
Is transferred to (i, 1). Similarly, in each pixel connected to the even-numbered row electrodes G2 shown in FIG. 13, for example, the i-th pixel exhibits only red R, so that the pixel electrode 1 of this pixel
The signal voltage Vbi applied to 3 (i, 2) is generated in order to reproduce the brightness of red, and the pixel voltage 13 (i, 2) is generated from the column electrode Si via the TFT 14 (i, 2).
It is transferred to 2). The same applies to other pixels.

Next, a driving procedure for the above-mentioned driving circuit will be described.

With the above configuration, first, in one line period, the sampling pulses Sa1, ..., Sai ,.
..San, sampling pulses Sb1, ..., Sb
Since i, ... Sbn sequentially become “High” level, the transistors Aa1, Ab1, ..., Aai, A
bi, ..., Aan, Abn are sequentially turned on,
Signal voltages Va1 and Vb obtained from the video signals Va and Vb
1, ..., Vai, Vbi, ..., Van, Vbn
Are sampling capacitors Da1, Db1, ..., D
.., Dan, and Dbn are sequentially sampled. The above is the three-point sequential sampling method.

Further, as another sampling method,
There is a three-point simultaneous sampling method as shown in FIG. 16 of Japanese Patent Application Laid-Open No. 3-158895, in which signal voltages of three pixels given to pixels R, G and B are sampled as one unit. In this method, sampling pulses Sa1 ′, ..., Sai ′, ..., San ′, in one line period
Sb1 ', ..., Sbi', ..., Sbn 'are shown in FIG.
As shown in FIGS. 6n to 16s and 16t to 16y, the horizontal 3 dots are regarded as one unit and sequentially become the “High” level. Therefore, the transistors Aa1, Ab1 ,.
, i, Abi, ..., Aan, Abn are also turned on by three stages each, and the signal voltage V obtained from the video signals Va, Vb
a1, Vb1, ..., Vai, Vbi, ..., Va
n, Vbn are sampling capacitors Da1, Db1,
..., Dai, Dbi, ..., Dan, Dbn 3
It is sampled step by step. The following operation is the same in both the 3-point sequential sampling method and the 3-point simultaneous sampling method.

In one line period, sampling capacitors Da1, Db1, ..., Dai, Dbi, ...
After the above sampling operations by Dan, Dbn are all completed, the line switch signal voltage T changes to "High".
all transistors Ba
1, Bb1, ..., Bai, Bbi, ..., Ba
Since n and Bbn are turned on all at once, each signal voltage V
a1, Vb1, ..., Vai, Vbi, ..., Va
n and Vbn are the hold capacitors Ea1, Eb1, ...
.., Eai, Ebi, ..., Ean, Ebn are held.

In this way, each hold capacitor Ea1, Eb1, ..., Eai, Ebi, during one line period.
..., the signal voltage Va held by Ean and Ebn
1, Vb1, ..., Vai, Vbi, ..., Va
Each of n and Vbn is the pixel electrode 13 (1, 1) of each pixel of the matrix type liquid crystal panel 15 of the delta arrangement shown in FIG.
13 (i, 1), ..., 13 (n, 1), 13 (1,
2), ..., 13 (i, 2), ..., 13 (n,
It is transferred to 2).

A line selection signal V applied to the row electrode G1
First, the G1 becomes the “High” level during the 1/2 line period, and the TFT 14 (1,
1), ..., 14 (i, 1), ..., 14 (n,
1) is turned on. During this period, the output switching signal CNTB is at the “Low” level and the output switching signal CNT is
Since A is at "High" level, the transistor Cb
, ..., Cbi, ..., Cbn are all in the off state, and transistors Ca1, ..., Cai ,.
,, Can are all turned on all at once, so that the pixel signal V is applied to each column electrode S1, ..., Si ,.
, Vbn are not output as S1, ..., VSi, ..., VSn, and signal voltages Va1, ..., Vai ,.
Only will be output respectively.

Therefore, each signal voltage Va1, ...
Vai, ..., Van are TFTs 14 (1, 1) connected to the row electrodes G1 that are in the ON state all at once, ...
, 14 (i, 1), ..., 14 (n, 1) through the pixel electrodes 13 (1, 1) ,.
1), ..., 13 (n, 1), respectively.

In the remaining 1/2 line period, the line selection signal VG2 applied to the row electrode G2 becomes "High" level, and the TFT 14 (1, connected to the row electrode G2.
2), ..., 14 (i, 2), ..., 14 (n,
2) are all turned on. During this period, the output switching signal CNTA is at the “Low” level and the output switching signal CNT is
Since B is at "High" level, the transistor Ca
, Cai, ..., Can are all in the off state, and transistors Cb1, ..., Cbi ,.
Since n and n are all turned on at the same time, each column electrode S
, ..., Si, ..., Sn are the pixel signals VS1,
.., VSi, ..., VSn as signal voltage Va
, ..., Vai, ..., Van are not output, but only the signal voltages Va1, ..., Vbi ,. Therefore, each signal voltage Vb1,
, Vbi, ..., Vbn are connected to the row electrodes G2 that are in the ON state all at once.
2), ..., 14 (i, 2), ..., 14 (n,
2) via the pixel electrodes 13 (1, 2), ..., 13
, (13, (n, 2)).

That is, the sample hold circuit SAMa1,
, SAMi are for holding video signals Va1, ..., Vai, ..., Van related to the pixels connected to the electrodes G1, G3 ,. , The sample hold circuit SAMb1,
..., SAMbi, ..., SAMbn hold video signals Vb1, ..., Vbi, ..., Vbn relating to pixels connected to the row electrodes G2, G4 ,. become.

When the matrix type liquid crystal panel 15 of the delta arrangement shown in FIG. 13 is driven in this way, as described above, the signal voltages Va1 applied to the pixels connected to the row electrodes G1, G3, ... ..., Vai, ... V
With respect to an, video signals Vb1, ..., Vb given to the pixels connected to the row electrodes G2, G4, ...
Since i, ... Vbn is delayed by half a pixel, the phenomenon that the pixel boundary line is disturbed is lost, and a clear image is reproduced on the display panel 15 in the delta arrangement.

[0029]

[Problems to be Solved by the Invention]
In the dot-sequential sampling method, as shown in FIG. 12, since the period of the clock signal CK used is a 2-dot period 2τ, the input clock frequency is considerably high, and the input clock frequency is further increased as the number of horizontal pixels is increased. Therefore, it causes unnecessary radiation and malfunction of the logic. Further, since it is necessary to shift the sampling pulse for every two dots, the column electrode drive circuits 1 and 2 are complicated.

As described above, when three-point sequential sampling is performed, the cycle of the clock signal CK must be set to 2dot period 2τ as shown in FIG. 12, and if the number of horizontal pixels is increased, the frequency of the clock signal CK must be increased. Therefore, problems such as generation of unnecessary radiation and malfunction of logic occur. Further, in the case of color display, since a point that should originally be displayed as one point is represented by three adjacent points R, G, and B,
Since the sampling times of R, G, and B are each shifted by τ, it becomes difficult to reproduce the color that should originally be displayed at one point.

Next, in the three-point sequential sampling, as shown in FIG. 17, a sampling pulse Sa1 for sampling the signal voltages V _R , V _G and V _B given to the R, G and B pixels from the video signal Vc. , Sa2, Sa3 to generate a shift clock CK1 having a period of 1 dot (=
.tau.), the signal voltage obtained by sampling also becomes a signal level of a portion that differs by one dot period (= .tau.) in time series, and R, G, and The difference in B signal level appears as a problem of defective color display.

For example, in a liquid crystal display panel (normally white mode), when a binary digital video signal as shown in FIG. 19a is input to pixels of each horizontal line to display a black vertical line, The generated video signal is likely to have a blunt rising and falling waveform as shown in FIG. 19B due to the output impedance, wiring resistance, and capacitance of the video amplifier. When the video signal given to each pixel is sampled by the sampling clock shown in FIG. 19c, the timing thereof corresponds to the dull part of the video signal, and the timing shown in FIG.
Not only the level becomes low like the R voltage of
One R data will be sampled twice. In the example of FIG. 19, sampling is not performed twice. For this reason, the R video signal has a lower voltage level than the expected value and is sampled twice more. Therefore, what should originally be displayed as one dot extends over two dots, and the R pixel in the next stage is colored. Since the lines are also sampled at the same timing, a thin vertical line adjacent to the vertical black line with color blur is displayed.

Further, since the cycle of the shift clock CK1 is one dot period (= τ), the clock frequency becomes high, and if the input clock frequency is further increased as the number of horizontal pixels is increased, unnecessary radiation occurs or logic is generated. Cause malfunction.

Further, in the case of three-point simultaneous sampling, FIG.
As shown in FIG.
Since the signal voltages V _R ', V _G ' and V _B 'given to G and B are sampled at the same timing by the sampling pulses Sa1', Sa2 'and Sa3', there is no problem of display failure as described above. Since the signal voltage of the same level occupies three horizontal dots, a high resolution cannot be obtained in a display device having a small number of horizontal pixels.

The present invention solves the above conventional problems, and an object of the present invention is to provide a display driving device which eliminates color display defects and has a high resolution display capability.

[0036]

A display driving device according to the present invention has a plurality of pixels having respective colors of red, green and blue arranged in a matrix, and a sampling pulse is used to display red,
Display that has a holding means for fetching and holding the green and blue video signals, scans the odd-numbered column electrodes and the even-numbered column electrodes with separate driving circuits, and supplies the video signals to the respective pixels for display. In the driving device, a clock signal generating means for generating a clock signal having a period of 3/2 pixel period, a start pulse generating means for generating a start pulse for starting sampling, and 3 sequentially based on the clock signal and the start pulse. Sampling pulse generating means for generating the sampling pulse delayed by the pixel period, and three red points adjacent to each other by the sampling pulse,
The present invention is provided with a sampling means for sampling green and blue pixels at the same time, thereby achieving the above object.

Further, in the display driving device of the present invention, red, green, and blue pixels are arranged in a delta pattern every adjacent horizontal odd line and horizontal even line of a plurality of pixels arranged in a matrix. In a display drive device that supplies video signals to the plurality of pixels for display, the sampling timings of the video signals supplied to the pixels are simultaneously sampled in two colors adjacent in the horizontal direction, and another color is sampled at the next timing. It has a sampling means that repeats sampling so as to sample one color, and thereby achieves the above object.

Further, in the display driving device of the present invention, red, green, and blue pixels are arranged in a delta pattern every three horizontal pixels adjacent to each other in a horizontal odd line and a horizontal even line. In a display drive device for supplying a video signal to the plurality of pixels for display, a first sampling pulse for sampling a video signal to be applied to one pixel of the horizontal odd line of the display panel, and a first sampling pulse of the display panel. The present invention has the sampling means for shifting the phase of the second sampling pulse for sampling the video signal to be applied to the pixels of the horizontal even-numbered lines adjacent to each other, thereby achieving the above object.

[0039]

With the above configuration, the clock frequency is 2 /
Since it is driven by 3, it is possible to increase the number of horizontal pixels while suppressing the occurrence of unnecessary radiation and the malfunction of the logic, and the color reproducibility is improved. Moreover, the configuration of the column electrode drive circuit is simplified.

Further, means for simultaneously sampling the video signals to be given to adjacent pixels of red, green and blue at the sampling timing of the signals and sequentially sampling another one point, or an image to be given to the pixels of the odd line of the display device By sampling the video signal by a means for shifting the phase of the timing of the sampling pulse of the signal and the timing of the sampling pulse of the video signal given to the pixels on the even lines, the composite color of one point of the video signal is added to adjacent horizontal odd numbers. It is possible to display 3 pixels of red, green, and blue by combining lines and horizontal even lines.

Since the levels of the signal voltages supplied to these three pixels are sampled at the same timing, there is no problem in color display failure, and the display range is from horizontal 3 dots to horizontal 2 dots as in the case of conventional three-point simultaneous sampling. , And the sampling pulse shift timing can be performed in every 1.5 pixels (1.5τ), so that it can be driven at a low clock frequency for 3-point sequential sampling, compared to the conventional 3-point simultaneous sampling. High resolution can be obtained.

[0042]

EXAMPLES Examples of the present invention will be described below. A drive circuit of a matrix type display device will be described by taking a drive circuit for driving a TFT liquid crystal display device as an example.

FIG. 1 is a block circuit diagram of a column electrode drive circuit of odd columns in a display drive circuit showing an embodiment of the present invention, and FIG. 2 is a block circuit diagram of a column electrode drive circuit of even columns. Further, FIG. 3 shows a timing chart in the case of performing 2-point 1-point toggle sampling using this column drive circuit.

In FIGS. 1 and 2, the pulse width determination circuit 32 of the column electrode drive circuit 31 receives the start pulse SP, generates a pulse SPU having a predetermined pulse width, and supplies it to the input terminal D of the D flip-flop DU11. Supply. In addition, the pulse width determination circuit 34 of the column electrode drive circuit 33
Receives the start pulse SP, generates a pulse SPD having a predetermined pulse width, and outputs the D flip-flop DD1.
1 to the input terminal D. Here, the terminals CK11,1
Clock signals CK11 and CK12 are input to 2. The clock signals CK11 and 12 are clock signals having a frequency of ⅔ of the clock signal CK of FIGS. 7 and 8.

The D flip-flop DU11 in the column electrode drive circuit 31 has a pulse QU11 delayed in time with respect to the pulse SPU given to the input terminal D when the clock signal CK11 given to the control terminal CK11 rises. To generate. This pulse QU11 is applied to the input terminal D of the D flip-flop DU12 and the sampling circuit 3
Give to 5,36. Furthermore, the D flip-flop DU1
2 is also the terminal CK1 as in the D flip-flop DU11.
The pulse QU11 given to the input terminal D when the clock signal CK11 given to 1 rises,
Pulse QU12 delayed in time with respect to pulse QU11
To generate. This pulse QU12 is applied to the input terminal D of the D flip-flop DU13 and the sampling circuit 37. Hereinafter, the D flip-flop DU13 and the D flip-flop DU14 operate similarly.

The D flip-flop DD11 in the column electrode drive circuit 33 has a pulse QD delayed in time with respect to the pulse SPD applied to the input terminal D when the clock signal CK12 applied to the terminal CK12 rises.
11 is generated. This pulse QD11 is applied to the input terminal D of the D flip-flop DD12 and the sampling circuit 38. Like the D flip-flop DD11, the D flip-flop DD12 also takes in the pulse QD11 given to the input terminal D when the clock signal CK12 given to the terminal CK12 rises and generates the pulse QD12 delayed in time from the pulse QD11. To do. This pulse QD12 is applied to the input terminal D of the D flip-flop DD13 and the sampling circuits 39 and 40. Below, D
Flip-flop DD13 Further D flip-flop D
D14 operates similarly.

As described above, since the clock signals CK11 and CK input to the column electrode drive circuit 31 and the column electrode drive circuit 33 are the same signal, the sampling circuits 35 and 36 of the column electrode drive circuit 31 and the column electrode drive circuit 33 are supplied. The sampling circuit 38 will operate simultaneously. After that, at the next rising of the clock signals CK11 and 12, the sampling circuit 37 of the column electrode driving circuit 31 and the sampling circuits 39 and 40 of the column electrode driving circuit 33 operate simultaneously. The same operation is repeated thereafter.

Therefore, the adjacent three dots of R, G and B can be sampled at the same time, so that the color reproducibility is improved and the structure of the column electrode drive circuit can be simplified. Further, since a clock signal having a frequency of ⅔ of the conventional clock frequency is input, it is possible to avoid unnecessary radiation and malfunction of the logic. Note that FIG. 4 shows a circuit configuration example of the sampling circuit of FIGS. 1 and 2, and FIG. 5 shows a circuit configuration example of the output buffer circuit of FIGS. 1 and 2. Both the sampling circuit and the output buffer circuit are shown. It can be easily configured.

Next, another embodiment of the present invention and still another embodiment will be described. FIG. 6 shows R in another embodiment of the present invention,
The timing diagram of the sampling pulse of the video signal given to each pixel of G and B and the example of a display pattern when a black-and-white vertical line are displayed alternately are shown. FIG. 7 shows a timing chart of sampling pulses of a video signal given to each pixel of R, G, and B in the three-point simultaneous sampling method of still another embodiment of the present invention, and similarly black and white vertical lines are alternately displayed. The example of the display pattern at this time is shown. The wiring pattern of each display pixel is the same as that shown in FIGS. 1 and 2, and the description thereof is omitted here. In FIG. 6, video signals applied to adjacent R (red) and G (green) pixels are simultaneously sampled, and video signals applied to another B (blue) pixel at one point are sampled in order. Further, in FIG. 7, the sampling of the video signal is performed by shifting the phase of the timing of the sampling pulse of the video signal applied to the pixels of the odd line of the display device and the timing of the sampling pulse of the video signal applied to the pixels of the even line. From the above, the composite color of one point of the video signal is shown in FIG.
It is possible to display three pixels of R, G, and B (delta arrangement) by combining horizontal odd-numbered lines and horizontal even-numbered lines as shown in FIG.

Since the levels of the signal voltages supplied to these three pixels are sampled at the same timing, there is no problem in color display failure, and the display range is from horizontal 3 dots to horizontal 2 dots as in the case of conventional 3-point simultaneous sampling. , And the sampling pulse shift timing can be performed in every 1.5 pixels (1.5τ), so that it can be driven at a low clock frequency for 3-point sequential sampling, compared to the conventional 3-point simultaneous sampling. High resolution can be obtained.

That is, the waveform W (3) shown in FIGS. 6 and 7.
~ W (14) is for sampling the signal voltage given to each pixel of R, G, B of the display panels 41, 42,
Sb of sampling pulses Sa1, Sa2, Sa3, ..., Sb generated by the shift registers 9 and 10 of FIG.
, Sb2, Sb3, ..., Sampling pulses Sa1 ′, Sa2 ′, Sa3 ′, ..., Sb1 ′,
The timings of Sb2 ', Sb3', ... Are shown.

Further, the sampling pulses Sa1, Sa2, Sa3, ..., Sb1, S in FIG. 6 and FIG.
b2, Sb3, ..., Sampling pulse Sa
1 ', Sa2', Sa3 ', ..., Sb1', Sb
.. are synchronized with the rising edge of the shift clock CK, sampling is started when the start pulse SP is input, and sampling pulse S
a1, Sa2, Sa3, ..., Sb1, Sb2, Sb
3, ..., Sampling pulses Sa1 ′, Sa
2 ', Sa3', ..., Sb1 ', Sb2', Sb
3 ′, ... At the rising edge of the transistor Aa in FIG.
1, Ab1, ..., Aai, A _bi , ..., Aan,
Abn sequentially turns on, and the signal voltage changes to the sampling capacitors Da1, Db1, ..., Dai, Dbi,
..., Dan and Dbn are sequentially sampled.

R in a delta array composed of the first and second rows of the display pattern on the display panel 41 of FIG.
Looking at the sampling waveform of the video signal given to each of the G and B pixels, sampling pulses W (3), W (4), W (8) and W (5), W (6 ) And W (7) always rise at the same timing, so R, G, and B 3 pixels (delta array) in which horizontal odd lines and horizontal even lines are combined
It can be seen that the video signals given to are always simultaneous. As a result, the problem of color display failure due to the timing shift of the video signals given to the R, G, and B pixels in the delta array does not occur.

Therefore, comparing the sampling method in the black and white display pattern of the display panel 41 displaying the vertical lines with the three-point simultaneous sampling method in FIG. 7, the black and white vertical lines in the sampling method in the present invention are displayed. The display pattern of the display panel 41 occupies a pixel range of horizontal 3 dots to display one line each for black and white, whereas the three-point simultaneous sampling method occupies a pixel range of horizontal 6 dots to display one line each for black and white. This occupies the range, and the sampling method in the present invention can simply obtain a doubled degree of resolution as compared with the three-point simultaneous sampling method.

Here, as an example, the sampling of the video signal applied to the R and G pixels is performed at the same timing, but the sampling of the video signal applied to the G and B pixels or the B and R pixels is performed at the same timing. Also gives similar results.

[0056]

As described above, according to the first aspect, the clock frequency can be driven at 2/3 of the conventional frequency, and the number of horizontal pixels can be increased while suppressing the occurrence of unnecessary radiation and the malfunction of the logic. It is possible to increase the resolution. Further, since three adjacent R, G, and B dots are sampled at the same time, color reproducibility is improved, and the configuration of the column electrode drive circuit can be simplified.

According to the second and third aspects, it is possible to provide a matrix type display device having a high resolution display capability without causing a problem of color display failure.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a column electrode drive circuit of an odd column in a display drive circuit showing an embodiment of the present invention.

FIG. 2 is a block circuit diagram of a column electrode drive circuit for even columns in a display drive circuit according to an embodiment of the present invention.

FIG. 3 is a timing chart when two-point one-point toggle sampling is performed using the column electrode drive circuit of FIGS. 1 and 2.

FIG. 4 is a circuit diagram of a sampling circuit in the column electrode drive circuit of FIGS. 1 and 2.

5 is a circuit diagram of an output buffer circuit in the column electrode drive circuit of FIGS. 1 and 2. FIG.

FIG. 6 is a diagram showing an example of a sampling pattern of a video signal given to each pixel of R, G, and B and a display pattern when black and white vertical lines are alternately displayed in another embodiment of the present invention. is there.

FIG. 7 shows R, G, B according to still another embodiment of the present invention.
FIG. 9 is a diagram showing an example of a display pattern when a sampling pulse timing of a video signal given to each pixel and a black and white vertical line are alternately displayed.

FIG. 8 is a display pattern diagram of a matrix liquid crystal display device of delta arrangement according to the present invention.

FIG. 9 is a block diagram of a conventional TFT liquid crystal display device having a display panel in which pixels are arranged in a matrix.

10 is a block diagram of a column electrode drive circuit 1 in the TFT liquid crystal display device of FIG.

11 is a block diagram of a column electrode drive circuit 2 in the TFT liquid crystal display device of FIG.

FIG. 12 is a column electrode drive circuit 1 or 2 shown in FIGS.
3 is a timing chart of the main part of FIG.

FIG. 13 is a configuration diagram of a conventional matrix type liquid crystal display device of delta arrangement.

14 is a circuit diagram of a column electrode drive circuit for driving the matrix type liquid crystal display device of FIG.

15 is a waveform diagram of a shift lock pulse and a sampling pulse in a three-point sequential sampling method when driving the matrix type liquid crystal display device of the delta array of FIG.

FIG. 16 is a waveform diagram of a shift lock pulse and a sampling pulse in a three-point simultaneous sampling method when driving a conventional matrix type liquid crystal display device of delta arrangement.

FIG. 17 is a diagram showing an example of a sampling pattern in the 3-point sequential sampling method.

FIG. 18 is a diagram showing an example of a sampling pattern in the three-point simultaneous sampling method.

FIG. 19 is a diagram showing sampling timing waveforms and display data for explaining problems in the 3-point sequential sampling method.

[Explanation of symbols]

3 row electrode drive circuit 11, 12 shift register 13 pixel electrode 14 TFT (thin film transistor) 15 display panel 31, 33 column electrode drive circuit 32, 34 pulse width determination circuit 35, 36, 37, 38, 39, 40 sampling circuit R red Pixel presenting G G pixel exhibiting green B pixel presenting blue L Distance between horizontal pixels τ Delay time between horizontal pixels CK Shift clock SP Start pulse Va, Vb Video signals G1, G2, ..., Gi, ..., Gn Row electrodes S1, S2, ..., Si, ..., Sn Column electrodes VG1, VG2, ..., VGi ,.
Line selection signals VS1, VS2, ..., VSi, ..., VSn
Pixel signal T Line switch signal CNTA, CNTB output switching signal Sa1, ..., Sai, ..., San sampling pulse Sb1, ..., Sbi, ..., Sbn sampling pulse Sa1 ′, Sa2 ′, Sa3 ′ , ... sampling pulse Sb1 ', Sb2', Sb3 ', ... sampling pulse Aa1, ..., Aai, ..., Aan transistor Ab1, ..., Abi, ..., Abn transistor Ba1, ..., Bai, ..., Ban transistors Bb1, ..., Bbi, ..., Bbn transistors Ca1, ..., Cai, ..., Can transistors Cb1, ..., Cbi, ... ., Cbn transistor Da1, ..., Dai, ..., Dan Sampling capacitor Db1, ..., D i, ..., Dbn sampling capacitors Ea1, ..., Eai, ..., Ean hold capacitors Eb1, ..., Ebi, ..., Ebn hold capacitors F1, ..., Fi, ... , Fn output buffers SAMa1, ..., SAmai, ..., SAMan
Sample-and-hold circuit SAMb1, ..., SAMbi, ..., SAMbn
Sample and hold circuit _{V R, V G, V B} , ··· pixel signal _{V R ', V G',} V B ', ··· pixel signal

Claims (3)

[Claims] 1. An odd-numbered column having holding means for arranging a plurality of pixels having respective colors of red, green, and blue in a matrix form and receiving and holding red, green, and blue video signals by sampling pulses. In a display drive device in which electrodes and even column electrodes are scanned by separate drive circuits to supply a video signal to each pixel for display, a clock signal for generating a clock signal having a cycle of 3/2 pixel period Generating means, start pulse generating means for generating a start pulse for starting sampling, and 3 sequentially based on the clock signal and the start pulse.
A display drive device comprising: a sampling pulse generation unit that generates the sampling pulse delayed by a pixel period; and a sampling unit that simultaneously samples three adjacent red, green, and blue pixels by the sampling pulse. 2. A video signal is arranged in a delta pattern for every three pixels of red, green, and blue over a horizontal odd line and a horizontal even line adjacent to a plurality of pixels arranged in a matrix. In a display driving device for supplying and displaying the same, sampling timings of the video signals supplied to the respective pixels are simultaneously sampled in two horizontally adjacent colors,
A display drive device having a sampling means for repeating sampling so as to sample another one color at the next timing. 3. A video signal is arranged in a delta pattern for every three pixels of red, green, and blue over a horizontal odd-numbered line and a horizontal even-numbered line which are adjacent to each other in a plurality of pixels arranged in a matrix. In a display drive device for supplying and displaying a first sampling pulse for sampling a video signal to be applied to one pixel of the horizontal odd line of the display panel, and a pixel of the adjacent horizontal even line of the display panel And a display driving device having sampling means for sampling by shifting the phase of a second sampling pulse for sampling a video signal to be given to the display device.