JP3288326B2 - Vector processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing apparatus, and more particularly to a vector processing apparatus in which each vector pipeline operation unit independently controls instruction issuance.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional vector processing apparatus of this kind, which comprises an instruction control unit 101 for controlling an instruction,
A plurality of vector pipeline operation units 111 to 11n;
The crossbar 20 performs data transfer between the vector pipeline operation units 111 to 11n.

[0003] A vector pipeline operation unit 111 receives instruction of a vector from the instruction control unit 101 and manages resources in the vector pipeline operation unit and issues a vector instruction. Synchronization control means 10 for exchanging a synchronization control signal with another vector pipeline operation unit via signal line 103 in issuing an instruction to synchronize the issuance of vector instructions.
5 is included.

The vector pipeline operation unit 11n
Similarly to the vector pipeline operation unit 110, the configuration includes an instruction execution control unit 104 and a synchronization determination unit 105.

Each of the vector pipeline operation units 111 to 11n to which the vector elements are allocated in an interleaved manner.
Operates independently according to the resource status and processes the given vector instruction. At this time, if the given vector element is processing closed in each vector pipeline operation unit, it is not always necessary to simultaneously issue instructions to the operation circuits 108 in each vector pipeline operation unit. However, when executing an instruction requiring transfer of a vector element or a memory access instruction between vector pipeline operation units, it is necessary to issue an instruction in synchronization with each operation circuit.

In issuing a vector instruction, the number of vector elements (hereinafter, referred to as the number of vector elements) is not always an integral multiple of the number of vector pipeline operation units (hereinafter, referred to as the number of pipelines). For this reason, the calculation of a different number of elements may be performed between the calculation units.

For example, referring to FIG. 5, consider an apparatus in which the number of vector pipeline operation units is two. First, assuming that a vector instruction X having eight vector elements is issued (T = 0), each vector pipeline arithmetic circuit performs an arithmetic operation on four vector elements, and a Does not occur at (T =
4). However, a vector instruction Y having a vector element of 7
Is issued, since the number of pipes is two, the vector pipeline operation unit 111 performs an operation with a vector element of 4 and the vector pipeline operation unit 11n performs an operation with a vector element of 3 (T = 7,8). As described above, in the case where the number of elements to be processed varies among the vector pipeline operation units, if instructions that do not need to be synchronized are continuously issued, a large difference occurs in instruction issuance timing.

Therefore, in the conventional vector processing apparatus, when processing a vector instruction requiring synchronization, the next instruction is issued to the arithmetic circuit while synchronizing between the vector pipeline arithmetic units. Therefore, in order to perform the synchronization control, the instruction execution control means 104 must determine whether or not the given vector instruction is an instruction requiring synchronization, and notify the synchronization determination means 105 of the vector pipeline operation unit, respectively. did not become. Further, the synchronization determination means 105 transmits the synchronization control signal in the vector pipeline operation unit to the signal line 10.
3 and the status of the synchronization control signal from the other vector pipeline operation unit is received, and when it is determined that the vector instruction can be issued, the instruction execution control means 104 had to be notified.

In FIG. 6, the number of pipelines is 2, the number of vector elements in a vector instruction is 7, and an instruction A
This is an operation example in which an instruction sequence is processed in the order of → instruction B → instruction C (synchronous instruction) → instruction D (synchronous instruction).

It is assumed that the instructions A and B are operation instructions closed in the vector pipeline operation unit and need not be synchronized.

In processing the instruction A, the instruction execution control means 104 of the vector pipeline arithmetic unit 111 indicates the number of vector pipeline arithmetic units, the number of vector elements, and the number of the vector pipeline arithmetic unit. The number of processing elements “4” is calculated from the pipeline number (in this case, the vector pipeline operation unit 111 is the first and the vector pipeline operation unit 112 is the second). This is the number of operation processing elements in the vector pipeline operation unit. Based on this, resource management, instruction issuance, and operation are performed in the instruction execution control unit 104 (time T = 0 in FIG. 6). Similarly, the instruction execution control unit 104 of the pipeline arithmetic unit 112 also calculates the number of processing elements “3” from the number of vector pipeline arithmetic units, the number of vector elements, and the pipeline number (= 2) of the vector pipeline arithmetic unit. Calculate and use this for instruction issue control and arithmetic. The operation for instruction B is the same. However, the vector pipeline operation unit 111
Comparing the issuance timing of the instruction B with the vector pipeline operation unit 112, the respective vector pipeline operation units independently control the instruction issuance, so that the instruction issuance timing is shifted due to the difference in the number of elements. (T = 3,4). Assume that instructions C and D are instructions that process vector elements across vector pipes. In this case, since the vector elements in the vector pipeline operation units 111 and 112 need to be transferred to another vector pipeline operation unit via the crossbar 102 for processing, the vector pipeline operation unit 112 It is necessary to synchronize sending and receiving.

Therefore, the instruction execution control means 104 notifies the synchronization determination means 105 that the synchronous instruction is issued prior to the execution of the instructions C and D, and instructs the synchronization determination means 105 of the other vector pipeline operation unit 110 to execute the instruction. (T = 6, 12). Instruction execution control means 1
Similarly, when the instruction being executed ends, the synchronization determination unit 105 is notified that the instruction is being executed, and the synchronization determination unit 105 of the other vector pipeline operation unit 11n is notified that the instruction can be issued (T = 8, 13). The vector pipeline operation units 111 and 112 issue the next vector instruction when the synchronization control signal is notified from all of the synchronization determination units of each vector pipeline operation unit (T = 9,
104). As described above, an instruction can be issued only when the synchronization control signals of all the vector pipeline operation units 111 and 112 are prepared, and the timing of instruction issuance from the instruction execution control unit 104 is synchronized.

[0013]

In the above-mentioned prior art,
When processing an instruction that requires synchronization, the synchronization control signal is exchanged before the instruction is issued, and then issued.
Preparation time was required for issuing the instruction, and extra processing time was required.

An object of the present invention is to reduce the overhead time required for synchronous processing in a vector processing device in which vector elements are allocated to respective vector pipeline arithmetic units in an interleaved manner, thereby speeding up processing.

[0015]

In order to solve the above-mentioned problems, a vector processing apparatus according to the present invention comprises: an instruction control unit for controlling instructions; In a vector processing device having a plurality of vector pipeline operation units that perform control and a crossbar that performs data transfer between the plurality of vector pipeline operation units, the plurality of vector pipeline operation units are each provided with the plurality of vectors. A control element number determining unit for obtaining a maximum number of operation processing elements among the number of operation processing elements in each of the pipeline operation units as a control element number; and an instruction execution control unit for performing instruction issue control. The execution control means issues the next instruction based on the value of the number of control elements obtained by the control element number determination means. Performs control.

Further, each of the plurality of vector pipeline operation units further includes a memory access instruction synchronization determination unit for performing a synchronization determination for a memory access instruction among the vector pipeline operation units, and the instruction execution control unit includes a memory access instruction unit. For the instruction, the memory access instruction synchronization determining means determines the synchronization with another vector pipeline processing device and controls the issuance of the next instruction.

[0017]

[0018]

Next, an embodiment of a vector processing apparatus according to the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the embodiment of the present invention has an instruction control unit 1, a crossbar 2, and a plurality of vector pipeline operation units 11 to 1n.

The instruction control unit 1 controls all the instructions. For vector instructions, the vector pipeline operation units 11 to
1n, and each vector pipeline operation unit 11-1
Vector elements are allocated to n vector registers.

The crossbar 2 receives data from the vector pipeline operation units 11 to 1n and transfers data between the vector pipeline operation units.

The vector pipeline operation unit 11 receives the vector instruction from the instruction control unit 1, and controls the resource management in the vector pipeline operation unit 11 and the issuance of the vector instruction to the operation circuit. An operation element number determination unit 6 for receiving information from the instruction execution control unit 4 and obtaining the number of vector elements for processing the operation allocated to the vector pipeline operation unit (hereinafter, referred to as the number of operation processing elements); Control element number judging means 7 which receives information from instruction execution control means 4 and obtains the maximum value of the number of operation processing elements in all vector pipeline operation units.
Receiving the information from the instruction execution control means 4 and notifying the synchronization control signal of the memory access instruction to another vector pipeline operation unit and receiving the synchronization control signal from the other vector pipeline operation unit. Determination means 5.

Similarly to the vector pipeline operation unit 11, the vector pipeline operation units 12 to 1n also include an instruction execution control unit 4, an operation element number determination unit 6, a control element number determination unit 7, and a memory access instruction synchronization unit. It includes determination means 5.

The instruction control unit 1 controls a previous instruction given from a higher-level device (not shown) and notifies each of the vector pipeline operation units 11 to 1n. The instruction execution control means 4 of each of the vector pipeline operation units 11 to 1n sequentially issues instructions according to the use status of resources in the vector pipeline operation unit.

In the instruction execution control means 4, the number of vector elements, the number of pipelines, and the pipeline number indicating the number of the vector pipeline operation unit in the operation element number determination means 6 are used to determine the vector pipeline. The number of calculation processing elements of the line calculation unit 11 is obtained, and the calculation circuit 8 is notified to perform calculation using this value. Further, the control element number determination means 7 obtains the maximum number of processing elements in all the vector pipeline operation units from the number of vector elements and the number of pipes. Then, it notifies the instruction execution control means 4 to use this value as the number of control elements. The instruction execution control means 4 performs control using the number of control elements as an instruction issue cycle. Vector pipeline operation unit 12
1n operate similarly to the vector pipeline operation unit 11.

Here, the method of calculating the number of operation processing elements is as follows: When the number of vector elements is x, the number of pipelines is y, and the pipeline number is z, [x / y] +1 (the remainder of x / y ≧ z Case) [x / y] (Remainder of x / y <case of z). Here, [x / y] represents a quotient obtained by dividing x by y.

The number of control elements is obtained as [x / y] +1 (the remainder of x / y is other than 0) and [x / y] (when the remainder of x / y is 0). As described above, the timing at which each of the vector pipeline operation units 11 to 1n issues an instruction to the operation circuit is performed based on the number of control elements. Other than that, all vector pipeline operation unit 1
1 to 1n can issue instructions at the same timing without requiring the operation of synchronous control.

For a memory access instruction, the memory control unit 9 notifies the memory access instruction synchronization determination unit 5 of the end timing of the processing, and the information is synchronously controlled by another vector pipeline operation unit and the instruction execution control unit 4. Notify as a signal. At the same time, it receives a synchronization control signal from another vector pipeline operation unit via the signal line 3. Upon receiving all the synchronization control signals from the other vector pipeline operation units, the memory access instruction synchronization determination unit 5 notifies the instruction execution control unit 4 of the information. The other vector pipeline operation units 11 to 1n operate in the same manner, whereby it is possible to know the memory access instruction end timing of the other vector pipeline operation units, and to synchronize the subsequent vector instruction issue timings. It becomes possible.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 2, instruction control unit 1 converts a given instruction into each of vector pipeline operation units 11 to 1n.
(S1 in FIG. 2). The instruction execution control means 4 of each of the vector pipeline operation units 11 to 1n determines whether the assigned instruction is a memory access instruction (S2). If the instruction is not a memory access instruction, the number of processing elements of the vector element in the vector pipeline operation unit is obtained from the number of vector pipeline operation units, the number of vector elements and the pipeline number of the vector pipeline operation unit by the operation element number determination unit 6. (S3). Further, the number of control elements is determined from the number of vector pipeline operation units and the number of vector elements by the control element number determination means (S3). The instruction execution control means 4 controls the execution of the arithmetic circuit by the number of processing elements of each, and monitors whether or not the time of the number of control elements has elapsed (S4). Upon detecting that the time equal to the number of control elements has elapsed, the instruction execution control means 4 issues the next instruction (S5). On the other hand, if it is determined in S2 that the assigned instruction is a memory access instruction, the instruction execution control means 4 executes a memory access, and the memory access instruction synchronization determination means 5 notifies the memory control unit 9 of the end timing. Wait (S6). Upon receiving the notification of the end timing from the memory control unit 9, the memory access instruction synchronization determining unit 5 notifies the memory access instruction synchronization determining unit 5 of the other vector pipeline operation unit of a synchronization control signal via the signal line 3 ( S7). The memory access instruction synchronization determining means 5 determines whether or not a synchronization control signal has been received from all the memory access instruction synchronization determining means 5 of the other vector pipeline operation units (S8). It notifies the instruction execution control means 4 (S9). When receiving the notification of the completion of the synchronous control processing, the instruction execution control means 4 issues the next instruction (to S5).

Next, an example of the operation of the present invention will be described in detail with reference to the drawings.

FIG. 3 shows an example in which the vector pipeline operation unit is "2" and the number of vector elements is "7". Instruction A → Instruction B → Instruction C (Memory Access Instruction) → Instruction D → Instruction E This is an operation example when the instruction sequence is processed. Here, instructions A and B are instructions that do not require synchronization, instruction C is a memory access instruction, and instructions D and E are instructions that require synchronization.

First, when the instruction A is issued to the arithmetic circuit, in the vector pipeline arithmetic unit 11, the number of arithmetic elements and the number of vector elements and the pipeline number (in this case, the vector pipe) The line operation unit 11 is the first, the vector pipeline operation unit 1
The number of processing elements “4” is calculated from “2” as 2), and the number of control elements “4” is calculated from the number of pipes and the vector element by the control element number determination means 7. The instruction execution control means 4 uses the vector pipeline operation unit 1
1 for resource management and instruction issuance. Similarly, in the vector pipeline operation unit 12, the number of processing elements "3" is calculated by the operation element number determination means 7, and the control element number determination means 6 calculates the number of control elements "
4 ″. Then, the instruction execution control means 4 of the vector pipeline operation unit 12 performs resource management and instruction issuance of the vector pipeline operation unit 12 based on these.

Thus, in the vector pipeline operation unit 11 having the number of processing elements “4”, the cycle time is “4”.
The progress, that is, the processing of the preceding vector instruction ends, and the next vector instruction is issued to the arithmetic circuit. On the other hand, in the vector pipeline operation unit 12 having the number of processing elements “3”, when the cycle time has elapsed “4”, that is, when the cycle time has elapsed “1” after the end of the previous processing, the next vector instruction is issued. .

Therefore, the vector pipeline operation unit 11
When the instruction A is issued at time T = 0, the number of processing elements and the number of control elements are both "4", so that at the timing of T = 4, 8 B and instruction C are issued. On the other hand, in the vector pipeline operation unit 12 in which the number of processing elements is “3” and the number of control elements is “4”, the instruction A ends at T = 3, but since the number of control elements is “4”, 1 After waiting for the clock, the instruction B is issued at the timing of T = 4. Instruction C
Is also issued after waiting one clock after the end of instruction B.

Since instruction C is a memory access instruction,
The timing at which the vector load data arrives at the vector pipeline operation units 11 and 12 may vary depending on the state of the memory. It is not easy to predict the timing of this variation and issue an instruction. Therefore,
The memory control unit 9 notifies each vector pipeline operation unit of the timing at which the memory access ends, and based on this information, the memory access instruction synchronization determination unit 5 sends the vector pipeline operation unit 11, 12 exchanges synchronization control information. Thereby, the end of the memory access instruction can be synchronized between the vector pipeline operation units 11 and 12, and the timing of issuing the next instruction can be adjusted. FIG. 3 shows that a shift occurs between the pipeline operation units to process the memory access instruction C, and 2T is required for the synchronization control. As described above, if the immediately preceding instruction is a memory access instruction, the issuance of the subsequent vector instruction D requires the exchange of synchronization control signals between the operation units. It is no longer necessary to perform synchronous control on the data, so that the processing can be sped up.

As described above, according to the embodiment of the present invention, in controlling the execution of the vector instruction, the next instruction is executed without performing the synchronization control processing between the vector pipeline operation units by the synchronization determining means. This makes it possible to issue the instructions sequentially in synchronization with each other, thereby reducing the extra overhead for performing the synchronization control and speeding up the execution of the vector instruction.

[0038]

As is apparent from the above description, according to the present invention, by adopting a control configuration in which the instruction issue timing of all vector pipeline operation units is predicted, it is possible to issue instructions in a conventional synchronous manner. It is possible to reduce the overhead required for the synchronous processing and to increase the processing speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation example of the exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional device.

FIG. 5 is a timing chart illustrating an operation example of a conventional device.

FIG. 6 is a timing chart illustrating an operation example of a conventional device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 101 Instruction control part 2, 102 Crossbar 3, 103 Signal line 11-1n, 111-11n Vector pipeline operation part 4, Instruction execution control means 5 Memory access instruction synchronization judgment means 6 Operation element number judgment means 7 Number of control elements Determination means 8, 108 Arithmetic circuit 104 Instruction execution control means 105 Synchronization determination means

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-289224 (JP, A) JP-A-9-198374 (JP, A) JP-A-6-28388 (JP, A) JP-A-5-1983 35474 (JP, A) JP-A-4-360241 (JP, A) JP-A-4-30253 (JP, A) JP-A-3-241452 (JP, A) JP-A-2-127768 (JP, A) JP-A-1-284967 (JP, A) JP-A-1-261780 (JP, A) JP-A-63-155352 (JP, A) JP-A-62-187971 (JP, A) JP-A-61-95477 (JP, A) JP-A-60-215280 (JP, A) JP-A-60-77265 (JP, A) JP-A-57-113175 (JP, A) JP-A-57-64863 (JP, A) Japanese Patent Laid-Open No. 57-39474 (JP, A) JP-A-51-10746 (JP, A) Hiroyuki Izumisawa, two others, multiple parallel pipeline system That vector computer, the 30th (Showa 60 years the previous fiscal year) National Conference Papers (1), Japan, Japan Information Processing Society of Japan, March 13, 1985, p. 101-102 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/16 G06F 15/16-15/177 G06F 9/38

Claims (2)

(57) [Claims] An instruction control unit for controlling instructions; a plurality of vector pipeline arithmetic units for interleaving and assigning vector data and independently controlling instruction issuance according to resource status; and the plurality of vector pipeline arithmetic units. A vector processing device having a crossbar for transferring data between units, wherein each of the plurality of vector pipeline arithmetic units has a maximum number of arithmetic processing elements among the number of arithmetic processing elements in each of the plurality of vector pipeline arithmetic units. A control element number determining unit that determines the number of elements as a control element number; and an instruction execution control unit that performs instruction issue control, wherein the instruction execution control unit determines the number of control elements determined by the control element number determining unit. A vector processing device for controlling issuance of a next instruction according to a value. 2. The method according to claim 1, wherein each of the plurality of vector pipeline operation units further includes a memory access instruction synchronization determination unit that performs a synchronization determination on a memory access instruction among the vector pipeline operation units. 2. The vector processing device according to claim 1, wherein for the instruction, the memory access instruction synchronization determination unit determines synchronization with another vector pipeline processing device and controls the issuance of the next instruction.