JP2001184340A - Information processor and method for synchronizing plural vector processors - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor, with which the number of vector pipelines is increased and vector instruction processing time can be shortened, concerning the information processor provided with plural vector processors. SOLUTION: This device is provided with a synchronizing means for executing instructions, which are fetched during the time when a synchronizing instruction command is fetched until a synchronism cancel command is fetched, synchronously among plural vector processors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus having a plurality of vector processors.

[0002]

2. Description of the Related Art A conventional vector processing device is configured by connecting a plurality of vector processors to a main storage device. Each of the plurality of vector processors includes: 1. A plurality of vector pipelines including a plurality of vector registers and a plurality of pipeline arithmetic units for processing vector data stored in the plurality of vector registers. A vector control unit is provided for inputting, decoding, and decoding instructions to be executed by the plurality of vector pipelines, generating control signals inside the processor, and controlling the plurality of vector pipelines.

[0003] This type of vector processing mechanism is called a multiplex parallel pipeline in the sense that each vector processor has a plurality of vector pipelines and operates in parallel. , Vector instructions are loaded so that a series of vector data to be processed are equally distributed to the vector registers of the plurality of vector pipelines, and are processed by the plurality of pipeline arithmetic units.

[0004]

In the above-described vector processing apparatus, since each processor can operate only with the number of vector pipelines configured therein, it is possible to shorten the arithmetic processing time by using the parallel effect. I could not do it. When multiple processors operate synchronously,
Since synchronous issuance processing was performed for all instructions, useless processing time was required until instruction execution.

An object of the present invention is to provide an information processing apparatus having a plurality of vector processors, which can increase the number of vector pipelines and shorten the vector instruction processing time.

[0006]

An information processing apparatus according to the present invention synchronously executes instructions fetched between a time when a synchronization instruction instruction is fetched and a time when a synchronization release instruction is fetched, between a plurality of vector processors. It is characterized by comprising a synchronizing means.

Further, in the information processing apparatus according to the present invention, in the information processing apparatus described above, the synchronization instruction instruction has an operand for designating a vector processor to be synchronized, and the synchronization means performs synchronization when the synchronization is performed. , And is synchronized between the vector processors specified by the operands.

Furthermore, in the information processing apparatus according to the present invention, in the above information processing apparatus, each vector processor includes an instruction control unit, a memory access unit, a vector control unit, a vector processing unit, a processor network unit, and a pipeline crossbar unit. It is characterized by having.

Further, the information processing apparatus according to the present invention is characterized in that, in the above information processing apparatus, the instruction processing section includes a scalar processing section and an instruction decoding section.

Further, in the information processing apparatus according to the present invention, in the above information processing apparatus, the vector control section includes an instruction decoding section, a synchronous instruction designating section, a configuration flag, an element determining circuit, an instruction issuing section, and a synchronous instruction detecting circuit. , A synchronization flag, an instruction issue check unit, an instruction issue OK flag, an external device synchronization flag, an external issue OK flag, an instruction execution unit, and a signal line.

Further, in the information processing apparatus according to the present invention, in the above information processing apparatus, the vector processing section includes a plurality of vector pipelines including a plurality of registers, a plurality of arithmetic units, and a crossbar in a pipe. Features.

According to the method for synchronizing between a plurality of vector processors according to the present invention, an instruction fetched between the time when a synchronization instruction instruction is fetched and the time when a synchronization release instruction is fetched is executed in synchronization between the plurality of vector processors. It is characterized by the following.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to the present invention is a processing apparatus for processing vector data with a plurality of vector processors, wherein the plurality of processors synchronize to operate in parallel to reduce vector processing time. It is.

Referring to FIG. 1, an information processing apparatus 1 includes a main storage device 8 and a plurality of vector processors 1 and 1n for executing data processing. Each vector processor executes an instruction read from the main storage device 8. An instruction control unit 2 for decoding and outputting a scalar instruction and a vector instruction, and a main storage device 8
A memory access processing unit 3 for controlling access to a vector, a vector control unit 5 for issuing and controlling a vector instruction, a vector processing unit 6 for holding a plurality of pipeline arithmetic units for processing vector data, a vector processing device and It comprises a processor network unit 4 for exchanging vector data between storage devices, and a pipeline crossbar unit 7 for exchanging vector data between a plurality of vector pipeline computing units. Although not shown, it is assumed that the main storage device 8 and the plurality of vector processing devices 1 and 1n are connected by a crossbar. In the above information processing apparatus, there are provided a case where the plurality of processors are independently processed by individual instructions, and a unit which enables operations from instruction issue to data processing to be performed in parallel in one instruction in synchronization. Means for switching between a case where a plurality of processors operate in synchronization with the same instruction and a case where they independently operate one vector data without synchronization in accordance with an instruction.

An interface 100 between the main storage device 8 and the instruction control unit 2 is a signal line of an instruction read from the main storage device.

The instruction control unit 2 includes a scalar processing unit 20 composed of a scalar register for storing scalar data necessary for scalar processing and an arithmetic unit for address calculation, index calculation, and control variable calculation. An instruction decoding unit 21 that determines whether an input instruction is an instruction processed by the scalar processing unit 20 or an instruction processed by the vector processing unit 6 and transfers the instruction to each processing unit. The memory access instruction is output to the vector control unit 5 via the signal line 101 and the memory access processing unit 3 via the signal line 102.

The memory access processing unit 3 includes a signal line 102
, A control signal is sent to the processor network unit 4 via a signal line 103 which decodes the request code sent from the instruction control unit 2 and manages the state of the processor network unit 4 and controls a memory access request. Of data between the signal line 104 of FIG. 4 and the signal line 105 of the vector processing unit 6 is controlled.

The vector control unit 5 includes an instruction decoding unit 51 that decodes a vector instruction input from the instruction control unit 2 via the signal line 101, a synchronization instruction instruction unit 50 that stores and holds a plurality of synchronization instruction instructions, A configuration flag 5 that indicates a processor and that stores and holds a plurality of synchronous instruction instructing units 50 used to calculate the number of vector pipeline arithmetic units
7, an element determination circuit 58 for obtaining the number of processing vector elements evenly allocated to the vector pipeline computing unit from the number of vector elements and the configuration flag 57, and an instruction issuing unit 54 for receiving an instruction decoded by the instruction decoding unit. It is necessary to synchronize with the synchronous instruction detecting circuit 5A in which the instruction decoded by the instruction decoding unit 51 matches the instruction registered in the synchronous instruction instructing unit 50 and the detection result of the synchronous instruction detecting circuit 5A. Synchronization flag 52 indicating instruction
And an instruction issuance checking unit 55 for checking each resource to determine whether the instruction stored in the instruction issuing unit 54 can be issued.
An instruction issue OK flag 56 for storing the result of the instruction issue check unit, a signal line 200 for notifying the instruction issue OK flag to another processing device, a synchronization flag 53 for storing the synchronization flag 52, , An external device synchronization flag 580 notified from another processing device via the signal line 203, and an externally issued OK flag 5B also notified from another processing device via the signal line 204. An instruction execution unit 59 for checking the states of the synchronization flags 53 and 58 and the instruction issue flags 56 and 5B and permitting the execution of the instruction; a signal line 106 for notifying the vector processing unit 6 of the execution permission; Is notified to the pipeline crossbar unit 7 by the signal line 107.

The vector processing section 6 is composed of a plurality of vector pipelines 60 and 6m, each of which stores a plurality of vector registers 61 for storing vector data, a plurality of arithmetic units 62, and transfer of data in the vector pipeline. The instruction is executed in accordance with an instruction input through a signal line 106 from the vector control unit 5 which is constituted by an in-pipe crossbar 63 for performing

The pipeline crossbar 7 inputs the vector data from the plurality of vector pipelines 60 and 6m from the vector processing unit 6 via the signal line 108, and if the instruction from the vector control unit 5 is a process in the processing device. The vector data is returned to the vector pipeline instructed via the signal line 108. If the instruction from the vector control unit 5 is between the processing devices, the vector data is output to another processing device via the signal line 205. Further, after inputting vector data from another processing device via the signal line 206 and processing according to the instruction, the data is returned to the vector pipeline of the vector processing unit 6 via the signal line 108. The vector processing device 1n has exactly the same configuration as the vector processing device 1, and the numbers used in all the description are given n and described later.

Next, the operation of the circuit of FIG. 1 will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, an instruction is notified from the main storage device 8 to the vector processing devices 1 and 1n to the instruction control unit 2 via signal lines 100 and 100n. In order to enhance the parallel effect, the vector processing apparatuses 1 and 1n are notified of the instruction that must be operated synchronously and the processor number by the synchronization instruction instruction shown in FIG. . Further, the synchronization instruction instruction and the processor number and the instruction stored in the synchronization instruction instructing section 50 and the configuration flag 57 which must be operated synchronously can be released. The operations 1 to 6 will be described with reference to the following instruction sequence. 1. 1. VLD (V0) main memory → vector register 0 2. VLD (V1) main memory → vector register 1 VADD (V0 + V1 → V2) Vector register 0 + vector register 1 → vector register 2
Number 4. 4. Synchronization instruction instruction VST instruction instruction VST (V2 → MM) Vector register No.2 →
Store in main memory 6. Synchronization release instruction Release VST instruction The first VLD (V0) instruction is notified from the main storage device 8 to the vector processing devices 1 and 1n to the instruction control unit 2 via the signal lines 100 and 100n. The notified instruction is decoded by the instruction decoding unit 21 of the instruction control unit 2 as a scalar processing instruction or a vector processing instruction.
The instruction is sent to the vector control unit 5 via 101n and decoded by the instruction decoding unit 51. The number of vector pipelines and the number of vector elements are respectively obtained from the configuration flag 57 and the instruction decoding unit 51, and the element determination circuit 58 obtains an equal number of vector elements to be processed by the vector pipeline arithmetic unit. A signal line 10 which is notified to the memory access processing units 3 and 3n through signal lines 102 and 102n to decode the request code, manages the states of the processor network units 4 and 4n, and controls the memory access request.
3, 103n, processor network unit 4, 4n
Control signal to the main memory 8 and the signal lines 104 and 104
Send a VLD request via n. VLD (V0)
Is determined as an instruction that does not need to be synchronously issued by the instruction decoding unit 51, is stored in the instruction issuing unit 54, the resource is checked by the instruction issuing check unit 55, and the instruction issuing flag 56
Since the synchronization flag 53 is not lit, there is no need to issue the instruction synchronously, and the instruction is issued from the signal line 106 to the vector processing unit 6 via the instruction execution unit 59. The same is performed in the other vector processing device 6n. On the other hand, the vector data read by the request output to the main storage device is input to the processor network unit 4 through 104 and 104n, and is input to the vector pipeline 60, 6m, 60n, and 6m configured through the signal lines 105 and 105n.
n, interleaved and input to the crossbar 6 in the pipe.
3 and stored in the vector register 61 designated by the instruction.

The second VLD (V1) instruction operates in the same manner as the preceding instruction VLD (V0), and will not be described.

Third VADD (V0 + V1 → V2)
Does not notify the instructions to the memory access processing units 3 and 3n, but transmits the signal to the vector control unit 5 via the signal lines 101 and 101n.
Will be notified only. VA notified to the vector control unit 5
The DD instruction is determined to be an instruction that does not need to be synchronously issued by the instruction decode unit 51, and is stored in the instruction issue unit 54 at the same time as checking the resources by the instruction issue check unit 55, setting the instruction issue flag 56, and Since 53 is not lit, it is not necessary to issue the instruction synchronously, and the instruction is issued from the signal line 106 to the vector processing unit 6 via the instruction executing unit 59. The vector processing unit 6 that has received the instruction executes the vector registers 61 (V0, V1) and 61m (V
0, V1), the vector data is read out from the vector register 61 (V2), 61m (V2) which is input to the crossbar 63 in the pipe and processed by the operation unit 62.
Is stored in The vector processing unit 6n operates in the same manner as the vector processing unit 6, but the collection of vector data loaded into the vector processing device due to the busy network between the vector processing device and the main storage device (not shown) causes a delay synchronization instruction. Unsuccessful subsequent instructions operate independently since they are executed only by checking resources in the vector processing device.

Fourth synchronization instruction instruction (VST instruction instruction)
Thus, the VST instruction is stored and held in the synchronization instruction instructing section 50, and the synchronization instruction processor number is stored and held in the configuration flag 57. Note that the operand of the synchronization instruction instruction includes a synchronization designation processor number, which specifies a plurality of vector processors to be synchronized. When the number of processors in the system is a constant, each processor is assigned to each bit of the operand, and whether each processor is to be synchronized is set depending on whether each bit is 1 or 0. Such an operand configuration may be used. If the number of processors in the system is uncertain, the operand configuration may be such that each processor is assigned to each bit of the operand and the number of processors to be synchronized is inserted at the front of the operand.

The fifth VST instruction is notified to the memory access processing units 3 and 3n through the signal lines 102 and 102n, and is also notified to the vector control unit 5 through the signal lines 101 and 101n. The VST instruction notified to the vector control unit 5 is synchronized with the instruction decoded by the instruction decoding unit 51 and synchronized with the instruction held in the synchronous instruction designating unit 50 by the synchronous instruction detection circuit 5A when the instruction is determined to be synchronous. The flags 52 and 53 are set, and the instruction issuing unit 54 is notified from the signal line 201 to the other vector processing device 1n that the synchronous instruction has been set. The VST instruction set in the instruction issuing unit 54 checks the resources in the instruction issuing check unit 55, and if the instruction can be issued, sets the instruction issuing OK flag 56 and performs other vector processing from the signal line 200 in the same manner as the synchronization flag. Notify the device 1n. The other vector processing device 1n has the same VS as the vector processing device 1.
When it is determined that the T instruction is an instruction issued synchronously by the synchronous instruction detection circuit 5An, the synchronous flags 52n and 53n are set, and the synchronous instruction is set to the instruction issuing unit 54n from the signal line 201n to the other vector processing device 1. Notify the thing. The vector processing device 1 receives the synchronization flag 53n of the vector processing device 1n via the signal line 203, sets the external synchronization flag 580, and the VST instruction set in the instruction issuing unit 54n of the vector processing device 1n is a synchronization instruction. Recognize things. Instruction issuing unit 54 of the vector processing device 1n
The VST instruction set in the instruction issuance check unit 5
5n, the resource is checked, and if it can be issued, the instruction issue OK flag 56n is set and at the same time the signal line 20 is set.
0n to the vector processing device 1 and the signal line 204
, The external issue OK flag 5B is set. The instruction execution unit 59 recognizes from the synchronization flag 53 and the external synchronization flag 58 that the instruction to be issued by the vector processing device 1 or 1n is a synchronous instruction, and sets the instruction issue OK flag 56 and the external issue OK flag 5B at the same time. Then, the instruction execution instruction is notified to the vector processing unit 6. The vector processing units 6 and 6n receive the instruction execution instruction at the same time,
Vector registers 61, 61m, 61n, 61mn (V
2) The vector data is read out from each of the signal lines 10
5, 105n, processor network section 4, 4n
At the same time, and stored in the main storage device 8 via the signal lines 104 and 104n.

The transmission and reception of the above-mentioned flag for synchronizing is limited between processors to be synchronized specified by the operand of the synchronizing instruction.

6. The synchronization release instruction (VST instruction release)
4. Synchronization instruction instruction 5
0, the data stored and held in the configuration flag 57 is released.

[0028]

The effect of the present invention is that the number of vector pipelines can be increased and the vector instruction processing time can be shortened by setting instructions which must be synchronized between the processors and controlling the synchronous issue between the processors.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a synchronization instruction command according to the embodiment of the present invention.

[Explanation of symbols]

 1, 1n vector processor 2 instruction control unit 3 memory access processing unit 4 processor network unit 5 vector control unit 5A synchronous instruction detection circuit 5B externally issued OK flag 6 vector processing unit 7 pipeline crossbar unit 7 20 scalar processing unit 21 instruction decoding unit REFERENCE SIGNS LIST 50 synchronization instruction instructing unit 51 instruction decoding unit 52 synchronization flag 53 synchronization flag 54 instruction issuing unit 55 instruction issuing check unit 56 instruction issuing OK flag 57 configuration flag 58 element determination circuit 580 external device synchronization flag 59 instruction execution unit 61 vector register 62 operation Instrument 63 Crossbar in pipe 106 Signal line 107 Signal line 200 Signal line 201 Signal line 8 Main storage device

Claims (7)

[Claims] 1. An information processing apparatus, comprising: a synchronizing means for executing a fetched instruction in synchronization between a plurality of vector processors between a time when a synchronization instruction instruction is fetched and a time when a synchronization release instruction is fetched. Processing equipment. 2. The information processing apparatus according to claim 1, wherein the synchronization instruction instruction has an operand for designating a vector processor to be synchronized, and the synchronization means uses the operand when synchronizing. An information processing apparatus for synchronizing between designated vector processors. 3. The information processing device according to claim 1, wherein each vector processor includes an instruction control unit, a memory access unit, a vector control unit, a vector processing unit, a processor network unit, and a pipeline crossbar unit. An information processing apparatus characterized by the above-mentioned. 4. The information processing apparatus according to claim 3, wherein the command processing unit includes a scalar processing unit and a command decoding unit. 5. The information processing apparatus according to claim 3, wherein the vector control unit includes an instruction decoding unit, a synchronous instruction designating unit, a configuration flag, an element determining circuit, an instruction issuing unit, a synchronous instruction detecting circuit, a synchronous flag, An information processing apparatus comprising: an instruction issue check unit; an instruction issue OK flag; an external device synchronization flag; an external issue OK flag; an instruction execution unit; and a signal line. 6. The information processing apparatus according to claim 3, wherein the vector processing unit includes a plurality of vector pipelines including a plurality of registers, a plurality of arithmetic units, and a crossbar in a pipe. Processing equipment. 7. A method for synchronizing between a plurality of vector processors, wherein the fetched instruction is executed between the plurality of vector processors in a period from fetching a synchronization instruction instruction to fetching a synchronization release instruction.