SU1559340A1 - Arithmetic device with microprogram control - Google Patents

Abstract

The invention relates to computing and can be used in the design of arithmetic devices of computers. The purpose of the invention is to increase the speed of the multiplication operation while reducing the equipment. The device contains an arithmetic unit made of N computational cells and an accelerated transfer node, a bus interface driver, a state controller, a memory address register, two operand selection nodes, each of which contains a connected address multiplexer and a buffer register, and a firmware control block command register, command decoder, interrupt decoder, firmware control node, microinstructions memory node, first microcommand register and interrupt handling unit, as well as the source DC, data bus, address bus, the input clock signal and straight communication between said blocks according to the drawings. New is the introduction of the address generation register, the second microinstruction register, the bit control signal decoder, the first address operand node has an address decoder connected between the address multiplexer output and the second input address register register, and also the "Setup" and clock inverse inputs are entered and the relationship between the inserted and known device blocks according to the drawings. 7 il. 2 tab.

Description

The invention relates to the field of computing and can be used in the design of arithmetic devices of computers.

The aim of the invention is to increase the speed of the multiplication operation while reducing the equipment.

On league. 1 and 2 presents an arithmetic unit with firmware; in fig. 3 is a diagram of the first operand selection node; in fig. 4 - microcommand format; on

FIG. 5 is a block diagram of the organization of the microcommand control; 6 is a time chart of the organization of the firmware control; in fig. 7 multiplication algorithm.

The device contains an arithmetic logic unit 1 that performs arithmetic and logical operations on operands, a microprogram control unit 2 that controls the operation of unit 1.

Block 1 contains arithmetic logic unit 3 (ALU), consisting of computational cells 4-1 (large J integrated circuits, for example, BIS 1804 BC1), node 8 of accelerated transfer (BIS 180 BP1), controller 9 states, bus driver 10, the memory address register 11, the first node 12 of the choice of 2 operands, the second node 13 of the choice of operands.

The microprogram control unit 2 contains a register of 14 commands, a decoder 15 interrupts (BIS 550PT7 2 (2Kx8), a decoder of 16 commands, a microprogram control unit 17 (BIS 1804VU4), an address generation register 18, a microcommand memory node 19 (four eight-bit BIS3 556РТ16 sections (8 "x8), first register 20 microinstructions, second register 21 microinstructions, interrupt handling unit 22 (BIS 585IK14), decoder 23 bit control signals, data bus 24, 3 bus 25 addresses, DC source 26, clock input 27 right

signals, input 28 clock inverse signals, input 29 Installation.

The circuit node selection operands (figure 3) 4 contains the multiplexer 30 address 30, the decoder address 31 and the buffer register 32.

The reception of information in registers 20 and 21 is carried out synchronously to the cycles (T) and (T).

In order to synchronize the time processes, the microcommand address information on register 32 must be synchronous with the operation of node 3- With this purpose, when the address is received, the third input of register 32 is gated with clock T, gating and the operation of node 3. The decoder 31 is a zero-bit address of the node 22 emulates a zero-range of 5 d address d, depending on the input signals C1, C2, Sz by the formula

d (C1 n-C2) NW,

four

where C1, C2, NW are the inputs of the decoder 31} d is the output of the decoder 31 In the table. 1 represents the truth

states of input and output signals

decoder 31.

Table 1

C1

C2

NW

X matches any value (O or 1) „

In each microcommand Multiplication (Fig. 7), under the control of the low-order value of the shift register O containing the multiplier value, the odd (initial) value of the address of the general purpose register is even in accordance with Table 2. 2

table 2

Emulated odd value of general register address

About 1

Even (14) Odd (15)

0

0

Note. For the non-enumerated address, 15 is selected for the even -14.

The word microcommands is contained in registers 20 and 21 (0-31 and 32-63 bits of microcommands, respectively) ..

Register bits are combined into 5 control fields of the device (a total of 9 fields).

The number of microcommand fields (0-63) corresponds to the size of the outputs of the blocks of registers 20 and 21.

Register control floor 20 (0-31 micro-command bits):

the first control field (bit depth - control functions of node 3

the second control field (20-22 bits) - control of loading the initial addresses of the instruction microprograms (decoder 16), interrupt handling microprogram vectors (decoder 15)

155

return addresses of microinstructions (register 20);

the third control field (12-15 bits) is the control of data reception of the data generator 10 data from the bus 24 data,

the fourth control field (16-19 bits) - management of the functions of forming the address of the microcommand node $ 17

the fifth control field participates in the formation of a microcommand of 3 parallel formats:

first format (0-N bit) Hell

res

|| forming an address constant

node 17;

second format (0-8 bits) Constant — formation of a constant, as an operand of ALU 3;

third format (0 bits) Shift - shaping the functions of controller shift 9.

The use of the multi-format microcommand (the use of individual bits and word fields of the microcommand to form the control functions of various devices) reduces the required word length of the microcommand. For example, in the block 2 structure under consideration, the word length is required.

25 odd and then even resu. The read information from 19 is written to the first groups of registers 20 and 21 at the time of its front of the signals T and T, after

microinstructions are reduced by 15 register-breaking registers to the first inputs.

In the block diagram of the organization of the firmware control (Fig. 5}, the interrelations of the main information flows of blocks t and 2 between nodes 17-21, 12, 13, 3 and 9 are shown.

From the output of node 17 to the 12-bit bus, the address of the microcommand goes to the first group of inputs of the register 18. Code

Microcommand addresses are fixed by the front edge of the gate T according to the synchronization register 18.

The time strobe T is a signal with a period of 0.5 µs, a duty cycle of 2. Time, a signal T is an inverse signal T. From the register 18 output, the twelve most significant bits of the address from the microcommand are fed to the input of node 19 There is also a signal T connected,

In this case, the zero (low) address resolution.

Therefore, during the period of passing the signal T, the information on the 32-bit bus will be twice selected from node 19

5 at an odd, and then at an even address. The read information from node 19 is written to the first groups of inputs of registers 20 and 21 at the time of the leading edge of the signals T and T arriving at the first inputs of the registers.

Dov.

Control register floor 21 microcommands:

the first control field — the control of the operands of ports A and B of node 3 (48 to 59 bits) is divided into the control of node 12 (bits) and the control of node 13 (bits);

35

The control signals for the operation of the node 3 from the first group of outputs of the register 20 are fed to the inputs of sections k - 7, node 3 "

Information from the first group of outputs of the register 21 about the choice of sources of operands shifted forward half a step relative to the operation cycle of the node 3 enters the inputs of the nodes 12 and 13 and

50-53 and 56-59 bits of the first field 4d are synchronized by the T gate. They participate in choosing the register number Che-C by selected nodes 12 and 13 by cutting ports A and B of node 3 and 48, 9 and 5,

Arithmetic or logical operations in ALU 3 are performed by the corresponding inputs of the C - 7 cells with an operand.

55 bits in the choice of the source of the operand in ALU 3;

the second control field is the decoder 23 (60-63 bits) control, which is used to form sixteen bits of the micro-command control features;

the third control field is the control of the recording of the signs of the state and the formation of the flag of the controller 9 (32 kk bits);

the fourth control field is the generation of interface features that serve as signals for maintaining the interface information and controlling the operation of the generator 10 and register 11 (k $ - kj bit).

The control signals for the operation of the node 3 from the first group of outputs of the register 20 are fed to the inputs of sections k - 7, node 3 "

Information from the first group of outputs of the register 21 about the choice of sources of operands shifted forward half a step relative to the operation cycle of the node 3 enters the inputs of the nodes 12 and 13 and

synchronized with strobe T. With selected nodes 12 and 13 through co45

0

five

Arithmetic or logical operations in ALU 3 are performed by the corresponding inputs of the C - 7 cells with an operand.

The result of the operations is a selection of status indications from the outputs of the kt cell arriving at the corresponding inputs of the controller 9 for storage and modification.

The result after processing the state signals on a 13-bit bus arriving at the input of the controller 9 is to generate a signal F arriving at node 17.

When generating the signal F from the output of the controller 9, the information on the 12-bit bus from the outputs of the register 20 passes through the inputs of the node 17 as information of the next address MK.

715

In the absence of a signal F from the controller, the 12-bit address from node 17 is formed depending on the code combination on the 4-bit width of the inputs of node 17.

Consider the essence of the interaction of blocks 1 and 2 together

The start of operation is initiated by the Setup signal arriving at the second input of register 20, at which the Microcommand address from the fifth output of register 20 is recorded synchronously with the T signal in two cycles through node 17 to register 18. This is the initial state for start the device.

The microinstruction address at the input of the node 19 is sequentially formed over a period, the signal T is formed twice: in the half period odd and half period even, differing among themselves by a unit of the least significant bit.

Then in register 20 (cyclograms and 4) there is information that controls the operation of the A-th micro-command, and in register 21 during the first half-period there is information for the A-micro command, and during the second information, selected by an odd 25 period, for A + 1 micromanagement address is written to register 21 by the signal T, and even by the even one to register 20 by the signal T.

The information stored in register 20 controls the operation of node 3.

The number of the general purpose register (RON) of node 3 is generated by nodes 12 and 13 synchronously to signal T.

The dotted lines in FIG. 5 shows the passage of information simultaneously for three consecutive values of the next address of microinstructions (A, A - 1, A + 2).

At the time interval x, the following actions occur:

under the control of registers 20 and 21, arithmetic or logical operations are performed in node 3; signs of the word of the process state are formed

dy

At the same time, under the control of register 18, containing information about the number of microcommand A + 1 (sequence diagram 30 9), the odd is selected from node 19 (sequence diagram 7), and then the even address of A + 1 microcommand is recorded from node 19 at the even odd address in regist 21 (cyclogram 4) and on the even adres su in register 20 (cyclogram 3)

The number of the general purpose register of node 3, containing the operand necessary to perform the operation, is stored in node 12 or 13 synchronously with the operation of node 3 (sequence diagram 10).

From the timing diagram (Fig. 6) and the block diagram of the management organization (Fig. 5), it can be seen that the proposed scheme implements a conveyor

35

40

and recorded at the end of the time-interval of the 2nd generation of the next micro address into the controller 9; commands, i.e., when the control of register 18 is executed and the sign T is selected twice (odd, then the even address MK A - 1 ) information from node 19 and at the end of the inter-,. time shaft x is recorded, respectively, in register 21 (odd address) and register 20 (even address);

under the control of a 4-bit bus with a group of outputs of register 20, node 17 generates the next sampling address, micro-commands A-2 and, at the end of time interval x, is written to register 18.

55

Under the control of the microcommand A, in the node 3 under the control of the register 18 is selected from the node 19 of the information A + 1 of the microcommand, and in the node 17 the address A + 2 of the microcommand is generated.

Combining the process of generating the next address for microinstructions A, A + 1, A + 2 creates the possibility of a significant reduction in its execution time.

Operator 1 prepares multiply operands, i.e. places the multiplicand and multiplier in devices 3 "multiplier

eight

Q 5

0

The dynamics of the formation of the next microcommand address, the operation of nodes 3 and 9 are explained in the timing diagram shown in FIG. 6, on which the numbers of cyclograms are vertically marked from top to bottom, horizontally - the durations and types of cyclograms with the allocation of the time interval x.

The cyclograms 1 and 2 show the sequence of sync pulses T and T, synchronizing the operation of the device.

On cyclograms 1-10, the work of the sequence of micro-instructions from A-1 to A + 5 is considered.

Suppose that time point x corresponds to the execution of micro-command A according to the cyclogram 5 in node 3

Then in register 20 (cyclograms 3 and 4) there is information controlling the operation of the A-th micro-command, and in register 21 during the first half-period there is information for the A-micro-command, and during the second half of the period for A + 1 micro-command.

At the same time, under the control of register 18, containing information about the number of microcommand A + 1 (sequence diagram 0 9), odd is selected from node 19 (sequence diagram 7), and then the even address of A + 1 microcommand, from node 19, at an odd address is written into the register 21 (cyclogram 4) and at an even address in register 20 (cyclogram 3)

The number of the general purpose register of node 3, containing the operand necessary to perform the operation, is stored in node 12 or 13 synchronously with the operation of node 3 (sequence diagram 10).

From the timing diagram (Fig. 6) and the block diagram of the management organization (Fig. 5), it can be seen that the proposed scheme has a conveyor for

five

0

Under the control of the microcommand A, in the node 3 under the control of the register 18 is selected from the node 19 of the information A + 1 of the microcommand, and in the node 17 the address A + 2 of the microcommand is generated.

Combining the process of generating the next address for microinstructions A, A + 1, A + 2 creates the possibility of a significant reduction in its execution time.

Operator 1 prepares multiply operands, i.e. places the multiplicand and multiplier in devices 3 "multiplier

is sent to the shift register multiplied in the general register at an odd address (for example, 15), in the general register that is different at the address of the low-order bit (E of our example with address 14), placed before the multiplication procedure information with the code 0 ... 0, and in the future - the sum of partial products

Operator 2 loads into the cycle counter, placed in node 17, information equal to the number of multiplication cycles (with a 16-bit multiplier 16). $

When performing a multiplication cycle, operator 3 subtracts one from the contents of the Cycle counter at node 17 and transfers control:

operator 4 in the case of information 20 of the loop counter, is not equal to zero;

operator 7 in the case of information in the loop counter is zero, i.e. at the end of the multiplication cycle.

In each 25 cycle, the C operator analyzes the value of the lower bit of the Q shift register of node 3, transfers control to operator 5 in the case of Q6 0, to operator 6 in the case of Q0 1,.

Operator 5 performs a summation of the general register of the accumulator of the sum of partial products with general register 14, containing information equal to zero, and a census of the obtained sum of partial products 5 into general register 9. The same operator shifts the contents of general registers 9 and Q (the sum of partial products and the multiplier by bit to the right), and the younger bits of the contents of general register 9 (tail) flow into the higher bits of register Q.

The low-order bit of the register Q is pushed out of the register and disappears. 45

Operator 6 performs a summation of general purpose register 9 (accumulator of the sum of partial products) with general register 15 containing the multiplicand, and a census of the obtained sum of partial products into general register 9. Both operators unconditionally transfer control to operator 3 "The cycle is repeated .55

At the end of the cycle, the operator 7 generates the signs of the state of the state by the result of the multiplication

and sampling the next command line.

The execution of operators 3 - 5 branches A and 3, 4 and 6 of branch B is combined in one micro-command (1 micro-tact). With the duration of microtact 250, the multiplication cycle time is not 250 ns.

When multiplying two 16-bit numbers, Tz 250 is not x 16 4000 not.

The execution of all operators of the multiplication cycle by one micro-command is carried out with the help of node 12 (Fig. 3)

In the microcommand of the cycle Multiplication, the following actions are performed simultaneously:

decrement the contents of the cycle counter node 17;

summation of the contained general purpose registers with an odd number, for example, 15, where the multiplicative value is preliminarily recorded, and with any number in the range 0-13, in which the value of the sum of partial products accumulates, for example, 9

sending the result to the selected in the range of 0-13 general register, for example 9;

emulation of the zero bit of the address under control of the signals C1, C2 (at C2 0, d 0, i.e. the address from the original odd becomes even at the value of the lower order multiplier (C2) equal to zero and, conversely, at C2 1, d 1, i.e., with the value of the least significant bit, the multiplier (C2) equal to one remains odd;

shift one bit to the right of the shift register Q of node 3, containing the multiplier value and general purpose register 9 of partial products (the lower bit of the multiplier is present at the input of node 12 as a control signal C2);

analysis of the contents of the cycle counter of node 17 and the formation of the transfer control address (when (/K.ts/) 0 control is transferred to the repetition of the microcommand Multiplication, when / Rc4iU (/ 0 to execute the microcommands of the operator 7 (Fig. 6)) Sent pre-information OO..O.

The main operations in the multiplication operation are performed in block 1 between sections 4-7 and controller 9 as shift operations on the multiplier registers. and the register of partial products, which are shift register 10

15

The D inputs of cells 4–7 as an operand of the next operation or through the inputs – outputs of the imaging unit 10 to the data bus 2k for storing in external media.

In case of storing the result of calculations in the external RAM, the microcommands generate the address of the external RAM cell from the first outputs of the register 11 to the bus 25, provide the interface for receiving the address from the register 11 and data from the generator 10 via the bus 2k to the external RAM.

Due to the convolution of the time processes occurring in block 2 during the sampling of the address of the next microcommand, a shorter time step is achieved when the equipment of block 2 is reduced

mi q and s node 3

The work on performing arithmetic and logical operations on operands in node 3 is carried out under the control of the microcommand fields from the first output groups of register 21 (12-bit bus) and register 20 (9-bit bus);

Under the control of signals, a group of outputs of register 21 selects nodes 12 and 13 of the sources of addresses of operands of the internal random access memory of node 3 (source 1 — register 14, source 2 — register 21).

From the outputs of register 20 is produced

control of arithmetic or logic-20 processing of information (250 non), by scaling operations in node 3 over operands.

Operands can be used depending on the values of the control functions of the node 3 arriving from 25 inclusions, a regular bus and a 5-bit bus register-Signal 11, bus installation 29, sig

ra 20, from the internal random access memory of the node 3 or from the data bus through the driver 10 to the D-inputs of the node 3.30

According to the results of operations on operands in ALU 3, signs (Z, C, V, N-Bxoflbi of controller 9) of the word state of nodes are generated.

Control signals from a 13-bit output from a group of outputs to a 4-bit bus of outputs of the register 21 in the control bus to a group of inputs of the node T, the scooter 9 memorizes and processes the status word and, depending on their combinations, produces a signal F to organize the process of branching the microprogram. Process - the exchange of information with external devices is done via interface,

Consider the work of AU, starting with the ms of the moment of inclusion, t, e „initialization of the initial address of the microprogram

identifying the absence of secondary supply voltages or the presence of transients when they are established, goes to the second input of register 20, In register 20, under control of CHI-nal. Setting field 4 (Fig. 4) produces control function of node 17 to generate address O.O. , post 17 produces a 12-bit address (0 ... 0) and exposes it to the output

The register 18 writes the specified 0 ... 0 (even) address using the clock signal T and begins to fetch the contents of the zero cell of the node 19 (most significant bits, 32-63) with the recording of information 45 using the clock signal T into the register 21.

address bus 25 and data 24.

If it is necessary to transfer, the exchange of information with external data carriers over the interface is a type. Bus bus. Address and Data are combined.

From the first outputs of register 11, a 16-bit address code and signs to accompany it are sent to the CQ of well 25 address.

The result of operations on operands

Register 18 on the clock signal T writes the specified 0 ... 0 (even) address and begins sampling the content zero cell of node 19 (most significant bits, 32-63) with recording information 45 on the clock signal T in register 21.

The clock pulse T connects the lower-order address at the input of the node 19. Address 00 ... 01 (odd) selects from the node 19 the contents of the first cell and records the clock signal T into register 20 (lower bits 0-31) from the clock signal T. This ends the initialization process.

initial address of the firmware Incialization, in progress

which is loaded, installed

From the first outputs of the k-7 cells, 5 values of various counters and nodes at the inputs of the imaging unit 10 for the zalomy-blocks 1 and 2 returned to the initial state. nani in the buffer register and broadcast through the outputs of the former 10 on

The initialization program ends with loading into register 4 of the first command.

The D inputs of cells 4–7 as an operand of the next operation or through the inputs – outputs of the imaging unit 10 to the data bus 2k for storing in external media.

In case of storing the result of calculations in the external RAM, the microcommands generate the address of the external RAM cell from the first outputs of the register 11 to the bus 25, provide the interface for receiving the address from the register 11 and data from the generator 10 via the bus 2k to the external RAM.

Due to the convolution of the time processes occurring in block 2 during the sampling of the address of the next microcommand, a shorter time step is achieved when the equipment of block 2 is reduced

 information processing (250 not),

 on, Signal 11 Bus installation 29, sig

Consider the work of AU, starting with the ms of the moment of inclusion, t, e „initialization of the initial address of the microprogram

barking from a group of outputs on a 4-bit bus to a group of inputs of node T,

identifying the absence of secondary supply voltages or the presence of transients when they are established, is fed to the second input of register 20, In register 20, under control of CHI-nal. Setting field 4 (Fig. 4) turns out the control function of node 17 to generate address O.O. posting from a group of outputs on a 4-bit bus to a group of inputs of node T,

Node 17 generates a 12-bit address (0 ... 0) and exposes it to the output.

The register 18 writes the specified 0 ... 0 (even) address according to the clock signal T and begins to sample the contents of the zero cell of the node 19 (most significant bits, 32-63) with the recording of the information on the clock signal T in the register 21.

The sync pulse T connects the lower-order address at the input of the node 19. Address 00 ... 01 (odd) selects from node 19 the contents of the first cell and writes the synch signal T to register 20 (lower bits 0-31). This ends the initialization process.

initial address of the firmware Initialization, in progress

which is loaded, installed

the values of the various counters and nodes of blocks 1 and 2 to the initial state.

the values of the various counters and nodes of blocks 1 and 2 to the initial state.

The initialization program ends with loading into register 4 of the first command.

by signal from the decoder 23, received from the storage device. The command bits from the second group of DSPs on a 16-bit bus go to decryption to the decoder 16. The data on the second group of inputs of the decoder control the outputs of the decoder, switch the outputs from high impedance to active mode. At the same time, the signals at the output of the decoder 15 and at the fifth group of outputs of register 20 (return address) are in a state of high impedance, i.e. disabled., .J5

From the output of the decoder 16 to the 12-bit bus, the starting address of the firmware of the command goes to node 17, is broadcast by it, is emulated depending on

by the measure specified in 0 - 2 bits of the manda. The third microinstruction exposes the contents of the specified general register from node 3 to output 11 of register 11, is recorded in it and is set as the address of the operand on the trunk 25. Selected from the external memory of the operand (multiplicand) from highway 2k enters the driver 10 and from it to the D-input cells 4-7.

The bus driver 10 performs an interface exchange procedure, i.e. receiving information on tracking signals and issuing appropriate acknowledgment signals on the reception and formation of external memory. The following (fourth) micro-command records information (multiplicative) in the fifteenth

functions from the control function of the transmission-2Q general purpose register (in our

example) of node 3. Two subsequent microinstructions send the constant from the fifth group of outputs to a 9-bit bus (in our case, 0 ... 0). Through generator 10 in general register 14 (in our example) and general register 9. With the help of shaper 10, by multiplying the most significant bit of the (ninth) constant and exchanging bytes between each other, combine any constant in the whole range of the 16-bit number.

The addresses coming from the fourth group of outputs of the register 20. The emulated address comes from the output of node 17 to the group of inputs of register 18 and, in the case of sampling, the initialization address is selected twice during the clock cycle from the microcommand memory node and written to registers 21 and 20.

Suppose that the next command is selected from the external storage device via the bus 24 data - the Multiplication command. From the condition that the code of the first multiplication microcommand is set in registers 20 and 21, the multiplication firmware is executed in accordance with the algorithm (FIG. 7).

The execution of statement 1 is to act upon a selection of information of a multiplier and a multiplicand of general registers or external memory cells. The location of the source operands and the methods for addressing the memory are determined by the instruction set. Assume that the implemented command system type SM-4. In this case, the contents of the general register number specified in the 6–8 bits of the word for the ampoule is a multiplier. The first microinstruction selects the contents of the general register (multiplier) and rewrites it within node 3 into the register Q.

The multiplier, depending on the addressing system specified in the command's 0-5 bits, is selected by the generated address from the external memory.

Suppose the addressing method is used when the address is placed in the general register with but

0

the measure specified in 0 - 2 bits of the cat manda. A third microinstruction exposes the contents of the specified general register from node 3 to the output of register 11, is recorded in it and set as the address of the operand to the highway 25. Selected from the external memory of the operand (multiplicand) from the highway 2k enters the driver 10 and From it to the D-input cells 4-7.

The bus driver 10 performs an interface exchange procedure, i.e. receiving information on tracking signals and issuing appropriate acknowledging signals on receiving information from an external memory. The following (fourth) micro-command records information (multiplicative) in the fifteenth

general purpose register (in our

Q general purpose register (in our

25

30 $$

about 45 0

five

example) of node 3. Two subsequent microinstructions send the constant from the fifth group of outputs to a 9-bit bus (in our case, 0 ... 0). Through driver 10, into general register 14 (in our example) and general register 9. With the help of shaper 10, it is possible by multiplying the most significant bit of the (ninth) constant and exchanging bytes among themselves to combine any constant in the whole range of the 16-bit number.

Having performed the action of operator 1, we perform operator 2 according to the multiplication algorithm of fig. 7. The following microinstruction sends information on a 12-bit bus C1 of the output group of register 20 of the constant Address in node 17, where the information is stored in a special cycle counter.

Generating the next micro-command address when moving from the first micro-command to the second, etc. carried out from the outputs of the register 20 on the 4-bit bus. Moreover, each microinstruction number N indicates the address of the sample from the NULL N + 2 microinstructions.

Having performed the actions of operators 1 and 2 (Fig. 7), we perform operators 3–5 multiplication cycles. These statements are executed during the execution of one microcommand Multiplication. For explanation, consider all the fields of the Multiply microcommand (Fig. 4). In field 5 of register 20, the 3 Shift format is used, the shift functions of the controller 9 are controlled: right shift of registers 9 and Q of general purpose.

151559340

In field 4, information is set that controls node 17 so that the register-counter of cycles is analyzed and its state is analyzed to go to (Rt4) 0 to repeat the microcommand.

sixteen

multiply, but by state (/ N / c /)

 0 - to perform operator operation 17.

The first field of register 20 is controlled by node 3 — a summation operation is performed and the received sum of partial products is sent to the address specified in the first field of node 13. In the first field of node 12, an address (POH number) is indicated, in which is multiplicand (address in our example 15). Unreviewed fields

11. The read out information from the external memory (command) is written to register 14 and the next command starts to be executed.

It is necessary to clarify the principle of receiving and processing the interrupt signals of node 22. Node 22 during the execution of the current firmware to

JQ commands receive, memorize interrupt signals from the digital computer and carry out interrupt processing according to the priorities assigned to them. Highest Received Interrupt Signal

15 into a 3-bit vector arriving at the inputs of the decoder 15. Sampling at the address of the vector is resolved after the command firmware is executed at the time of loading the initial address

microinstructions are set as follows from the decoder 16. From the output

Dov register 20 receives control of the selection and loading of addresses and microcommands from three possible sources from the outputs of nodes 20, 15 and 16.

at once, so that the actions of the devices controlled by them do not create mutual interference (blocked).

Node 12 emulates a zero-bit address of the general register of the general-purpose register under the control of the low-order bit-register of the Q body using the decoder 31.

With Qo 0, the address from the output of node 12

Dov register 20 receives control of selecting and loading addresses and micro commands from three possible sources: from the outputs of nodes 20, 15 and 16.

The state of these outputs at any one time is such that only one can be active, and the rest must be in a high impedance state (turned off)

even (14), With Q0 1 address from output-30 it is possible to disconnect all three sources of node 12 odd (15).

General register 15 contains multiplicative information.

General register 14 contains information 0 ... 0. d5

Therefore, actions of operators 4,5 or 4,6 are performed, namely:

RON + RON - RON, with 0 sh 1; RON - RON, at 0 0, and the subsequent shift to the right by one

40

bit of the contents of the registers ROND and Q. As a control on the input. 4 nodes 12 will enter the next bit multiplier and all actions will be repeated as many times as bits in the multiplier-45 inhabitant

NIKOV.

If a 3-bit bus signal is generated from the outputs of node 22, indicating that there is a requirement of at least one interrupt, certain outputs of the tristable sources of the microcommand of nodes 15–16 and 20 are switched, namely, the output of the decoder 15 becomes active.

The result is that instead of loading the starting address of the next command from decoder 16, the starting address of the interrupt signal of the highest priority interrupt signal from the received one is loaded.

At the end of the multiplication cycle, the sequence of microinstructions is performed by the actions of operator 7, which, based on the results of multiplying the recognition of the word of the controller 9 state (1-2 microcommands),

Next, the sampling address of the next microcommand to register 11 is generated, i.e. information from one of the general purpose registers of node 3 (command counter) from the information outputs of node 3 is entered in the register

J

sixteen

11. The read out information from the external memory (command) is written to register 14 and the next command starts to be executed.

It is necessary to explain the principle of receiving and processing the interrupt signals of node 22. During the execution of the current firmware, the command 22 accepts, memorizes interrupt signals from the digital computer and processes the interrupts according to the priorities assigned to them. The highest received interrupt signal transforms

into a 3-bit vector arriving at the inputs of the decoder 15. Sampling at the address of the vector is resolved after the command firmware is executed at the time of loading the initial address

following from the decoder 16. From the output

Dov register 20 receives control of selecting and loading addresses and micro commands from three possible sources: from the outputs of nodes 20, 15 and 16.

The state of these outputs at any one time is such that only one can be active, and the rest must be in a high impedance state (turned off)

it is possible to turn off all three sources

NIKOV.

If a 3-bit bus signal is generated from the outputs of node 22, indicating that there is a requirement of at least one interrupt, certain outputs of the tristable sources of the microcommand of nodes 15–16 and 20 are switched, namely, the output of the decoder 15 becomes active.

The result is that instead of loading the starting address of the next command from decoder 16, the starting address of the interrupt signal of the highest priority interrupt signal from the received one is loaded.

The end of the interrupt processing microprogram execution is again the micro-command of loading the micro-command's initial address from the decoder 16. There are no interrupts, then the next command from the register 14 of the commands is executed.

Claims (1)

Claims. A firmware arithmetic unit containing an arithmetic logic unit consisting of N computational cells, an accelerated transfer node, a bus driver, a state controller, a memory address register, two operand selection nodes, each of which contains an address multiplexer and a buffer register, and a microprogrammed control unit, containing the JQ command register, command decoder, Interrupt decoder, firmware control node, microinstructions memory node, first microcommand register and interrupt handling node, the data bus J5 connected to the first group inputs of the bus driver and information inputs of the command register, outputs of the bits of the first group of the command register are connected to the control inputs 20 of the address multiplexer of the first operand selector node, outputs of the bits of the second group of the command register are connected to the control inputs of the address multiplexer of the second node of operands 25 , the outputs of the bits of the third group are connected to the information inputs of the command decoder, the outputs of the command decoder and the interrupt decoder are connected to the first and second groups of address inputs the microprogram control node, the output of the interrupt vector of the interrupt handling node is connected to the information input of the interrupt decoder, the output of the bus driver is connected to the information inputs of N computational cells, the group of information outputs of which are connected to the information inputs of the memory address register, whose outputs are the address bus the device, the first, second and third outputs of the state of the first computational cell are connected to the inputs of the overflow sign and the transfer, respectively About the state controller, the first and second outputs of the bidirectional shift circuit of the i-th (where i 1,2 ,, .., N-1) computational cell are connected to the same-named (1 + 1) -th computational cell, the first and second you the shift propagation moves of the state controller are connected to the first and second inputs of the bi-directional shift circuit of the first computational cell, respectively; the third and fourth outputs of the shift of the state controller shift are connected to the first and second outputs of the bi-directional circuit  40 .,-50 N JQ J5 20 25,, 40 50 the shift of the Nth computational cell, the outputs of the distribution and transfer resolution of the (1 + 1) -th computational cell are connected to the inputs-outputs of the accelerated transfer node and the serial transfer inputs of the i-th computational cell, the output of the state controller transition condition is connected to the resolution input retrieving the address of the firmware control node, the transfer output of the state controller is connected to the serial transfer inputs of the Nth computational cell and the accelerated transfer node, the direct clock input of the device is connected to synchronous inputs of the state controller, firmware control node, address registers of the first and second operand selection nodes, the outputs of which are connected to the first and second inputs of the address, respectively, of all the computational cells, so as to increase the speed of the multiplication operation at one - time-wise hardware reduction, the address formation register is entered into the firmware control block, the second micro-register register, the bit control signal decoder, the first operand selection node is entered the address decoder, the output of which is connected to the write enable input of the buffer register of the first operand selection node, the zero bit of the multiplexer output of the address of the first operand selection node is connected to the first the input of the decoder bit control signals, the outputs from the first to the third bits of the multiplexer address of the first and second nodes of the operand selection are connected to the information inputs of the corresponding address register, the address outputs The microcommands of the firmware control node are connected to the information inputs of the address generation register, the outputs of which are connected to the address inputs of the microcommand memory node, the outputs of which are connected to the information inputs of the first and second microcommand registers; the second group of outputs of the first register of micro-commands is connected with the second group of inputs of the bus driver, the third group of 19 the first register of micro-instructions is connected to the third group of address inputs of the microprogram control node; the fourth group of outputs of the first register of micro-commands is connected to the control inputs for receiving and output of the bus driver; first one the micro-command register register is connected to the input of the interrupt processing unit, the seventh group of outputs of the first register of micro-commands is connected to the inputs of microcomputers of all computation cells, the first group of outputs of the second register of micro-commands is connected to the inputs of microcommands of the state controller, connected to the control inputs of the formation of the address of the register of the memory address and the control input of the formation of the characteristics of the tracking address 15 address and the address of the bus i driver, the third and the fourth and the groups of outputs of the second register of micro-commands are connected to the information inputs of multiplexers AD / 30 . 20 the first and second operand selection nodes, respectively, the fifth group of outputs of the second micro-register register is connected to the inputs of the bit control signal decoder, the first output of which is connected to the write register write enable input, the second output of the bit control signals decoder is connected to the second address of the address decoder, the third whose input is connected to the first output of the bidirectional shift circuit of the Nth computational The interrupt processing is connected to the control inputs of the interrupt decoder, the command decoder and the microinstruction register, the installation input of which is connected to the installation input of the device; the inverse clock input of the device is connected to the synchronous input of the second register of microinstructions, the second group of inputs of the bus driver is connected to the group of information in odov memory address register. Phie.1 MUL Qo Cl cr 2: CJ. T, 37 IIP b four W SP 5x.b h t ; et P / V Out -  Z3f-tzz -tzzt- with 4 &P(# OfeS & Vftf WITH Start } LL Preparing Operands S MUZ Registers Download cycle counter multiply 8 node 17 RON + RON9- ROND and ± Body multiply I Formation of signs of state With horses j 15593 0 Not