JP2900581B2 - Instruction control pipeline structure - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an instruction control pipeline structure in an instruction control device.

[Conventional technology]

2. Description of the Related Art Conventionally, an instruction control pipeline is provided in an instruction control device, and the number of times per unit time to decode an instruction and send an execution instruction to various execution units that execute the instruction, such as an operation execution unit and a memory control unit. Increase,
Thereby, the performance is improved. Here, the instruction control pipeline to which the present invention is applied is a pipeline of processing from the stage following the instruction fetch stage to the stage where an operation instruction is given to the arithmetic unit. In such an instruction control pipeline, for example, a pipeline consisting of four stages of an instruction decoding stage, an operand address calculation stage, an operand fetching stage, and an operation instruction stage to an operation unit, and an operand fetching stage are further provided. A pipeline composed of five stages subdivided into an address translation stage and a buffer access stage is used. Each stage has
An instruction register for holding the processing result of the stage is provided, and the output of the instruction register is used as an input to the next stage. The information held in the instruction register of each stage is referred to as instruction control information in this specification. In the instruction control pipeline, the processing of each stage can be executed simultaneously and concurrently without interference from others, so that an instruction execution instruction can ideally be issued every machine cycle.

By the way, if only one instruction control pipeline is provided in the instruction control device, there is not much problem with an intermittent failure, but if a fixed failure occurs, it immediately leads to a system down. That is, since the intermittent fault is a fault that occurs accidentally and has no reproducibility, if an invalid parity is detected in a certain stage of the instruction control pipeline, for example, an instruction retry is performed to restart the processing from the preceding stage. This ensures a normal operation. However, since the fixed fault is a continuous fault, the normal operation cannot be performed even if the instruction retry is attempted many times, and the system is brought down.

Therefore, in order to prevent a system failure even if a fixed fault occurs in the instruction control pipeline, it is called a superscalar in which a plurality of instruction control pipelines of the same type that operate asynchronously with each other are provided in the instruction control device. A scheme has been proposed. In such a method, if a fixed fault occurs in any of the instruction control pipelines, the degraded method is such that the faulty instruction control pipeline is removed from the operation target and the operation is continued in the remaining instruction control pipelines. , Normal operation can be continued.

[Problems to be solved by the invention]

According to the instruction control apparatus of the type in which a plurality of instruction control pipelines of the same kind operate asynchronously as described above, an excellent advantage that even if a fixed failure occurs in any one of the instruction control pipelines, a system down can be avoided. However, there are some problems to be improved even in such an instruction control device.

One of the problems is that it is difficult to quickly transfer the processing executed in the instruction control pipeline in which a fixed failure has occurred to a normal instruction control pipeline.

Second, if an instruction is suspended at a certain stage in an instruction control pipeline due to a halt factor in the pipeline, the following instruction will be executed for a reason other than that the preceding instruction is suspended. That is, it must be stopped on the instruction pipeline, even though there is no reason to stop.

The present invention is intended to solve such a problem, and an object of the present invention is to make the most of the advantage of having a plurality of instruction control pipelines of the same kind and to provide a communication function between the instruction control pipelines. Accordingly, it is an object of the present invention to provide an instruction control pipeline structure that allows a process performed in one instruction control pipeline to be immediately transferred to another instruction control pipeline.

[Means for solving the problem]

In order to achieve the above object, the present invention provides an instruction control having the same configuration in which processing from decoding of an instruction fetched by an instruction fetch unit to an operation instruction to a scalar operation unit is divided into a plurality of stages and executed in parallel. An instruction control device including a plurality of pipelines, wherein an instruction register of a first stage of a first instruction control pipeline has the first instruction control pipeline in a second instruction control pipeline different from the first instruction control pipeline. A signal line for transferring instruction control information held in an instruction register of a stage preceding the stage corresponding to the stage corresponding to the first stage in the second instruction control pipeline. And at least one of two signal lines for transferring instruction control information held in the instruction register of the stage to be transferred. Have adopted the decree control pipe line structure.

[Action]

In the present invention, the signal line of the first stage controls the instruction register of the first stage of the first instruction control pipeline.
The instruction control information held in the instruction register of the stage preceding the stage corresponding to the first stage in the second instruction control pipeline different from the second instruction control pipeline can be transferred. The instruction control information held in the instruction register of the stage corresponding to the first stage in the second instruction control pipeline different from the first stage can be transferred to the instruction register of the first stage of the instruction control pipeline.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which the present invention is applied to an instruction control device having two instruction control pipelines of the same type composed of five stages A to E. is there. For example, as described in [Prior Art], the processing from the stage following the instruction fetch stage to the stage of instructing the operation unit to perform the operation instruction is performed by the instruction decoding stage, the operand address calculation stage, and the operand When dividing into five stages, an address translation stage for fetching, a buffer access stage for fetching operands, and an operation instructing stage to the operation unit, the A stage is for decoding instructions and the B stage is for calculating operand addresses. , C stage corresponds to an address translation stage for fetching operands, D stage corresponds to a buffer access stage for fetching operands, and E stage corresponds to an operation instruction stage to an operation unit. As shown in FIG. 1, the instruction control device includes an instruction fetch unit 1 and instruction registers 2 to 6, a BUSY flag 12a to 16a, and a HOL, which constitute one instruction control pipeline.
D flags 12b to 16b, failure detection circuits 25 to 29, and instruction registers 7 to 11, B constituting the other instruction control pipeline
It includes USY flags 17a to 21a, HOLD flags 17b to 21b, failure detection circuits 30 to 34, a pipeline control unit 22, an instruction issue arbitration unit 23, and a scalar operation unit 24. And these connection relations are as follows.

The instruction fetch unit 1 is connected to instruction registers 2 and 7 in the A0 stage and the A1 stage by signal lines 102 and 107, respectively.

Between the A0 and B0 stage instruction registers 2 and 3; between the B0 and C0 stage instruction registers 3 and 4; between the C0 and D0 stage instruction registers 4 and 5; and between the D0 and E0 stage instruction registers 5 and 6 Between, signal lines 203, 304, 405, 506
Between the A1 and B1 stage instruction registers 7 and 8, and the B1 and C1 stage instruction registers 8 and 9
Between instruction registers 9 and 10 of C1 stage and D1 stage, D1
The instruction registers 10 and 11 of the stage and the E1 stage are connected by signal lines 708, 809, 910 and 1011.

Between the A0 and A1 stage instruction registers 2,7, between the B0 and B1 stage instruction registers 3,8, between the C0 and C1 stage instruction registers 4,9, and between the D0 and D1 stage instruction registers 5,10 Signal lines 207 and 702, 308 and 803, 40 between instruction registers 6 and 11 in the E0 and E1 stages.
9 and 904, 510 and 105, 611 and 116.

Between the A0 and B1 stage instruction registers 2 and 8; between the B0 and C1 stage instruction registers 3 and 9; between the C0 and D1 stage instruction registers 4 and 10; and between the D0 and E1 stage instruction registers 5 and 11 Stage, between the A1 and B0 stage instruction registers 7,3, between the B1 and C0 stage instruction registers 8,4, between the C1 and D0 stage instruction registers 9,5, and between the D1 and E0 stage instruction registers 10. , 6
The lines are connected by signal lines 208, 309, 410, 511.703, 804, 905, 106.

A0 stage, B0 stage, C0 stage, D0 stage, E0
The stage failure detection circuits 25, 26, 27, 28, 29 are connected by signal line 2522, and A1 stage, B1 stage, C1 stage, D1 stage.
The stage and E1 stage failure detection circuits 30, 31, 32, 33, and 34 are connected to the pipeline control unit 22 by signal lines 3022, respectively.

BUSY flag 12 indicating that a valid instruction exists in the A0, B0, C0, D0, and E0 stages
a, 13a, 14a, 15a, 16a, and HOLD flags 12b, 13b, 14 indicating that the instruction remains at that stage in the next machine cycle.
b, 15b, 16b are BUSY flags 17a, 18a, 19a, 20a, 21 indicating that there are valid instructions in the A1 stage, the B1 stage, the C1 stage, the D1 stage, and the E1 stage by the signal line 1222.
a and the HOLD flags 17b, 18b, 19b, 20b, 21b indicating that the instruction remains at that stage in the next machine cycle,
Each is connected to the pipeline control unit 22 by a signal line 722.

Selector 35,3 at the entrance of instruction register 2,3,4,5,6 of A0 stage, B0 stage, C0 stage, D0 stage, E0 stage
6, 37, 38, and 39 are instruction registers for the A1, B1, C1, D1, and E1 stages via the signal line 222.
7, 8, 9, 10, 11 selectors 40, 41, 42, 43, 44 at the entrance of signal line 2
27 are connected to the pipeline control unit 22 respectively.

The instruction issuance arbitration unit 23 is connected to the pipeline control unit 22 by a signal line 2322, and the scalar operation unit 24 is connected to the signal line
2324 is connected to the instruction issue arbitration unit 23.

Since this embodiment has the above-described configuration, it is possible to move instruction control information between both instruction control pipelines. Therefore, in this embodiment, (1) the two instruction control pipelines process different instructions independently and asynchronously.

(2) The processing of one instruction control pipeline is taken over by the other instruction control pipeline.

It has realized that.

The operation (1) is performed as follows. First, an instruction is read from a memory (not shown) by the instruction fetch unit 1, and from there, the instruction register 2 of the A0 stage of one instruction control pipeline or the A1 stage of the other instruction control pipeline through the signal line 102 or 107. To the instruction register 7. Then, regarding the instruction, the processing of each stage is performed in each stage in the order of A, B, C, D, and E, and the instruction stays in that stage until the processing in each stage is completed and the next stage can be performed. Is controlled by the pipeline control unit 22 as described above.
Then, an instruction is issued, that is, an operation instruction is given to the scalar operation unit 24 from the final stages E0 and E1. At this time, if an instruction is issued from both the E0 stage and the E1 stage to the scalar operation unit 24 at the same time, the instruction issuance arbitration unit 23 communicates with the pipeline control unit 22 via the signal line 2322. Exchanges and signal lines
By controlling operation instructions given to the scalar operation unit 24 via 2324, arbitration is performed so that instructions are not issued from both sides at the same timing.

FIGS. 2 and 3 are time charts of the arbitration operation for avoiding the issuance of the instruction to the scalar operation unit 24 at the same timing in the final stages E0 and E1.

FIG. 2 shows that when instructions 1 and 2 attempt to issue instructions to the scalar operation unit 24 at the same time in the final stages E0 and E1, one of the instructions is executed in accordance with the priority order predetermined between the instruction control pipelines. An example is shown in which issuance of instructions at the same timing is avoided by giving priority to issuance and delaying the other. That is, in this example, the instruction in the E0 stage is issued with priority first, and then the instruction in the E1 stage is issued. In such a case, the instruction issuance arbitration unit 23 checks the status information transmitted from the pipeline control unit 22 via the signal line 2322 to confirm that there is an instruction whose issuance conflicts with the E0 stage and the E1 stage. Signal line so that instruction 1 of high E0 stage is issued at the timing
An operation instruction is issued to the scalar operation unit 24 through 2324, and the instruction 2 of the E1 stage is controlled by the pipeline control unit 22 so as to remain at the E1 stage at that timing, and is controlled so that the instruction 2 is issued at the next timing. I do.

FIG. 3 shows that when the instruction 1 is waiting in the E0 stage for another factor, for example, waiting for operand data confirmation, the instruction is issued first in the E1 stage having a low priority, thereby efficiently and at the same timing. Here is an example of avoiding the instruction issue. That is, FIG. 3 shows instruction 1 and instruction 2 similarly to FIG.
Arrived at the final stage E0, E1 at the same time, but instruction 1
Since instruction cannot be issued until the timing because the operand is undetermined, instruction 2 is issued earlier despite the low priority E1 stage. Such control is performed by the pipeline control unit 22 through the signal line 2322.
The instruction issuance arbitration unit 23 determines whether or not an instruction can be issued in the next machine cycle based on the information sent through the CPU, and appropriately instructs the scalar operation unit 24 and the pipeline control unit 22 accordingly. This is done by issuing

Next, the operation of (2) for transferring the processing of one instruction control pipeline to the other instruction control pipeline is performed as follows.

First, when a fixed fault occurs in a control block (not shown) around a certain instruction register of one instruction control pipeline, an operation of taking over the processing to another normal instruction control pipeline is performed in the C0 stage. The following describes an example in which a fixed failure has occurred.

As shown in FIG. 4, if the instruction 1 is normally processed in the A0 stage and the B0 stage, and a fixed failure occurs in the C0 stage at the time of moving to the C0 stage, the failure detection circuit
Pipeline control unit detected by signal line 2522 at 27
Reported on 22. Upon receiving this report, the pipeline control unit 22 checks the corresponding BUSY flag and HOLD flag of the other instruction control pipeline through the signal line 1722, and
It is checked whether or not the condition that the stage is empty and another instruction does not flow from one stage is satisfied. If the condition is satisfied, the selector 42 at the entrance of the instruction register 9 of the C1 stage is connected to the signal line 409 by the signal line 227. Switch to the side. Thereby, as shown in FIG. 5A, the instruction control information of the instruction register 4 of the C0 stage is moved (evacuated) to the instruction register 9 of the C1 stage via the signal line 409. The timing is shifted to the C1 stage at the timing as shown in FIG. Thereafter, the instruction 1 flows through the C1, D1, and E1 stages as shown in FIG. Note that the pipeline control unit 22 logically closes the signal lines 304, 804, and 904 to disable the C0 stage in which the fixed failure has occurred. FIG. 5B shows such a state.

In the example shown in FIG. 4, it is assumed that no instruction is flowing through another instruction control pipeline, but when an instruction is flowing, the following control is performed. That is, as shown in FIG. 6, when another instruction 2 flows from the B1 stage to the C1 stage at the time of moving the instruction 1 of the C0 stage to the C1 stage, the pipeline control unit 22 avoids a collision at the C1 stage. Instruction 1 for one machine cycle longer
Stop on the stage and move to the C1 stage when it becomes possible to move.

By performing the above operation, the processing executed in the instruction control pipeline in which the fixed failure has occurred can be quickly taken over to the normal instruction control pipeline. Note that the above description is for the case where a fixed fault occurs in the C0 stage. However, in the embodiment of FIG. Stage, B1 stage, D1 stage, E1 stage, and A1 stage by signal lines 702, 803, 904, 105, 116.
Since the instruction control information of the B1, C1, D1, and E1 stages can be transferred to the A0, B0, C0, D0, and E0 stages, a fixed failure has occurred in other stages than the C0 stage In this case, the processing can be performed in the same manner as described above.

Next, an operation in which the processing of a subsequent instruction is taken over by another instruction control pipeline when the processing of one instruction is stagnated in one instruction control pipeline, and the operation in which the instruction is stagnated in the C0 stage is described as an example. This will be described below.

As shown in FIG. 7, when instruction 1 and instruction 2 are processed in the instruction control pipeline in that order and instruction 1 is stagnated in the C0 stage, the pipeline control unit 22 performs the following control. Do. First, the succeeding instruction 2 checks whether there is no reason to stop other than the fact that the preceding instruction 1 has stopped, and if so, the processing can be taken over to the other instruction control pipeline. Investigate whether or not. In this investigation, in this case, the condition that the other instruction does not exist in the C1 stage and the instruction of the B1 stage does not flow to the C1 stage when the corresponding BUSY flag and the HOLD flag are seen through the signal line 1722 is satisfied. It is performed depending on whether or not.
In the example of FIG. 7, since no instruction flows in the instruction control pipeline for taking over the processing, it is determined that the takeover is possible.
The pipeline control unit 22 switches the selector 42 at the entrance of the C1 stage to the signal line 309 side by the signal line 227, and transfers the instruction control information of the instruction register 3 of the B0 stage to the C1 stage through the signal line 309 as shown in FIG. To the instruction register 9. The timing is shifted to the C1 stage at a timing as shown in FIG. Thereafter, the instruction 2 is sent through the C1, D1, and E1 stages.

In the example of FIG. 7, it is assumed that no instruction is flowing through the other instruction control pipeline, but when an instruction is flowing, the following control is performed. That is, as shown in FIG. 9, when another instruction 3 flows from the B1 stage to the C1 stage at the timing of moving the instruction 2 of the B0 stage to the C1 stage, the pipeline control unit 22 avoids a collision at the C1 stage. Therefore, the instruction 2 is kept in the B0 stage until a timing at which the instruction 2 does not conflict with the C1 stage, and is moved to the C1 stage at a timing when the movement becomes possible.

By performing the above operation, the processing of the instruction following the stalled instruction can be immediately taken over by another instruction control pipeline. However, according to the conventional instruction control device which does not perform the control for taking over the instruction 2 to another instruction control pipeline, that is, according to the conventional instruction control device having no signal line from the stage B0 to the stage C1, as shown in FIG. The instruction 2 must stay in the B0 stage until the instruction 1 disappears from the C0 stage. Therefore, the issuance of the instruction 2 is at a timing, and compared with the embodiment of FIG.
Instruction issuance is delayed.

Although the above description is for the case where the instruction is stagnant in the C0 stage, the signal lines 208, 410,
The instruction control information of the A0 stage, C0 stage and D0 stage can be transferred to the B1 stage, D1 stage and E1 stage by 511, and the A1 stage by the signal lines 703, 804, 905 and 106.
B1 stage, C1 stage, D1 stage instruction control information to B0
Since the instruction can be transferred to the stage, C0 stage, D0 stage, and E0 stage, even when the instruction is stagnated in a stage other than the C0 stage, the same processing as described above can be performed.

〔The invention's effect〕

As described above, according to the present invention, the instruction control information held in the same stage of another instruction control pipeline or the preceding stage thereof is quickly transferred to a certain stage of a certain instruction control pipeline. There is an effect that can be. Therefore, for example, when a fixed fault occurs in a certain instruction control pipeline, or when there is a subsequent instruction meaninglessly waited by a preceding instruction, the instruction control information is promptly transferred to another instruction control pipeline. By taking over the process, it is possible to avoid the effects of the fixed failure and prevent delay of instruction issuance, and it is possible to further improve the performance of an instruction control device having a plurality of instruction control pipelines of the same type.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIGS. 2 and 3 show arbitration operations to avoid issuing instructions to the scalar operation unit 24 at the same timing in the final stages E0 and E1. Time chart, FIG. 4 is a time chart when another instruction control pipeline takes over processing when a fixed failure occurs, and FIG. 5 is a time chart when another instruction control pipeline takes over processing when a fixed failure occurs. FIG. 6 is another time chart when another instruction control pipeline takes over the processing when a fixed failure occurs. FIG. 7 shows another processing of the instruction following the stalled preceding instruction. FIG. 8 is a time chart when the instruction control pipeline is taken over, and FIG. 8 is an operation explanatory diagram when the processing of the instruction following the stalled preceding instruction is taken over by another instruction control pipeline; The figure is stagnant Time chart when the processing of the instruction following the preceding instruction is taken over by another instruction control pipeline, and FIG. 10 shows the time when the instruction following the stalled preceding instruction is kept waiting. It is a chart. In the figure, 1 ... instruction fetch unit 2-11 ... instruction register 12a-21a ... BUSY flag 12b-21b ... HOLD flag 22 ... pipeline control unit 23 ... instruction issue arbitration unit 24 ... scalar operation unit 25-34 ... fault detection circuit 207, 208, 308, 309, 409, 410, 510, 511, 611 ... signal lines for transferring information between corresponding stages of different instruction control pipelines 702, 703, 803, 804, 904, 905, 105, 106 ... signal lines for transferring information of stages preceding the corresponding stages to different instruction control pipeline stages

Claims (3)

(57) [Claims] A plurality of instruction control pipelines having the same configuration are provided which divide a process from decoding of an instruction fetched by an instruction fetch unit to an operation instruction to a scalar operation unit into a plurality of stages and execute them in parallel. In the instruction control device, an instruction register of a first stage of a first instruction control pipeline may include a stage corresponding to the first stage in a second instruction control pipeline different from the first instruction control pipeline. An instruction control pipeline structure comprising a signal line for transferring instruction control information held in an instruction register of a preceding stage. A plurality of instruction control pipelines having the same configuration for dividing a process from decoding of an instruction fetched by an instruction fetch unit to an operation instruction to a scalar operation unit into a plurality of stages and executing the divided stages in parallel; In the instruction control device, an instruction register of a first stage of a first instruction control pipeline may include a stage corresponding to the first stage in a second instruction control pipeline different from the first instruction control pipeline. An instruction control pipeline structure comprising a signal line for transferring instruction control information held in an instruction register. 3. A plurality of instruction control pipelines having the same configuration, wherein processing from decoding of an instruction fetched by an instruction fetch unit to an operation instruction to a scalar operation unit is divided into a plurality of stages and executed in parallel. In the instruction control device, an instruction register of a first stage of a first instruction control pipeline may include a stage corresponding to the first stage in a second instruction control pipeline different from the first instruction control pipeline. A signal line for transferring instruction control information held in an instruction register of a preceding stage; and an instruction register of a stage corresponding to the first stage in the second instruction control pipeline to the instruction register of the first stage. And a signal line for transferring the instruction control information held in the instruction control pipeline.