JP3281008B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a data rewritable semiconductor memory device suitable for use in, for example, the field of non-volatile memory. In recent years, in the field of non-volatile memory, data can be rewritten by electrically erasing data, for example, an electrically erasable programmable (EEPROM).
Many semiconductor memory devices such as an Able Read Only Memory have been developed.

[0002] This is a nonvolatile memory which can be rewritten by electrically erasing predetermined data which has been written in advance. Such a non-volatile memory achieves a large capacity and low cost in consideration of use by replacing a medium such as a magnetic storage device, and has a low cost in consideration of use in a portable information processing terminal. Voltage is required.

[0003]

2. Description of the Related Art Conventionally, as a semiconductor memory device which is a nonvolatile memory which can be rewritten by erasing predetermined data written in advance, for example, an EPROM
(Erasable Programmable Read Only Memory) or EEP
ROMs and the like are known. However, the EPROM has the advantage of a small cell size, but the use of ultraviolet rays for data erasure makes data erasure troublesome.
PROMs can erase data easily because they can electrically erase data, but have the problem that it is difficult to increase the capacity due to the large cell size compared to EPROMs.

Therefore, a semiconductor memory device called, for example, a FLASH memory, which has the advantages of these memories, has been developed. FIG. 4 is a sectional view of the most typical cell in the FLASH memory. In the figure, CG is a control gate, FG is a floating gate, D is N ⁺
D is a drain, S is an N ⁺ -type source, and PS is a P-type substrate.

FIG. 5 is a circuit diagram showing a cell matrix configuration of the FLASH memory shown in FIG. In the figure, C is the memory cell, WL _x denotes a word line, BL _x bit line, SL _x
Indicates a select line. (However, _x indicates _i , _j , _a , _m , _n in the figure) Next, the operation will be described.

First, when writing to memory cell C,
Indicates that the control gate CG and the drain D have a high potential.
Voltage V_PPIs applied, and the drain is applied in the same manner as in the EPROM.
Floating due to avalanche injection near in-D
When electrons are injected into the gate FG, the memory cell C is cut off.
Is When erasing, the drain D is floated.
The source S has a high potential voltage V _PPIs applied and the flow
With the removal of electrons from the operating gate FG,
The written data is erased.

The potential levels of the control gate CG, drain D, source S, and substrate PS in the above-described operating state are set to values as shown in Table 1.

[0008]

[Table 1]

[0009]

However, such a conventional semiconductor memory device has a configuration in which written data is erased by extracting electrons from the floating gate FG. There was a problem as described above. That is, if too many electrons are extracted during erasing, excessive erasing occurs, and there is a problem that a non-selected memory cell causes a leak current to flow.

Therefore, in order to prevent excessive erasure, it is necessary to perform complicated control such that electrons must be extracted from the floating gate FG little by little at the time of erasure to perform a read check. Further, with the increase in the storage capacity of the semiconductor memory device, it is necessary to prevent process variations, that is, variations in individual memory cells, which makes the manufacturing itself difficult.

Further, the test time of the semiconductor memory device becomes enormous. Therefore, it is conceivable to add a selection transistor like an EEPROM. However, in this case, the addition of the selection transistor causes a new problem that the cell size is increased, which is not practical. [Object] It is an object of the present invention to provide a semiconductor memory device that suppresses an adverse effect due to excessive erasure while suppressing an increase in cell size.

[0012]

In order to achieve the above object, a semiconductor memory device according to the present invention provides an electrically erasable semiconductor device.
In a storage device, a predetermined number of messages on the same word line
A plurality of memory cell groups are formed with a memory cell as one unit,
Gate connected to the word line for each of a plurality of memory cell groups
Forming a plurality of MOS transistors,
Connecting the source of each memory cell in each cell group
In both cases, the sources are shared via the MOS transistor.
It is configured to connect to a communication source . Where
A plurality of memory cell groups including MOS transistors
Formed in a cell and previously written in the plurality of memory cell groups.
The specified data, and apply a negative potential voltage to the word line.
Adding and erasing is preferable.

In addition, the above-mentioned MOS transistor includes the above- mentioned MOS transistor.
Preferably well to form a plurality of memory cell groups which are divided into at least two or more, if you erase a predetermined data written in advance in the plurality of memory cell groups, the well and substrate the same potential It is effective to do.

[0014]

According to the present invention, a MOS transistor in which a word line of a memory cell group is connected to a gate is provided.
Since the S transistor and the source of each memory cell in the memory cell group are connected in common, and only the selected memory cell group is connected to the source at the time of reading data, the non-selected memory cell group Even if an over-erased cell exists, the source of the unselected memory cell group is cut off, so that the influence of the over-erased cell is suppressed.

Further, complicated control for erasing is not required, and since one MOS transistor is added to one memory cell group, the cell area is almost the same as that of the conventional one. That is, adverse effects due to excessive erasure are prevented, and an increase in cell size at that time is also suppressed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 3 are views showing one embodiment of a semiconductor memory device according to the present invention. First, the configuration will be described. In FIGS. 1 to 3, the same reference numerals as those of the conventional example shown in FIGS.

FIG. 1 is a cross-sectional view of a memory cell according to the present embodiment. In the figure, G is the gate of a MOS transistor T, CS is an N ⁺ type common source, PW is a P type well, and NS is an N type. It is a substrate. FIG. 2 is a plan view showing a configuration of a main part of the present embodiment. In the drawing, CW is a contact window, WL is a word line made of polysilicon, BL is an aluminum wiring bit line, CS
Is a common source made of aluminum wiring, S is a source made of a diffusion layer, and FG is a floating gate.

FIG. 3 is an equivalent circuit diagram of FIG.
B denotes a memory cell group, which is composed of one byte, that is, an 8-bit memory cell C, and one MOS transistor T. Next, the operation will be described. In this embodiment, as shown in Table 2, the word line WL selected at the time of reading the high-potential voltage V _CC (in this case, 5V) by being a state in which electrons in the floating gate FG is injected (Writing In this state, the data is cut off, and in the state where electrons are extracted (erased state), the data is turned on, thereby detecting "L" and "H" of data.

[0019]

[Table 2]

Here, since only the source of the selected memory cell group CB is set to the potential of 0 V, even if a leak exists in the unselected memory cell group CB, the MOS transistor (source transistor) T Since it is cut off , the leakage current path is
The memory cell selected from among the non-selected memory cell groups CB
That occurs only in some memory cells adjacent to the memory group CB
Therefore, the leak current can be substantially ignored . At the time of writing, like a normal EPROM, a high potential voltage V _PP (in this case, 12V) to the word line WL with is applied, to the bit line BL high level voltage V _PP (in this case, 12
The application of V) causes avalanche breakdown, and electrons are injected into the floating gate FG.

[0021] At the time of erasing, a negative high potential voltage -V _PP (in this case, -7V) to the word line WL by tunneling over from the floating gate FG to the wells PW side by is applied, electrons are extracted . this is,
In the configuration of this embodiment, since a high potential voltage cannot be applied to the common source CS during erasing, electrons are emitted from the floating gate FG to the substrate NS by applying a negative high potential voltage to the gate. It is.

Here, by raising the potential of the well PW to V _CC (5 V in this case), which is the same potential as the substrate NS, the electric field can be increased and the erase time can be shortened. As described above, in the present embodiment, the problem of excessive erasure can be avoided by adding one MOS transistor to a memory cell group having a predetermined number of bits. Therefore, even if the capacity is increased, the same area as that of the conventional cell can be realized, and excessive erasure due to process variation can be prevented.

In the above embodiment, the number of memory cells in the memory cell group commonly connected to the source is 8 bits, that is, in units of 1 byte. However, the present invention is not limited to this. Needless to say, the unit is arbitrary as a unit suitable for the processing system.

[0024]

According to the present invention, a MOS transistor in which a word line of a memory cell group is connected to a gate is provided.
Memory cells commonly connected via an OS transistor
Connect each source of each memory cell in the group to a common source ,
At the time of data reading, only the selected memory cell group is connected to the source, so even if an over-erased cell exists in the unselected memory cell group, the source of the unselected memory cell group is disconnected. In addition, the influence of the over-erased cells can be suppressed.

Further, complicated control for erasing is not required, and the number of added MOS transistors is one for each memory cell group, so that the cell area is almost the same as that of the conventional one. Therefore, adverse effects due to excessive erasure can be prevented, and an increase in cell size at that time can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a memory cell of a semiconductor memory device of the present invention.

FIG. 2 is a plan view illustrating a main configuration of the present embodiment.

FIG. 3 is an equivalent circuit diagram of FIG.

FIG. 4 is a sectional view of a memory cell in a conventional FLASH memory.

FIG. 5 is a circuit diagram showing a cell matrix configuration of a conventional flash memory.

[Explanation of symbols]

CG control gate FG floating gate D drain S source PS P-type substrate C memory cell WL _x word line BL _x bit line SL _x select line CS common source G gate WL word line BL bit line PW P-type well NS N-type substrate CW contact Window CB memory cell group

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (4)

(57) [Claims] 1. An electrically erasable semiconductor memory device.
A predetermined number of memory cells on the same word line
To form a plurality of memory cell groups, and a gate is connected to the word line in each of the plurality of memory cell groups.
Connected MOS transistors are formed, and in each of the plurality of memory cell groups, the source of each memory cell is formed.
Source, and the source is connected to the MOS transistor.
A semiconductor memory device connected to a common source via a resistor . 2. The plurality of MOS transistors including the MOS transistors.
A memory cell group is formed in the well, and the plurality of memory cells are formed.
The predetermined data written in advance to the word group is
2. The semiconductor memory device according to claim 1, wherein a negative potential voltage is applied to said memory cell for erasing . 3. The plurality of MOS transistors including the MOS transistors.
The wells forming the memory cell group are divided into at least two or more.
3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is divided. 4. The method according to claim 1, wherein said plurality of memory cell groups are written in advance.
When erasing predetermined data, the well is set at the substrate potential.
4. The electric potential as set forth in claim 2, wherein:
Semiconductor storage device.