JP3279011B2 - Arrangement method of circuit blocks in semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a semiconductor integrated circuit, in particular method of arranging the circuit blocks in a semiconductor integrated circuit having at least one circuit block configured using the basic cell of a gate array formed on a chip About.

[0002]

2. Description of the Related Art A gate array has an NA on an LSI chip.
Basic cells corresponding to logic gates such as ND and NOR are arranged in a grid pattern, and the aim is to simplify the design with a regular structure. In other words, the use of a gate array allows the design to proceed while expressing all logic using a limited number of basic cells.
Both logical design and layout design become simple. In addition, as for the wiring design between basic cells, various LSIs can be created only by generating a mask pattern related to the wiring, so that it is suitable for manufacturing a large number of small-quantity LSIs in a short time and at low cost. ing.

Conventionally, a desired LSI has been manufactured using a gate array.
Has been arranged mainly in terms of wiring layout efficiency. Here, a circuit block refers to a logical function unit such as a memory area, an A / D converter, a shift register, or a counter. As described above, when considering the arrangement of circuit blocks from the viewpoint of wiring layout efficiency, circuit blocks with high power consumption may be unevenly arranged on an LSI chip.

[0004]

In a semiconductor integrated circuit using a gate array, as shown in FIG. 2, each power supply line of V _DD / V _SS has, for example, a two-layer structure (1 in FIG. 1). Layers are alternately arranged in a mesh shape by alternate long and short dash lines, and the second layer is alternately arranged in a mesh shape by alternate long and two short dashes lines, and each main power supply line of V _DD / V _SS arranged in the periphery of the chip 10 (in the figure). Current is supplied from the main power supply lines 11 and 12 of V _DD / V _SS to the circuit block 13 disposed on the chip 10 through the respective power supply lines in a mesh form. It has become so.

Therefore, as described above, since the circuit blocks of high power consumption are unevenly distributed on the chip, the number of power supply lines that can supply current to the circuit blocks of high power consumption among the mesh-like power supply lines is limited. Will be done. For example, assuming that the high power consumption circuit block 13 is disposed in the middle of the upper side of the chip 10 as shown by a broken line in FIG.
Therefore, the current is mainly supplied from the main power supply line on the upper side by the respective power supply lines in the middle part of the second layer.

In such a case, the current flowing through each power supply line for supplying current to the circuit block 13 with high power consumption increases, and the electromigration (E
M) The standard may not be satisfied. Here, the term “electro-migration” refers to a phenomenon in which metal atoms move by an electric current. Particularly, in the case of an IC having a large current density, the life is determined to some extent by the electromigration of wiring. The limit current density is about 10 ⁵ A / cm ^{2 in} the case of aluminum (Al) wiring.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to suppress an increase in the current density of a power supply line due to uneven distribution of high power consumption circuit blocks on a chip. and to provide a method of arranging the circuit blocks in a semiconductor integrated circuit adapted to satisfy the criteria.

[0008]

A method of arranging circuit blocks according to the present invention includes at least one circuit block configured using a basic cell of a gate array formed on a chip. On the other hand, in a semiconductor integrated circuit for supplying a current from a main power supply line arranged on the periphery of a chip through a power supply line arranged in a mesh shape with at least a two-layer structure, a first-layer power supply line and a second-layer power supply The ratio of the resistance value per unit length of the line is set to a predetermined resistance ratio, and the arrangement of at least one circuit block on the chip is determined based on the resistance ratio.

[0009]

In the method of arranging circuit blocks in a semiconductor integrated circuit , first, the ratio of the resistance value per unit length between the power supply line of the first layer and the power supply line of the second layer is set to a predetermined resistance ratio. The resistance ratio determines a position on the chip where a substantially uniform current can be supplied to the circuit block from at least two main power supply lines. Therefore, by determining the arrangement of the circuit blocks on the chip based on the resistance ratio, it is possible to supply a substantially uniform current to the circuit blocks from at least two main power supply lines.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a flowchart showing a procedure of a method for arranging circuit blocks according to the present invention. In a semiconductor integrated circuit using the gate array to which the present invention is applied, in the two-layer wiring structure shown in FIG. 2, as a wiring material of each power supply line of the V _DD / V _SS, 1-layer and 2-layer co ,
It is assumed that aluminum (Al) is used. In FIG. 1, first, the ratio of the resistance value per unit length between the power supply line of the first layer and the power supply line of the second layer is set to a predetermined resistance ratio (step S1). Next, based on the resistance ratio, an arrangement of the circuit block 13 indicated by a broken line in FIG. 2 on the chip 10 is determined (step S2).

Here, when the resistance per unit length of the aluminum wiring (1AL) of the first layer and the aluminum wiring (2AL) of the second layer are substantially equal, that is, when the resistance ratio is approximately 1: 1, The current distribution bias due to the difference in the current consumption of the circuit blocks and the variation in their arrangement distribution is considered. As an example, on a 1.3K gate scale, as shown in FIG. 3, a current is weighted for each of the 36 gates, and the V _DD / V _SS of the chip peripheral portion is set using the arrangement distribution on the chip as a parameter. The current flowing from each power supply line shall be calculated.

In FIG. 3, within one cell (for 36 gates)
Then, the magnitude of the current source I is fixed (for example, 19.7
[A. u. ], And the total current between the cells is weighted. In this example, the total weighting is 36 (constant). Here, [a. u. ] Means any unit (a
rbitrary unit). Here, the reason why it is set to 36 (constant) is that the total amount is obtained when all 36 squares (1 square and 36 gates) are uniform (1 square weight 1).

First, as shown in FIG.
Consider the case where the high current cells are concentrated on the area No. 4. In this case, the weight of the hatched portion is 3.1, and the other weights are 0.3.
And As a result, the weight of the current value in the hatched portion is 61.0.
7 [a. u. ] (= 19.7 [au] .times.3.1),
The weight of the other current values is 5.91 [a. u. ] (= 1
9.7 [a. u. ] × 0.3).

When the high current cells are concentrated at the corner where the side C and the side D intersect (A), the current distribution on each side A to D is as shown in FIG. At this time, the maximum current on the side A is 6.120.
[A. u. ], The maximum current on the side B is 6.511 [a.
u. ], The maximum current on the side C is 2.277 × 10 [a.
u. ], The maximum current on the side D is 2.362 × 10 [a.
u. ].

When the high current cells are concentrated substantially at the center of the chip (B), the current distribution on each side A to D is as shown in FIG. At this time, the maximum current on the side A is 1.023 × 10
[A. u. ], The maximum current on the side B is 1.088 × 10
[A. u. ], The maximum current on the C side is 1.559 × 10
[A. u. ], The maximum current on the D side is 1.641 × 10
[A. u. ].

When the high current cells are concentrated substantially at the center of the side C (C), the current distribution on each side A to D is as shown in FIG. At this time, the maximum current on the side A is 6.964 [a.
u. ], The maximum current on the side B is 9.282 [a. u. ], C
The maximum current on the side is 2.516 × 10 [a. u. ], The maximum current on the D side is 1.418 × 10 [a. u. ].

Next, as shown in FIG.
Consider a case where high-current cells are concentrated at 9 (high-current regions are further concentrated than in FIG. 4). In this case, the weight of the hatched portion is 6.6, and the other weights are 0.
3 is assumed. As a result, the weight of the current value in the hatched portion is 13
0.02 [a. u. ] (= 19.7 [au] .times.6.
6), the weight of the other current values is 5.91 [a. u. ]
(= 19.7 [au] .times.0.3).

When the high current cells are concentrated at the corner where the C side and the D side intersect (A), the current distribution on each side A to D is as shown in FIG. At this time, the maximum current on the side A is 4.741.
[A. u. ], The maximum current on the side B is 5.001 [a.
u. ], The maximum current on the side C is 3.152 × 10 [a.
u. ], The maximum current on the D side is 3.276 × 10 [a.
u. ].

When the high current cell moves to the center of the side C (B), the current distribution on each side A to D is as shown in FIG. At this time, the maximum current on the side A is 5.548 [a.
u. ], The maximum current on the side B is 6.693 [a. u. ], C
The maximum current on the side is 3.656 × 10 [a. u. ], The maximum current on the D side is 1.589 × 10 [a. u. ].

When the high current cells are concentrated at the center of the side C (C), the current distribution on each side A to D is as shown in FIG. At this time, the maximum current on the side A is 5.819 [a.
u. ], The maximum current on the side B is 9.541 [a. u. ], C
The maximum current on the side is 3.742 × 10 [a. u. ], The maximum current on the D side is 9.541 [a. u. ].

Note that all the gates are all current uniform (weight 1).
In the case of, the maximum current on the sides A and C is 1.142 ×
10 [a. u. ], And its current density is 2.284 [a.
u. ], The maximum current of the side B and the side D is 1.185 × 10
[A. u. ].

FIG. 12 is a schematic diagram qualitatively showing the above results. In the same figure, “⇒” represents a large current, and “→” represents a current larger than other parts but smaller than “⇒”. FIG.
The case where the high current cells are concentrated at the corners of the chip as in the case of FIG. 8A and the case where the cells are concentrated at the center of one side of the chip as in the case of FIG. Each is shown.

When the chip is concentrated at the corner of the chip (a),
A large current (⇒) can be supplied mainly from two main power supply lines. On the other hand, when the current is concentrated at the center of one side (b), a large current (⇒) can be mainly supplied only from the main power supply line of one side, so that the value becomes large.

FIG. 12B shows the case where the high current cells are concentrated at the corners of the chip as in the case of FIG.
FIG. 4B shows a case where the chip is concentrated substantially at the center of the chip as in the case of FIG. Since the current supply path increases in the case (b) concentrated at the approximate center of the chip as compared with the case (a) concentrated in the corner of the chip, each V _DD
The current flowing through the power supply line is reduced.

FIG. 12C shows the case where the concentration of the high current cells is small (a) as in the case of FIG.
(B) shows a case where the degree of concentration is large as in (A). When the concentration is high, the current supply path decreases in the case (b), and the current flowing through each _VDD power supply line increases.

As is clear from the above, the magnitude of the current density when the high current cells are concentrated at the center of one side is i ₁ , the magnitude of the current density when the high current cells are concentrated at the corner is i ₂ , and the center of the chip is the magnitude of the current density in the case of centralized when i _3, the
i ₁ > i ₂ > i ₃ and the high power consumption circuit block
It can be seen that it is better to arrange at the center of the chip than at the end of the chip. In addition, even when the current density is concentrated on one side, the current density becomes higher toward the center than the end of the side.

That is, the high power consumption circuit block 13
In FIG. 13, the current density increases in the direction of the arrow from the center of the chip 10. Further, it is better to dispose the circuit blocks 13 with high power consumption in a distributed manner. Electro-migration (E) is the most extreme when dispersed, that is, when all gates are uniform.
M) is good.

Based on the above simulation results, in the present embodiment, when a circuit block is formed using basic cells of a gate array formed on a chip, the first layer of aluminum wiring is arranged when the circuit block is arranged. And 2
When the resistance value per unit length of the aluminum wiring of the layer is substantially equal, the circuit block 13 of high power consumption
As shown in the figure, the chip 10 is arranged at the center.

As described above, the high power consumption circuit block 1
By arranging 3 at the center of the chip 10, current can be supplied to the circuit block 13 from the main power supply lines on the four sides of the chip 10, so that the current supply path is maximized. As a result, the current flowing through each power supply line of V _DD / V _SS can be reduced to the maximum, and the electro-migration standard can be sufficiently satisfied.

If a circuit block with high power consumption cannot be arranged at the center of the chip due to the wiring layout or the like, the circuit block is arranged on the diagonal line of the chip or in the vicinity thereof as shown by a broken line in FIG. . In this way, by arranging the high power consumption circuit block on or near the diagonal line of the chip, the current can be supplied to the block from at least two sides, and the current supply path is smaller than when supplying from one side. Increase. Therefore, the current flowing through each power supply line of V _DD / V _SS can be reduced.

In particular, even on the diagonal line of the chip or in the vicinity thereof, as shown in FIG. 14, the current density of each power supply line of V _DD / V _SS becomes smaller in the direction of the arrow, that is, in the center of the chip. The degree to which the standard can be satisfied is increased. When there are a plurality of circuit blocks with high power consumption, the circuit block having the largest power consumption among the plurality of circuit blocks is arranged at the center of the chip, and the remaining circuit blocks are dispersed. It is arranged on the diagonal line of the chip or in the vicinity thereof.

For example, as shown in FIG. 15A, when there are five circuit blocks, the circuit block having the largest power consumption is arranged at the center of the chip, and the remaining four circuit blocks are arranged. Are uniformly dispersed. Also,
When there are three circuit blocks, as shown in FIG. 15B, the circuit block having the largest power consumption is arranged at the center of the chip, and the remaining two circuit blocks are arranged at the central circuit, for example. Arrange them at equal intervals across the block. However, in this case, it is not always necessary to arrange the remaining two circuit blocks with the central circuit block interposed therebetween, and as shown by a broken line in FIG. Just do it.

As described above, when a plurality of circuit blocks having different power consumptions are provided, the circuit block having the largest power consumption is arranged substantially at the center of the chip, and the remaining circuit blocks are arranged on the chip. By arranging them on a diagonal line or in the vicinity of the diagonal lines, it is possible to supply a substantially uniform current from the four main power supply lines to the circuit block having the largest power consumption, and to supply at least two main power supply lines to the other circuit blocks. A substantially uniform current can be supplied from the line.

As described above, the first-layer power supply line
If the resistance value per unit length of the power supply line of the layer is almost equal, the best position for arranging the circuit block is
It is almost in the center of the chip. By arranging the circuit blocks in the center of the chip, the wiring resistance of the first layer from the left and right sides of the chip to the center of the chip (indicated by X in FIG. 16) is R1, and the chip resistance is from the upper and lower sides of the chip. If the wiring resistance of the second layer up to the center is R2, then R1 = R2, so that a substantially uniform current can be supplied from the four main power supply lines to the circuit block arranged in the center of the chip. .

This maximizes the path of current supply to the circuit block arranged in the center of the chip. as a result,
Since the current flowing through each of the mesh-shaped power supply lines for supplying the current to the circuit block disposed in the center of the chip can be reduced to the maximum, the electro-migration standard can be sufficiently satisfied.

Next, a case where the resistance value per unit length of the power supply line of the first layer and the power supply line of the second layer are different will be described. First, consider a case where the ratio of the resistance value per unit length between the power supply line of the first layer and the power supply line of the second layer is 2: 1. In this case, the best positions for arranging the circuit blocks are the positions indicated by the crosses in FIG. 17, that is, the positions near the center between the chip center and the right side of the chip and the positions symmetrical to the crosses.

For the circuit block arranged at the position indicated by the mark x in FIG. 17, the resistance of the first layer from the left side of the chip to the mark x is R11, and the wiring resistance of the first layer from the right side of the chip to the mark x is set. The resistance is R1, 2 from the upper and lower sides of the chip to the X mark.
Assuming that the wiring resistance of the layer is R2, R1 = R2 <R11, so that a substantially uniform current can be supplied from the main power supply lines on the three sides of the chip to the circuit blocks arranged at the positions indicated by the crosses.

Next, consider a case where the ratio of the resistance value per unit length between the power supply line of the first layer and the power supply line of the second layer is 3: 1. In this case, the best position for arranging the circuit blocks is the position indicated by the mark x in FIG. 18, that is, the position inside the right side of the chip by a distance of 1/3 of the distance between the center of the chip and the right side of the chip, and There are two locations symmetrical to the mark.

As for the circuit blocks arranged at the positions indicated by the crosses in FIG. 18, the wiring resistance of the first layer from the left side of the chip to the crosses is R11, and the cross resistance from the right side of the chip is the same as in the above case. Assuming that the wiring resistance of the first layer up to R1 is R1, and the wiring resistance of the second layer from the upper and lower sides of the chip to the mark x is R2,
Since R1 = R2 <R11, a substantially uniform current can be supplied to the circuit blocks arranged at the positions indicated by the crosses from the main power supply lines on the three sides of the chip.

As described above, when the resistance value per unit length of the power supply line of the first layer and the power supply line of the second layer are different,
The best positions for arranging the circuit blocks are two places, and it is possible to supply substantially uniform current to the circuit blocks arranged at those positions from the main power supply lines on the three sides of the chip. However, as is clear from the characteristic diagram of FIG. 19, when the resistance value per unit length of the power supply line of the first layer and the power supply line of the second layer are different, the number of main current supply paths is reduced by one. First, since the load on one current supply path increases, the maximum current flowing through the power supply line increases.

As described above, the arrangement of the circuit blocks capable of supplying a substantially uniform current from the main power supply lines on the three sides of the chip is such that the resistance value per unit length of the power supply line of the first layer and the power supply line of the second layer is small. It can be realized even in almost the same case. In this case, the resistance ratio is 2: 1 as shown in FIG.
In the case of (1), the best positions are two as shown in FIG. 7B, whereas the positions where the maximum current flowing through the power supply line is the same are four. Therefore, considering the ease of design, it is more desirable that the power supply line of the first layer and the power supply line of the second layer have substantially the same resistance value per unit length.

The setting of the resistance ratio between the power supply line of the first layer and the power supply line of the second layer can be easily realized by changing the wiring material of each layer. In the above embodiment, the case where the power supply line has a two-layer structure has been described. However, the present invention can be applied to, for example, a three-layer structure in which a bypass wiring is arranged in a third layer. The combined resistance of the wiring resistances of the first and third layers may be treated as the wiring resistance of the first layer.

[0044]

As described above , according to the present invention ,
The ratio of the resistance value per unit length between the power supply line of the first layer and the power supply line of the second layer is set to a predetermined resistance ratio, and the arrangement of the circuit blocks on the chip is determined based on this resistance ratio. This makes it possible to determine a position on the chip where substantially equal current can be supplied from the main power supply lines on at least two sides to the circuit block, so that the current flowing through each of the mesh-like power supply lines can be reduced, and the electromigration standard can be reduced. Can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure of a method of arranging circuit blocks according to the present invention.

FIG. 2 is a pattern diagram showing wiring of a power supply line having a two-layer structure.

FIG. 3 is a diagram showing a state in which a chip is divided into 36 and an equivalent circuit in each cell.

FIG. 4 is a diagram showing each state when high current cells are concentrated on a quarter of the total gate;

FIG. 5 is a characteristic diagram when a high current cell is concentrated at a corner of a chip.

FIG. 6 is a characteristic diagram when a high current cell is concentrated substantially at the center of a chip.

FIG. 7 is a characteristic diagram when a high current cell is concentrated substantially at the center of one side of a chip.

FIG. 8 is a diagram showing each state when high current cells are concentrated on 1/9 of the total gate.

FIG. 9 is a characteristic diagram when a high current cell is concentrated at a corner of a chip.

FIG. 10 is a characteristic diagram when the high current cell moves to the center of one side of the chip.

FIG. 11 is a characteristic diagram when a high current cell is concentrated at the center of one side of a chip.

FIG. 12 is a schematic diagram qualitatively showing a simulation result.

FIG. 13 is a diagram for explaining a relationship between a position of a circuit block on a chip and an increase in current density.

FIG. 14 is a diagram showing the best position of a circuit block on a chip when the resistance ratio is 1: 1.

FIG. 15 is a diagram showing a preferred position when a plurality of circuit blocks exist.

FIG. 16 is a diagram for explaining the grounds of the best position when the resistance ratio is 1: 1.

FIG. 17 is a diagram for explaining the grounds of the best position when the resistance ratio is 2: 1.

FIG. 18 is a diagram for explaining the grounds of the best position when the resistance ratio is 3: 1.

FIG. 19 is a characteristic diagram illustrating a relationship between a resistance ratio and a maximum current value at each position on a chip of a circuit block.

FIG. 20 is a diagram showing a positional relationship between circuit blocks when the resistance ratio is 1: 1 (A) and when the resistance ratio is 2: 1 (B).

[Explanation of symbols]

10 ... chip, 11 ... V _DD mains supply line, 12 ... V _SS main power supply line, 13 ... circuit block

Claims (1)

(57) [Claims] 1. A power supply having at least one circuit block formed by using a basic cell of a gate array formed on a chip, and having at least a two-layer structure with respect to this circuit block in a mesh form. In a semiconductor integrated circuit for supplying current from a main power supply line arranged on a peripheral portion of a chip through a line, a ratio of a resistance value per unit length between a first-layer power line and a second-layer power line is determined by a predetermined resistance ratio. And arranging the at least one circuit block on a chip based on the predetermined resistance ratio.