JP3258212B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3258212B2
JP3258212B2 JP22927595A JP22927595A JP3258212B2 JP 3258212 B2 JP3258212 B2 JP 3258212B2 JP 22927595 A JP22927595 A JP 22927595A JP 22927595 A JP22927595 A JP 22927595A JP 3258212 B2 JP3258212 B2 JP 3258212B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
semiconductor
resin member
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22927595A
Other languages
Japanese (ja)
Other versions
JPH0974110A (en
Inventor
稔 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP22927595A priority Critical patent/JP3258212B2/en
Publication of JPH0974110A publication Critical patent/JPH0974110A/en
Application granted granted Critical
Publication of JP3258212B2 publication Critical patent/JP3258212B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Thyristors (AREA)
  • Die Bonding (AREA)
  • Rectifiers (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、電極基体を介し
て半導体素子基体を圧接する構成を備える半導体装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which a semiconductor element base is pressed into contact with an electrode base via an electrode base.

【0002】[0002]

【従来の技術】シリコン制御整流素子(SCR)などい
わゆるサイリスタと称される半導体装置では、大電力の
変換装置として多方面に使用されている。特に大容量を
取扱う半導体装置は、ヒートサイクルに対して熱的歪み
を軽減し長寿命化を図るため、図5に示すような加圧接
触構造が採用されている。
2. Description of the Related Art A semiconductor device called a thyristor such as a silicon controlled rectifier (SCR) is widely used as a high power converter. In particular, a semiconductor device that handles a large capacity employs a pressure contact structure as shown in FIG. 5 in order to reduce thermal distortion with respect to a heat cycle and extend the life.

【0003】即ち、中心のシリコンウェハ等の半導体素
子基体1は、モリブデンあるいはタングステンからなる
緩衝板2を介して、Cuによるカソード電極基体3及び
アノード電極基体4に挟持されるとともに、半導体素子
基体1にはゲート電極配線5が接続されて構成される。
なお、半導体素子基体1に接して左右にセラミック等に
よる放熱フィン6が設けられている。上記半導体素子基
体1、緩衝板2、カソード電極基体3及びアノード電極
基体4のこれら隣接する相互間の各接触電気抵抗、及び
接触熱抵抗が十分小さくなる程度の荷重で、図中上下両
方向から半導体素子基体1面に加圧され、パッケージに
組込まれて使用される。
That is, a semiconductor element substrate 1 such as a central silicon wafer is sandwiched between a cathode electrode substrate 3 and an anode electrode substrate 4 made of Cu via a buffer plate 2 made of molybdenum or tungsten. Is connected to the gate electrode wiring 5.
Heat radiation fins 6 made of ceramic or the like are provided on the left and right in contact with the semiconductor element substrate 1. The semiconductor element base 1, the buffer plate 2, the cathode electrode base 3, and the anode electrode base 4 are loaded from the top and bottom in FIG. It is pressed against the surface of the element substrate 1 and incorporated into a package for use.

【0004】上記従来の半導体装置では、半導体素子基
体1は大電力化に対応するために広面積化されており、
直径60mm以上のものもあり、カソード電極基体3及
びアノード電極基体4間に外側から荷重をかけることに
よって半導体素子基体1の両面を圧接し、放熱特性の向
上を図っている。
In the above-described conventional semiconductor device, the semiconductor element substrate 1 has a large area in order to cope with an increase in power.
Some have a diameter of 60 mm or more. By applying a load between the cathode electrode substrate 3 and the anode electrode substrate 4 from the outside, both surfaces of the semiconductor element substrate 1 are pressed against each other to improve heat radiation characteristics.

【0005】しかしながら、上記のように構成された従
来の半導体装置では、半導体素子基体1を両面から圧接
するのに、図6に示すように、ばね7やボルト8締め等
荷重を加える機構を別途必要とする。
However, in the conventional semiconductor device configured as described above, a mechanism for applying a load such as a spring 7 or a bolt 8 is separately provided for pressing the semiconductor element substrate 1 from both sides, as shown in FIG. I need.

【0006】とりわけ、大電流を制御する場合には、回
路構成上並列接続を採用せざるを得ないから、図6に示
すように、複数(図6では3個)の半導体装置(サイリ
スタ)Aを積み重ね(スタッキング)、4本の支持シャ
フト9に上下に押え板10及び絶縁体11を通し、相互
間に冷却フィン12を介在させて圧接する方法が用いら
れる。
In particular, when controlling a large current, parallel connection must be adopted in terms of the circuit configuration. Therefore, as shown in FIG. 6, a plurality (three in FIG. 6) of semiconductor devices (thyristors) A Are stacked (stacked), a pressing plate 10 and an insulator 11 are vertically passed through four support shafts 9, and a cooling fin 12 is interposed therebetween to press-contact each other.

【0007】これらの荷重を加える機構の付加は、小型
化に適していない上に、装置が大掛かりとなるから半導
体装置組立て時の作業も煩雑なものになるという難点が
あった。また、その場合複数並列配置の各半導体素子基
体1に負荷される圧接応力に偏りが生じた場合は、接触
電気抵抗及び接触熱抵抗が不均一となり回路特性に悪影
響を及ぼすため、複数の半導体素子基体1に均等な圧接
応力を発生させる必要があるが、簡単な構成で均等な圧
接応力を発生させることは容易でなかった。
[0007] The addition of these load applying mechanisms is not suitable for miniaturization, and also has the drawback that the work involved in assembling the semiconductor device becomes complicated because the device becomes large-scale. Further, in this case, when the pressure contact stress applied to each of the plurality of semiconductor element substrates 1 arranged in parallel is biased, the contact electric resistance and the contact thermal resistance become non-uniform and adversely affect the circuit characteristics. It is necessary to generate a uniform pressure contact stress on the base 1, but it was not easy to generate a uniform pressure contact stress with a simple configuration.

【0008】[0008]

【発明が解決しようとする課題】上記のような大電力用
圧接型の半導体装置の問題点、即ち、小型化に不適で複
雑な構造であり、組立て時の作業が煩雑で製造工数が多
くなること、加えて、複数の半導体素子基体1の圧接時
に生じる圧接応力の不均一を生じやすい等の状況に鑑み
てこの発明はなされたものである。
The problem of the above-described high-power press-contact type semiconductor device is that it has a complicated structure which is unsuitable for miniaturization, and the assembly work is complicated and the number of manufacturing steps is increased. In addition, the present invention has been made in view of such a situation that the pressure contact stress generated when the plurality of semiconductor element substrates 1 are pressed is likely to be non-uniform.

【0009】従って、この発明の目的は、圧接力発生機
構をより簡易な構造で実現し、小型化を図り、かつ製造
の容易な大電力用圧接型の半導体装置を提供することに
ある。また、この発明は、複数の半導体素子基体1を同
時に圧接する場合にも容易に対応できる構造とし、接触
電気抵抗、接触熱抵抗の均一性を向上することにある。
Accordingly, it is an object of the present invention to provide a high-power press-contact type semiconductor device which realizes a press-contact force generating mechanism with a simpler structure, is small in size, and is easy to manufacture. Another object of the present invention is to improve the uniformity of the contact electric resistance and the contact thermal resistance by adopting a structure which can easily cope with the case where a plurality of semiconductor element bases 1 are simultaneously pressed.

【0010】[0010]

【課題を解決するための手段】この発明は、電極基体を
介して半導体素子基体を圧接する構造の半導体装置にお
いて、並列に配置された複数個の半導体基体及び前記複
数個の半導体素子基体に対応する複数個の電極基体を囲
み、且つ前記複数個の半導体基体間に介在するように形
成された樹脂部材を備えたことを特徴とする。
SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a structure in which a semiconductor element substrate is pressed into contact with an electrode substrate via a plurality of semiconductor substrates arranged in parallel and a plurality of the semiconductor element substrates. And a resin member formed so as to surround the plurality of electrode substrates and to be interposed between the plurality of semiconductor substrates.

【0011】この発明は、電極基体を介して半導体素子
基体を圧接する構造の半導体装置において、並列に配置
された複数個の半導体基体及び前記複数個の半導体素子
基体に対応する複数個の電極基体を囲み、且つ前記複数
個の半導体基体間に介在するように形成された樹脂部材
を構成したので、樹脂部材の硬化収縮力又は熱収縮力に
より、ばねやボルト締め等の荷重発生機構が不要とな
り、また荷重発生機構は樹脂のみで構成されるために、
製造が容易であり、加えて、半導体装置の製造工程にお
いて、既に樹脂部の硬化収縮力及び熱収縮力により圧接
荷重が発生しているから、半導体装置の組立て時に新た
に荷重を加える作業も不要となる。更に、複数の半導体
基体を平面的に配置して圧接する場合でも、半導体素子
基体を覆う樹脂は、個々の半導体素子基体ごとに独立し
た変形を可能とするので、圧縮応力の均一性を良好に保
つことができる。
According to the present invention, in a semiconductor device having a structure in which a semiconductor element substrate is pressed into contact with an electrode substrate, a plurality of semiconductor substrates arranged in parallel and a plurality of electrode substrates corresponding to the plurality of semiconductor element substrates are provided. And a resin member formed so as to be interposed between the plurality of semiconductor bases, so that a load-generating mechanism such as a spring or a bolt is not required due to the curing shrinkage force or the heat shrinkage force of the resin member. Since the load generating mechanism is made of only resin,
It is easy to manufacture, and in addition, in the semiconductor device manufacturing process, a pressing load is already generated due to the curing shrinkage force and heat shrinkage force of the resin part, so there is no need to add a new load when assembling the semiconductor device Becomes Furthermore, even when a plurality of semiconductor substrates are arranged and pressed against each other, the resin covering the semiconductor element substrates can be deformed independently for each semiconductor element substrate, so that the uniformity of the compressive stress can be improved. Can be kept.

【0012】[0012]

【発明の実施の形態】以下、この発明による半導体装置
の一実施の形態を図面を参照して詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention will be described below in detail with reference to the drawings.

【0013】図1(a)はこの発明による半導体装置の
第一の実施の形態を示す断面図、図1(b)は上面図で
ある。即ち、シリコンウェハ等の半導体素子基体1を、
モリブデンあるいはタングステンからなる緩衝板2を介
して、カソード電極基体3及びアノード電極基体4で挟
んだ後、カソード電極基体3及びアノード電極基体4の
一部を露出させた状態で全体を外部樹脂層を形成した樹
脂部材13で取り囲み、高温中で樹脂部材13を硬化さ
せる。樹脂部材13としては、硬化収縮率が約0.2
%、線膨張率が少なくとも室温で約16×10-6/℃ま
たガラス転移温度以上の高温で約60×10-6/℃のエ
ポキシ系封止樹脂が使用される。このように、樹脂部材
7は硬化収縮率及び線膨脹率がいずれも高く、加えて、
常温での剛性が高い材料からなるので、製造時の樹脂硬
化工程を終えたのちは、半導体素子基体1に対し強い圧
接応力が働く。
FIG. 1A is a sectional view showing a first embodiment of a semiconductor device according to the present invention, and FIG. 1B is a top view. That is, the semiconductor element substrate 1 such as a silicon wafer is
After being sandwiched between the cathode electrode substrate 3 and the anode electrode substrate 4 via the buffer plate 2 made of molybdenum or tungsten, the entire external resin layer is formed with the cathode electrode substrate 3 and the anode electrode substrate 4 partially exposed. The resin member 13 is surrounded by the formed resin member 13 and is cured at a high temperature. The resin member 13 has a curing shrinkage of about 0.2
%, A linear expansion coefficient of at least about 16 × 10 −6 / ° C. at room temperature and about 60 × 10 −6 / ° C. at a high temperature equal to or higher than the glass transition temperature. As described above, the resin member 7 has a high curing shrinkage rate and a high linear expansion rate.
Since it is made of a material having high rigidity at normal temperature, a strong pressure stress acts on the semiconductor element substrate 1 after the resin curing step at the time of manufacturing is completed.

【0014】なお、カソード電極基体3及びアソード電
極基体4の間には、樹脂成形時に樹脂が内部に流動する
のを防止するための障壁リング14を設けている。障壁
リング14は、剛性が低く導電性のない材料からなる。
また、半導体素子基体1の上面からカソード電極基体3
の内部を通り、ゲート電極配線5が引き出されている。
A barrier ring 14 is provided between the cathode electrode base 3 and the anode electrode base 4 to prevent the resin from flowing inside during the molding of the resin. The barrier ring 14 is made of a material having low rigidity and non-conductivity.
Also, the cathode electrode substrate 3
, The gate electrode wiring 5 is drawn out.

【0015】上記のように、この発明の半導体装置は、
半導体素子基体1を中央部に挟んだカソード電極基体3
及びアノード電極基体4の外側を取囲む樹脂部材13自
体がそれ自身の硬化収縮力又は熱収縮力により、外側か
ら内側へ向かう圧接力を発揮するので、従来採用してい
たばねやボルト締め等の荷重発生機構は不要となる。
As described above, the semiconductor device of the present invention
Cathode electrode base 3 with semiconductor element base 1 sandwiched in the center
In addition, the resin member 13 surrounding the outside of the anode electrode base 4 itself exerts a pressing force from the outside to the inside due to its own curing shrinkage force or heat shrinkage force. No generating mechanism is required.

【0016】このようにこの発明の半導体装置は、格別
複雑な機構を用いることなく、単に半導体素子基体1を
樹脂部材13で取囲むという簡単な構成で圧接機構を実
現したものである。加えて、この樹脂部材13による封
止という半導体装置の製造工程の中で、既に圧接荷重が
発生しているために、半導体装置組み込み時に別途荷重
を加える作業も不要となる利点も生ずる。
As described above, the semiconductor device of the present invention realizes the press-contact mechanism with a simple configuration in which the semiconductor element base 1 is simply surrounded by the resin member 13 without using a particularly complicated mechanism. In addition, in the semiconductor device manufacturing process of sealing with the resin member 13, since a press-contact load has already been generated, there is an advantage that an operation of separately applying a load when the semiconductor device is incorporated is not required.

【0017】図2(a)は、この発明による第二の実施
の形態を示す断面図で、図2(b)はその上面図であ
る。即ち、半導体素子基体1、緩衝板2、カソード電極
基体3、アノード電極基体4、ゲート電極配線5、樹脂
部材13及び障壁リング14より構成され、各々の機能
は前記第一の実施の形態と同様である。ただし、この実
施の形態では、各電極基体3、4の形状が第一の実施の
形態とは異なり中央部を外して同一円周上に4個突出し
た構造としたので、半導体素子基体1の中央部の上下ま
でを樹脂部材13によって覆ったことに特徴がある。そ
の結果、樹脂部材13の収縮力は半導体素子基体1面に
一層均一に加わることとなり、圧接応力の均一化を向上
させることができる。
FIG. 2A is a sectional view showing a second embodiment according to the present invention, and FIG. 2B is a top view thereof. That is, it is composed of a semiconductor element substrate 1, a buffer plate 2, a cathode electrode substrate 3, an anode electrode substrate 4, a gate electrode wiring 5, a resin member 13, and a barrier ring 14, and each function is the same as that of the first embodiment. It is. However, in this embodiment, unlike the first embodiment, the shape of each of the electrode bases 3 and 4 is different from that of the first embodiment in that the center part is removed and the four bases protrude on the same circumference. It is characterized in that the upper and lower portions of the central portion are covered with the resin member 13. As a result, the contraction force of the resin member 13 is more uniformly applied to the surface of the semiconductor element base 1, and the uniformity of the pressure contact stress can be improved.

【0018】図3は、図2に示した実施の形態の特徴を
特に強調した第三の実施の形態を示す断面図である。こ
の実施の形態においては、半導体素子基体1、緩衝板
2、カソード電極基体3、アノード電極基体4の中央部
にこれらに貫通する穴を設け、その空間にも、樹脂部材
13を注入した構造をなす。この際、半導体素子基体1
と樹脂部材13の間にも障壁リング14を設け、樹脂が
内部に流動するのを防止する。半導体装置をこのように
構成した結果、樹脂部材13の収縮の均一性は一段と向
上し、良好な加圧接触が得られ、熱的歪みを軽減し、接
触電気抵抗の均一化が図れる。
FIG. 3 is a sectional view showing a third embodiment in which features of the embodiment shown in FIG. 2 are particularly emphasized. In this embodiment, a hole is formed in the center of the semiconductor element substrate 1, the buffer plate 2, the cathode electrode substrate 3, and the anode electrode substrate 4, and a resin member 13 is injected into the space. Eggplant At this time, the semiconductor element substrate 1
A barrier ring 14 is also provided between the resin and the resin member 13 to prevent the resin from flowing inside. As a result of configuring the semiconductor device in this manner, the uniformity of shrinkage of the resin member 13 is further improved, good pressure contact can be obtained, thermal distortion can be reduced, and contact electric resistance can be made uniform.

【0019】図4(a)はこの発明の第四の実施の形態
を示す断面図で、図4(b)はその上面図である。複数
の半導体素子基体1a、1bが図示のように並列に配置
され、これに対応して緩衝板2a、2b、カソード電極
基体3a、3b、及び障壁リング14が夫々配置される
とともに、アノード電極基体4及びゲート電極配線5、
樹脂部材13は半導体素子基体1a、1bに共通となる
ように構成されている。各々の機能などは前記第一及び
第二の実施の形態と同様である。
FIG. 4A is a sectional view showing a fourth embodiment of the present invention, and FIG. 4B is a top view thereof. A plurality of semiconductor element bases 1a and 1b are arranged in parallel as shown in the drawing, and correspondingly, buffer plates 2a and 2b, cathode electrode bases 3a and 3b, and barrier ring 14 are respectively arranged, and an anode electrode base is provided. 4 and gate electrode wiring 5,
The resin member 13 is configured to be common to the semiconductor element bases 1a and 1b. Each function is the same as that of the first and second embodiments.

【0020】つまり、樹脂部材13は2個の半導体素子
基体1a、1bに対し、共通に圧接した構成としている
ことを特徴とする。外部樹脂層である樹脂部材13は、
双方の半導体素子基体1a、1bの間において凹部を形
成するから、他の部位より薄い隙間をもって成形されて
いる。その結果、個々の半導体素子基体1a、1bごと
に独立した樹脂の変形が可能であり、圧縮応力の均一性
を良好に保つことができる。
In other words, the resin member 13 is characterized in that the two semiconductor element substrates 1a and 1b are commonly pressed against each other. The resin member 13 which is the external resin layer is
Since a recess is formed between the two semiconductor element bases 1a and 1b, the semiconductor element bases 1a and 1b are formed with a smaller gap than other portions. As a result, the resin can be independently deformed for each of the semiconductor element bases 1a and 1b, and the uniformity of the compressive stress can be kept good.

【0021】なお、上記各実施の形態において、放熱用
の冷却フィンの付加は、カソード及びアノードの各電極
基体3、4に接触するフィンを組込むことによって容易
に実現することができる。
In each of the above-described embodiments, the addition of cooling fins for heat dissipation can be easily realized by incorporating fins that contact the electrode bases 3 and 4 of the cathode and the anode.

【0022】以上説明のように、この発明によれば、複
数の半導体素子基体を圧接する場合でも、格別複雑な構
成を必要とせず、簡単な構成で実現できる。なお、この
発明は上記の各実施の形態のみならず、その要旨を逸脱
しない範囲において、適宜変更して実施し得るものであ
る。
As described above, according to the present invention, even when a plurality of semiconductor element substrates are pressed against each other, it is possible to realize a simple configuration without requiring a particularly complicated configuration. The present invention can be implemented by appropriately modifying not only the above-described embodiments but also within the scope of the gist.

【0023】[0023]

【発明の効果】この発明の半導体装置は、大電力大容量
の圧接型の半導体装置の圧接力発生機能を簡易な構造で
実現し、小型化と製造の容易化が図られるとともに、複
数半導体素子の圧接機構にも柔軟に対応でき、接触電気
抵抗、接触熱抵抗の均一性が向上する効果が得られる。
According to the semiconductor device of the present invention, the pressure-generating function of a high-power, large-capacity pressure-contact type semiconductor device is realized with a simple structure. And the uniformity of the contact electric resistance and the contact thermal resistance can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の半導体装置の第一の実施の形態を示
す構成図である。
FIG. 1 is a configuration diagram showing a first embodiment of a semiconductor device of the present invention.

【図2】この発明の半導体装置の第二の実施の形態を示
す構成図である。
FIG. 2 is a configuration diagram showing a second embodiment of the semiconductor device of the present invention.

【図3】この発明の半導体装置の第三の実施の形態を示
す構成図である。
FIG. 3 is a configuration diagram showing a third embodiment of the semiconductor device of the present invention.

【図4】この発明の半導体装置の第四の実施の形態を示
す構成図である。
FIG. 4 is a configuration diagram showing a fourth embodiment of the semiconductor device of the present invention.

【図5】従来の半導体装置を示す構成図である。FIG. 5 is a configuration diagram showing a conventional semiconductor device.

【図6】図5に示す半導体装置を3個組込み荷重を加え
た状況を示す正面図である。
FIG. 6 is a front view showing a state in which three semiconductor devices shown in FIG. 5 are assembled and a load is applied.

【符号の説明】[Explanation of symbols]

1、1a、1b 半導体素子基体 2、2a、2b 緩衝板 3、3a、3b カソード電極基体 4 アノード電極基体 5 ゲート電極配線 13 樹脂部材 14 障壁リング DESCRIPTION OF SYMBOLS 1, 1a, 1b Semiconductor element base 2, 2a, 2b Buffer plate 3, 3a, 3b Cathode electrode base 4 Anode electrode base 5 Gate electrode wiring 13 Resin member 14 Barrier ring

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/52 H01L 29/74 H01L 23/28 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/52 H01L 29/74 H01L 23/28

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電極基体を介して半導体素子基体を圧接
する構造の半導体装置において、 並列に配置された複数個の半導体基体及び前記複数個の
半導体素子基体に対応する複数個の電極基体を囲み、且
つ前記複数個の半導体基体間に介在するように形成され
た樹脂部材を備えたことを特徴とする半導体装置。
In a semiconductor device having a structure in which a semiconductor element substrate is pressed into contact with an electrode substrate, a plurality of semiconductor substrates arranged in parallel and a plurality of electrode substrates corresponding to the plurality of semiconductor element substrates are surrounded. And a resin member formed so as to be interposed between the plurality of semiconductor substrates.
【請求項2】 前記半導体基体と前記電極基体とは、前
記樹脂部材の硬化収縮力又は加熱収縮力によって互いに
圧接構成されたことを特徴とする請求項1記載の半導体
装置。
2. The semiconductor device according to claim 1, wherein said semiconductor substrate and said electrode substrate are pressed against each other by a curing shrinkage force or a heat shrinkage force of said resin member.
JP22927595A 1995-09-06 1995-09-06 Semiconductor device Expired - Fee Related JP3258212B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22927595A JP3258212B2 (en) 1995-09-06 1995-09-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22927595A JP3258212B2 (en) 1995-09-06 1995-09-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0974110A JPH0974110A (en) 1997-03-18
JP3258212B2 true JP3258212B2 (en) 2002-02-18

Family

ID=16889566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22927595A Expired - Fee Related JP3258212B2 (en) 1995-09-06 1995-09-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3258212B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4631179B2 (en) * 2001-02-09 2011-02-16 富士電機システムズ株式会社 Semiconductor device and inverter device using the same
JP4781560B2 (en) * 2001-06-08 2011-09-28 三菱電機株式会社 Gate drive device
JP5024439B2 (en) * 2010-09-24 2012-09-12 富士電機株式会社 Semiconductor device
JP5684194B2 (en) * 2012-05-10 2015-03-11 株式会社東芝 Pressure welding semiconductor device and pressure welding method of pressure welding semiconductor device

Also Published As

Publication number Publication date
JPH0974110A (en) 1997-03-18

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