CN212209480U - Power device - Google Patents

Abstract

The utility model provides a power device, which comprises a first substrate, a second substrate, a chip and a substrate cushion block; a first metal layer is arranged on one surface of the first substrate, a second metal layer is arranged on one surface of the second substrate, the first substrate and the second substrate are arranged in parallel, and the first metal layer is opposite to the second metal layer; the bottom surface of the chip is bonded with the first metal layer, and the top surface of the chip is in contact with or bonded with the second metal layer; or the bottom surface of the chip is bonded with the second metal layer, and the top surface of the chip is in contact with or bonded with the first metal layer; the substrate cushion block is arranged between the first substrate and the second substrate, and the substrate cushion block is respectively contacted with the first metal layer and the second metal layer. The power device has the advantages that the circuit area for arranging the components and the heat dissipation area of the components are greatly increased by splitting the single-surface packaged substrate into the double-substrate structure, the problem of thermal accumulation of the components can be effectively solved, and the power device has good practicability.

Description

Power device

Technical Field

The utility model relates to the electron device field, concretely relates to device.

Background

At present, the main problem of limiting the power increase and size simplification of the semiconductor power device is the heat dissipation problem of the semiconductor power device. With the increase of power and simplified integration of size of semiconductor power devices, the size of components on the power devices is reduced, the distance between the components is reduced, and the performance of the components is easily weakened and damaged due to heat accumulation. At present, most of high-power devices are packaged in a single-side mode, the heat dissipation path of the single-side packaging is single, and the single-side packaging does not have space performance, so that the traditional single-side packaging is difficult to meet the heat dissipation requirement of high-power devices with high integration.

SUMMERY OF THE UTILITY MODEL

In order to overcome the shortcoming of current power device, the utility model provides a power device through becoming the double-base-plate structure with the base plate split of single-sided encapsulation, makes the circuit area that can supply components and parts to arrange and the heat radiating area greatly increased of components and parts, can effectively solve the hot accumulational problem of components and parts.

Correspondingly, the utility model provides a power device, which comprises a first substrate, a second substrate, a chip and a substrate pad;

a first metal layer is arranged on one surface of the first substrate, a second metal layer is arranged on one surface of the second substrate, the first substrate and the second substrate are arranged in parallel, and the first metal layer is opposite to the second metal layer;

the bottom surface of the chip is bonded with the first metal layer, and the top surface of the chip is in contact with or bonded with the second metal layer; or the bottom surface of the chip is bonded with the second metal layer, and the top surface of the chip is in contact with or bonded with the first metal layer;

the substrate cushion block is arranged between the first substrate and the second substrate, and the substrate cushion block is respectively contacted with the first metal layer and the second metal layer.

In an alternative embodiment, the bottom surface of the chip is provided with a first chip metal layer, and the bottom surface of the chip is directly bonded on the first metal layer or the second metal layer based on the first chip metal layer.

In an optional embodiment, when the top surface of the chip is bonded to the first metal layer or the second metal layer, the top surface of the chip is provided with a second chip metal layer, and the top of the chip is directly bonded to the first metal layer or the second metal layer based on the second chip metal layer.

In an optional embodiment, in an arrangement mode in which the top surface of the chip is in contact with the first metal layer, the top surface of the chip is in contact with the first metal layer at a first contact position;

the structure of the first metal layer at the first contact position is a plane, and the top surface of the chip is in contact with the plane of the first contact position, or the structure of the first metal layer at the first contact position is a groove, and the top surface of the chip is in contact with the bottom surface of the groove of the first contact position, or the structure of the first metal layer at the first contact position is a boss, and the top surface of the chip is in contact with the top surface of the boss of the first contact position;

under the arrangement mode that the top surface of the chip is in contact with the second metal layer, the top surface of the chip is in contact with the first metal layer at a second contact position;

the structure of the second metal layer at the second contact position is a plane, the top surface of the chip is in contact with the plane of the second contact position, or the structure of the second metal layer at the second contact position is a groove, the top surface of the chip is in contact with the bottom surface of the groove at the second contact position, or the structure of the second metal layer at the second contact position is a boss, and the top surface of the chip is in contact with the top surface of the boss at the second contact position.

In an optional embodiment, the substrate pad is a heat conducting insulating pad.

In an alternative embodiment, the first substrate and/or the second substrate is a copper-clad ceramic substrate.

In an alternative embodiment, the number of the chips is two or more.

In an alternative embodiment, two or more of the chip types include a combination chip and/or a single chip;

the single chip comprises a chip body;

the combined chip comprises a chip body and chip cushion blocks, wherein the chip cushion blocks are arranged on the top surface of the corresponding chip body.

In an optional embodiment, the combined chip is in contact with or bonded to the first metal layer based on the corresponding chip pad, and when the combined chip is bonded to the first metal layer based on the corresponding chip pad, a first pad metal layer is disposed on a top surface of the chip pad, and the chip pad is bonded to the first metal layer based on the first pad metal layer;

or the combined chip is in contact with or bonded with the second metal layer based on the corresponding chip cushion block, and when the combined chip is bonded with the second metal layer based on the corresponding chip cushion block, a second cushion block metal layer is arranged on the top surface of the chip cushion block, and the chip cushion block is bonded with the second metal layer based on the second cushion block metal layer.

In an alternative embodiment, the top surface and the bottom surface of the chip pad are contact surfaces, and the side surfaces of the chip pad protrude outward.

In an optional embodiment, two or more of the chips include a first MOS transistor, a second MOS transistor, a first diode, and a second diode;

the power device is provided with three wiring terminals and two groups of control terminals;

the three wiring terminals are a P pole, an N pole and an O pole respectively;

the two groups of control terminals are respectively a first group of control terminals and a second group of control terminals, the first group of control terminals comprise a G1 pole and an S1 pole, and the second group of control terminals comprise a G2 pole and an S2 pole;

the drain electrode of the first MOS tube is connected with the P pole, the gate electrode of the first MOS tube is connected with the G1 pole, and the source electrode of the first MOS tube is respectively connected with the S1 pole and the O pole;

the drain electrode of the second MOS tube is connected with the O pole, the gate electrode of the second MOS tube is connected with the G2 pole, and the source electrode of the second MOS tube is respectively connected with the S2 pole and the N pole;

the anode of the first diode is connected with the P pole, the cathode of the first diode is connected with the O pole, the anode of the second diode is connected with the O pole, and the cathode of the second diode is connected with the N pole.

In summary, the utility model provides a power device, which provides a larger circuit board layout area by the way of three-dimensional arrangement of double-substrate space, can reduce the arrangement density of the chip, and improve the heat dissipation condition of the power device; the top surface and the bottom surface of the chip are respectively contacted with or bonded with the metal layers of the two substrates, so that the advantage of large area of the metal layers can be fully utilized, the heat of the chip is rapidly diffused, and the heat dissipation effect is enhanced; the arrangement form of the chip cushion block can overcome the problem of inconsistent heights of a plurality of chips, simplify the processing difficulty and improve the heat dissipation performance; the design of the connecting layer and the welding layer can facilitate the processing of the power device and has good practicability; the setting of base plate cushion can protect the chip to a certain extent, prevents that the chip from being damaged because of stress concentration, has good practicality.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 shows a schematic diagram of a three-dimensional structure of a power device according to an embodiment of the present invention;

fig. 2 shows a schematic diagram of a three-dimensional structure of a power device according to an embodiment of the present invention;

fig. 3 shows a schematic three-dimensional structure of a first substrate according to an embodiment of the present invention;

FIG. 4 is a schematic cross-sectional structure diagram of a copper-clad ceramic substrate according to an embodiment of the present invention;

fig. 5 shows a schematic diagram of a circuit structure of a power device according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a chip bonding structure according to an embodiment of the present invention;

fig. 7 shows a schematic cross-sectional structure diagram of a power device according to a first embodiment of the present invention;

fig. 8 shows a schematic cross-sectional structure diagram of a power device according to a second embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

Fig. 1 shows the three-dimensional structure schematic diagram of the power device of the embodiment of the present invention, fig. 2 shows the three-dimensional structure schematic diagram of the power device of the embodiment of the present invention (for indicating the structure of the components outside the first substrate), fig. 3 shows the three-dimensional structure schematic diagram of the first substrate of the embodiment of the present invention.

The utility model provides a power device, basically, the power device comprises a first substrate, a second substrate, a chip and a plurality of substrate cushion blocks; a first metal layer is arranged on one surface of the first substrate, a second metal layer is arranged on one surface of the second substrate, the first substrate and the second substrate are arranged in parallel, and the first metal layer is opposite to the second metal layer; the bottom surface of the chip is bonded with the first metal layer, and the top surface of the chip is in contact with or bonded with the second metal layer; or the bottom surface of the chip is bonded with the second metal layer, and the top surface of the chip is in contact with or bonded with the first metal layer; the substrate cushion block is arranged between the first substrate and the second substrate, and the substrate cushion block is respectively contacted with the first metal layer and the second metal layer.

In addition, generally, a surface of an electronic component (i.e., a chip) on which pins are provided is referred to as a bottom surface, and since there are electronic components in which a part of the pins are not located on the bottom surface, in this embodiment, the bottom surface of the electronic component is defined to be provided with the pins, and if the electronic component has pins that are not located on the bottom surface, the part of the pins that are not located on the bottom surface are all located on the top surface, that is, the chip of this embodiment has two basic structures: one is that only the bottom surface of the chip has pins, and the other is that the bottom surface of the chip and the top surface of the chip have pins respectively. Therefore, the bonding structures generated on the bottom surface of the chip and the top surface of the chip mentioned in this embodiment are essentially the bonding structures generated on the leads on the bottom surface of the chip and the leads on the top surface of the chip, which are equivalent to each other, and the description will not be repeated later.

The power device of the embodiment of the utility model comprises a first substrate 1, a second substrate 2, a chip and a substrate cushion block 8; specifically, the number of the chips is multiple, and the bonding structure and the arrangement mode of each chip are mutually independent. A first metal layer 102 is disposed on one surface of the first substrate 1, a second metal layer 202 is disposed on one surface of the second substrate 2, the first substrate 1 and the second substrate 2 are disposed in parallel, and the first metal layer 102 faces the second metal layer 202.

Specifically, the first metal layer 102 on the first substrate 1 and the second metal layer 202 on the second substrate 2 are mainly used to form a corresponding circuit through etching and other processes and to dissipate heat of the chip by using the physical characteristics of the metal layers themselves, and in the specific implementation, in combination with the schematic cross-sectional structure diagram of the copper-clad ceramic substrate according to the embodiment of the present invention shown in fig. 4 of the accompanying drawings, the first substrate 1 and/or the second substrate 2 may be a Copper-clad ceramic substrate, which is an electronic base material manufactured by directly sintering a Copper foil 901 on the surface of a ceramic layer 902 using a DBC (Direct Bond coater) technique, in this embodiment, the Copper foil 901 covers both sides of the ceramic layer 902, one side of the copper foil 901 is used to form the first metal layer 102 on the first substrate 1 (the second metal layer 202 on the second substrate 2), and the other side of the copper foil 901 is used to enhance the heat dissipation of the first substrate 1 (the second substrate 2).

With reference to the schematic circuit structure diagram of the power device shown in fig. 5 in the accompanying drawings, specifically, since the structures of the power devices are numerous, the embodiment of the present invention is described by taking only one of the structures as an example, and the implementation manners of the other power devices can be modified adaptively.

The chip in the power device of the embodiment of the present invention includes a first MOS transistor 803, a second MOS transistor 804, a first diode 801 and a second diode 802; the power device is provided with three wiring terminals and two groups of control terminals; the three wiring terminals are a P pole, an N pole and an O pole respectively; the two groups of control terminals are a first group of control terminals 6 and a second group of control terminals 7 respectively, the first group of control terminals 6 comprises a G1 pole and an S1 pole, and the second group of control terminals 7 comprises a G2 pole and an S2 pole; the drain, the gate and the source of the first MOS tube 803 are respectively connected with the P pole, the G1 pole and the S1 pole, and the source of the first MOS tube 803 is also connected with the O pole; the drain, the gate and the source of the second MOS transistor 804 are respectively connected to the O pole, the G2 pole and the S2 pole, and the source of the second MOS transistor 804 is further connected to the N pole; the anode and the cathode of the first diode 801 are respectively connected with the P pole and the O pole, and the anode and the cathode of the second diode 802 are respectively connected with the O pole and the N pole.

Specifically, the circuit of the power device may refer to the structure shown in fig. 5, in the physical structure related to the power device shown in the drawing, a specific etched circuit is not shown on the metal layer, and in the specific implementation, the circuit structure of the power device is referred to for circuit design.

Accordingly, the second metal layer 202 of the embodiment of the present invention includes a first circuit partition 211, a second circuit partition 212, and a third circuit partition 213, and the first circuit partition 211, the second circuit partition 212, and the third circuit partition 213 are separated from each other and are insulated from each other. The first diode 801 and the first MOS tube 803 are arranged on the first circuit partition 211, and the second diode 802 and the second MOS tube 804 are arranged on the second circuit partition 212; the third circuit partition 213 is mainly used for supporting and dissipating heat from an O-pole connection plate (ground connection plate).

Accordingly, the first metal layer 201 of the embodiment of the present invention includes the fourth circuit partition 111, the fifth circuit partition 112 and the sixth circuit partition 113, and the fourth circuit partition 111, the fifth circuit partition 112 and the sixth circuit partition 113 are separated from each other and are insulated from each other. The fourth circuit partition 111 is mainly used for supporting and dissipating heat of the N-pole connecting plate 4 (negative-pole connecting plate); the fifth circuit partition 112 is mainly used for supporting and dissipating heat of the P-pole connecting plate 3 (positive-pole connecting plate); the sixth circuit partition 113 is used for bonding the second MOS transistor 804.

Specifically, in order to provide the external use of the power device, the power device of this embodiment further includes a P-pole connection board 3, an N-pole connection board 4, and an O-pole connection board 5, specifically, one end of the P-pole connection board 3 is bonded on the first circuit partition 211, and the other end is provided for external connection; one end of the N-pole connecting plate 4 is bonded on the second circuit partition 212, and the other end is externally connected; one end of the O-pole connecting plate 5 is bonded to the sixth circuit partition 113, and the other end is externally connected.

Correspondingly, since the first MOS transistor 803 and the second MOS transistor 804 need to be controlled by the outside to function, correspondingly, the power device of this embodiment further includes a first control connection board 6 and a second control connection board 7, where the first control connection board 6 is bonded and disposed on the sixth circuit partition 113, and is used for electrically connecting with the related circuit of the first MOS transistor 803; the second control connection board 7 is bonded to the second circuit partition 212 for electrically connecting with the related circuit of the first MOS transistor 803.

Specifically, the anode of the first diode 801 is located on the bottom surface, and the cathode of the first diode 801 is located on the top surface; the anode of first diode 801 is connected to P-plate 3 based on a corresponding circuit on first circuit partition 211, and the cathode of first diode 802 is connected to O-plate 5 based on a corresponding circuit on sixth circuit partition 113.

Specifically, the drain of the first MOS transistor 803 is disposed on the bottom surface of the first MOS transistor 803, and the source and the gate of the first MOS transistor 803 are disposed on the top surface of the first MOS transistor 803; the drain electrode of the first MOS tube 803 is connected to the P-pole connecting plate 3 based on the corresponding circuit on the first circuit partition 211, and the source electrode and the gate electrode of the first MOS tube 803 are connected to the first control connecting plate 6 based on the corresponding circuit on the sixth circuit partition 113; meanwhile, the source of the first MOS tube 803 is also connected to the O-pole connection plate 5.

Specifically, the cathode of the second electrode tube 802 is located on the bottom surface, and the anode of the second electrode tube 802 is located on the top surface; the cathode of the second electrode tube 802 is connected to the N-pole connecting plate 4 based on the corresponding circuit on the second circuit partition 212, and the anode of the second electrode tube 802 is connected to the O-pole connecting plate 5 based on the corresponding circuit on the sixth circuit partition 113.

Specifically, the drain of the second MOS transistor 804 is disposed on the top surface of the second MOS transistor 804, and the source and the gate of the second MOS transistor 804 are disposed on the bottom surface of the second MOS transistor 804; the missing marks of the second MOS transistor 804 are connected to the O-pole connecting plate 5 based on the corresponding circuit on the sixth circuit partition 113, the source and the gate of the second MOS transistor 804 are connected to the second control connecting plate 7 based on the corresponding circuit on the second circuit partition 212, and meanwhile, the source of the second MOS transistor 804 is also connected to the N-pole connecting plate 4 based on the corresponding circuit on the second circuit partition 212.

Specifically, when the first substrate 1 and the second substrate 2 are assembled into a power device, the chip on the first substrate 1 needs to be closely attached (bonded) to the second metal layer 202 of the second substrate 2, and the chip on the second substrate 2 needs to be closely attached (bonded) to the first metal layer 102 of the first substrate 1, so that the first substrate 1 and the second substrate 2 inevitably generate a certain force on the chip during the assembly operation. In order to prevent the chip from being damaged and failed by the acting force, on the one hand, the embodiment of the present invention sets the reasonable heights of the P-pole connecting plate 3, the N-pole connecting plate 4 and the O-pole connecting plate 5, and sets the fifth circuit partition 112, the fourth circuit partition 111 and the third circuit partition 213 corresponding to the P-pole connecting plate 3, the N-pole connecting plate 4 and the O-pole connecting plate 5, respectively, so that when the first substrate 1 and the second substrate 2 are assembled, the connecting plate can divide the acting force between the first substrate and the second substrate, so as to reduce the acting force applied to the chip, and prevent the chip from being damaged by the acting force; similarly, the first control connecting plate 7 and the second control connecting plate 6 can also produce the same action effect; on the other hand, because the connecting plate all is located the border position of base plate, in order to further improve the protection to the chip, this embodiment still is provided with a plurality of base plate cushion 8 between first base plate and second base plate, a plurality of base plate cushion 8 distributes and sets up on every chip position all around, through the height that rationally sets up base plate cushion 8, can form good partial pressure effect to the chip, reduces the risk that the chip is destroyed by the effort.

Specifically, the substrate pad 8 is a heat-conducting insulating pad, which can avoid damage to the circuit structure between power devices, and at the same time, heat conduction (higher than air) is generated between the first metal layer 102 and the second metal layer 202, so that the first metal layer 102 and the second metal layer 202 can be utilized to the maximum extent to achieve the best heat dissipation effect.

Optionally, the substrate pad 8 may be in the shape of a needle, a bar, or a block, and the specific shape may be adaptively designed according to the setting position.

Specifically, in the power device provided by this embodiment, the traditional single-substrate design is improved into a double-substrate design, so that the board layout area and the heat dissipation area can be increased by nearly one time under a similar volume, the layout difficulty of the chip is simplified, and the heat dissipation performance of the chip is improved; correspondingly, the circuit can be arranged on the two substrates, so that the wiring density is reduced, the design difficulty and the production difficulty can be reduced, and the production yield of products is improved; the top surface of the chip bonded on the first metal layer is in contact with or bonded with the second metal layer, and the top surface of the chip bonded on the second metal layer is in contact with or bonded with the first metal layer, so that the accumulation of chip heat can be avoided, the working temperature of the chip is reduced, the service life of the power device is prolonged, and the power device has good practicability.

Furthermore, the traditional chip bonding mode is usually realized by adopting solder such as solder paste and the like through a corresponding welding process, and the welding is realized in a mode of tool contact; in this embodiment, since the chip is located inside the device, if both the bottom surface and the top surface of the chip need to be bonded to the corresponding metal layers, the conventional chip bonding method is difficult to operate; in order to improve the operation efficiency, the chip bonding method according to the embodiment of the present invention may adopt an SAM (Self-Assembled Monolayer) technique. Specifically, the SAM is a low-temperature low-pressure self-assembled monolayer bonding based on a surface activation bonding technology.

Basically, therefore, the chip bottom surface is provided with a first chip metal layer, and the chip bottom surface is directly bonded to the first metal layer or the second metal layer based on the first chip metal layer. The first chip metal layer is used for forming a bottom layer for SAM technology operation on the bottom surface of the chip, so that bonding between the bottom surface of the chip and the first metal layer or the second metal layer is realized; the first chip metal layer is typically processed by an electroplating process.

Further, when the top surface of the chip is bonded to the first metal layer or the second metal layer, the top surface of the chip is provided with a second chip metal layer, and the top of the chip is directly bonded to the first metal layer or the second metal layer based on the second chip metal layer. The second chip metal layer is used for forming a top layer on the top surface of the chip for SAM technology operation, so that bonding between the top surface of the chip and the first metal layer or the second metal layer is realized; the second chip metal layer is typically processed by an electroplating process.

Preferably, the materials of the first chip metal layer and the second chip metal layer may be selected according to the material of their bonding targets (the first metal layer or the second metal layer); preferably, the bonding effect is good when the materials of the first chip metal layer and the second chip metal layer are the same as the materials of the bonding objects.

In this embodiment, since the first metal layer and the second metal layer are both made of copper foil, the first chip metal layer and the second chip metal layer are made of copper, and hereinafter, the first chip metal layer and the second chip metal layer are collectively referred to as the connection layer 903 for convenience of description.

Refer to fig. 6 for a schematic diagram of the chip bonding structure of the present embodiment. The bottom of the chip is provided with a first chip metal layer 903, when the chip is bonded to a copper foil 901 (metal layer), the contact surfaces of the bottom surface of the connecting layer 903 on the bottom surface of the chip and the top surface of the copper foil 901 are firstly subjected to surface treatment to make the contact surfaces smooth and flat, and then the contact surfaces are subjected to plasma treatment; under ion beam bombardment or plasma radiation, the oxide and contamination of the contact surface are removed, so that a clean contact surface is obtained, and active and incomplete chemical bonds are generated on the contact surface (it is required to say that the plasma treatment of the contact surface does not require physical tool contact); the two contact surfaces are then brought into contact with each other under certain conditions (low temperature and certain pressure) and upon contact of the two contact surfaces, the extremely unstable chemical bonds begin to spontaneously react to form strong chemical bonds 904.

Similarly, if the top surface of the chip needs to be bonded to the first metal layer or the second metal layer, the second chip metal layer 930 may be disposed on the top surface of the chip, and the top surface of the second chip metal layer 930 and the surface of the object to which the second chip metal layer 930 is bonded are bonded through the SAM process.

Specifically, the bonding structure between the chip and the first metal layer or the second metal layer is also related to the structure at the corresponding position on the first metal layer or the second metal layer. If the first metal layer or the second metal layer is a plane at the bonding position, bonding the chip on the plane at the bonding position; if the first metal layer or the second metal layer is provided with a groove at the bonding position, bonding the chip in the groove at the bonding position; and if the first metal layer or the second metal layer is provided with the boss at the bonding position, the chip is bonded on the top surface of the boss at the bonding position.

Further, when the number of chips is greater than two, if the total heights of the chips are not uniform, in order to enable the chips to be applied to the power device of the present embodiment, a corresponding design needs to be made.

The first embodiment is as follows:

fig. 7 shows a schematic cross-sectional structure diagram of a power device according to an embodiment of the present invention. In order to enable the chips with different chip heights to be applied to the power device provided by the present invention, optionally, in the arrangement mode that the top surface of the chip is in contact with the first metal layer, the top surface of the chip is in contact with the first metal layer at a first contact position; the structure of the first metal layer at the first contact position is a plane, the top surface of the chip is in contact with the plane of the first contact position, or the structure of the first metal layer at the first contact position is a groove, the top surface of the chip is in contact with the bottom surface of the groove at the first contact position, or the structure of the first metal layer at the first contact position is a boss, and the top surface of the chip is in contact with the top surface of the boss at the first contact position.

Under the arrangement mode that the top surface of the chip is in contact with the second metal layer, the top surface of the chip is in contact with the first metal layer at a second contact position; the structure of the second metal layer at the second contact position is a plane, the top surface of the chip is in contact with the plane of the second contact position, or the structure of the second metal layer at the second contact position is a groove, the top surface of the chip is in contact with the bottom surface of the groove at the second contact position, or the structure of the second metal layer at the second contact position is a boss, and the top surface of the chip is in contact with the top surface of the boss at the second contact position.

Specifically, through the structure setting of first metal level and second metal level, if set up to modes such as plane, recess, boss to guaranteeing that first base plate and second base plate are under the state that is parallel to each other, the chip of co-altitude can set up on first base plate and second base plate, in order to realize the utility model provides a power device's structure.

Based on the above-described embodiments, in the embodiment of the present invention, there are six cases in total for the arrangement form of the chips 9, six chips 9 are illustrated in fig. 7, and the six cases are illustrated in the six chips 9, respectively, for understanding with reference to fig. 7.

Specifically, this embodiment makes not co-altitude chip can the adaptation setting on first base plate or second base plate through set up the recess that corresponds the degree of depth or the boss that corresponds the height on the metal level of base plate, has guaranteed that the top surface of each chip can both keep in contact with corresponding metal level to realize improving the purpose of radiating effect, have good practicality.

Example two:

fig. 8 shows a schematic cross-sectional structure diagram of a power device according to an embodiment of the present invention. Specifically, the height of the chip can be adjusted to adapt the chip to the distance between the first substrate and the first substrate.

Specifically, in the present embodiment, the types of two or more of the chips are divided into a combination chip 20 and a single chip 21; the single chip 21 includes a chip body 10; the combined chip 20 comprises a chip body 10 and chip pads 11, wherein the chip pads 11 are arranged on the top surface of the corresponding chip body 10.

It should be noted that the chip body 10 is a chip in nature, and is the same as the chip described above in terms of physical meaning, and the naming manner of the embodiment of the present invention is only used for making a distinction in terms of semantic meaning.

In the concrete implementation, the height of a plurality of chip body 10 is different, in order to guarantee the whole highly uniform of a plurality of chip, or dwindles the difference in height of a plurality of chip, makes it can use to the utility model provides an in the power device structure, can set up chip cushion 11 on the top surface of chip body 10 to increase the chip height that chip body 10 corresponds.

Specifically, the top surface and the bottom surface of the chip pad 11 are smooth to ensure the contact between the chip pad 11 and the chip body 10 and between the chip pad 11 and the metal layers (the first metal layer 102 and the second metal layer 202).

Specifically, the chip pad 11 may be processed before the chip 10 is bonded to the corresponding metal layer, that is, the chip pad 11 is first disposed on the top surface of the chip 10 to form a complete chip, and then the chip is bonded to the corresponding metal layer.

Alternatively, the die pad 11 may be soldered to the top surface of the die body 10 by solder such as solder paste.

Optionally, after the bottom surface of the chip with the chip pad 11 is bonded to the corresponding metal layer, the top surface of the chip (i.e., the chip pad 11) needs to be contacted or bonded with another corresponding metal layer to ensure the heat dissipation effect.

Optionally, the combined chip is in contact with or bonded to the first metal layer based on the corresponding chip pad, and when the combined chip is bonded to the first metal layer based on the corresponding chip pad, a first pad metal layer is disposed on the top surface of the chip pad, and the chip pad is bonded to the first metal layer based on the first pad metal layer; or the combined chip is in contact with or bonded with the second metal layer based on the corresponding chip cushion block, and when the combined chip is bonded with the second metal layer based on the corresponding chip cushion block, a second cushion block metal layer is arranged on the top surface of the chip cushion block, and the chip cushion block is bonded with the second metal layer based on the second cushion block metal layer. The first pad metal layer and the second pad metal layer are provided for implementing the SAM process, and in particular, the bonding manner between the first pad metal layer and the metal layer and between the second pad metal layer and the metal layer may refer to the embodiments of the first chip metal layer and the second chip metal layer, and the description will not be repeated. Through the embodiment, the chip can be tightly contacted with the metal layer, and the heat dissipation effect of the metal layer on the chip can be further improved.

Optionally, because the chip pad 11 is disposed on the top surface of the chip, if the top surface of the chip body 10 is provided with pins, the chip pad 11 needs to be connected to a corresponding circuit, and in order to ensure the connection effect, the chip pad needs to be made of a conductive material. Meanwhile, the die pad 11 is generally made of a metal material having a high young's modulus to resist the pressure generated during the SAM process.

Alternatively, the top and bottom surfaces of the die pad 11 are contact surfaces, and thus, in order to ensure the contact tightness, the top and bottom surfaces of the die pad need to be processed into flat surfaces.

Optionally, the chip pad 11 may also have a certain heat dissipation function besides a conductive function, so that, in order to increase the heat dissipation effect of the chip pad, in this embodiment, the side surface of the chip pad 11 is not a regular plane or a curved surface, and the middle of the chip top block 11 protrudes outward, so that the side area of the chip pad 11 is increased, the contact area between the chip pad and the outside is increased, and the heat dissipation effect of the chip pad 11 is enhanced.

To sum up, the chip cushion block 11 of the embodiment has the functions of adjusting the height of the chip, improving the heat dissipation effect of the chip and electrically connecting the chip, and has good practicability.

Example three:

furthermore, as can be seen from the above description, the first chip metal layer, the second chip metal layer, the first pad metal layer, the second pad metal layer, and the solder between the pad and the chip body all can affect the overall height of the chip, so that the purpose of adjusting the overall height of the chip can be achieved by adjusting the thicknesses of the solder between the first chip metal layer, the second chip metal layer, the first pad metal layer, the second pad metal layer, and the pad and the chip body; therefore, in the specific implementation, the thickness of the structure can be adjusted to be suitable for different power devices.

In specific implementation, due to the thickness limitation of the metal layer, the implementation described in the first embodiment is generally applied to a scenario where the height difference of a plurality of chips is small, and the implementation described in the second embodiment is generally applied to a scenario where the height difference of a plurality of chips is large; in specific implementation, the implementation manners described in the first embodiment and the second embodiment can also be used in combination, and the embodiments of the present invention are not necessarily described in the first embodiment.

In summary, the utility model provides a power device, which provides a larger circuit board layout area by the way of three-dimensional arrangement of double-substrate space, can reduce the arrangement density of the chip, and improve the heat dissipation condition of the power device; the top surface and the bottom surface of the chip are respectively contacted with or bonded with the metal layers of the two substrates, so that the advantage of large area of the metal layers can be fully utilized, the heat of the chip is rapidly diffused, and the heat dissipation effect is enhanced; the arrangement form of the chip cushion block can overcome the problem of inconsistent heights of a plurality of chips, simplify the processing difficulty and improve the heat dissipation performance; the design of the connecting layer and the welding layer can facilitate the processing of the power device and has good practicability; the setting of base plate cushion can protect the chip to a certain extent, prevents that the chip from being damaged because of stress concentration, has good practicality.

The power device provided by the embodiment of the present invention is described in detail above, and the principle and the implementation of the present invention are explained by applying a specific example, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.

Claims (11)

1. A power device is characterized by comprising a first substrate, a second substrate, a chip and a substrate cushion block;

a first metal layer is arranged on one surface of the first substrate, a second metal layer is arranged on one surface of the second substrate, the first substrate and the second substrate are arranged in parallel, and the first metal layer is opposite to the second metal layer;

the bottom surface of the chip is bonded with the first metal layer, and the top surface of the chip is in contact with or bonded with the second metal layer; or the bottom surface of the chip is bonded with the second metal layer, and the top surface of the chip is in contact with or bonded with the first metal layer;

the substrate cushion block is arranged between the first substrate and the second substrate, and the substrate cushion block is respectively contacted with the first metal layer and the second metal layer.

2. The power device of claim 1, wherein the chip bottom surface is provided with a first chip metal layer, the chip bottom surface being directly bonded on the first metal layer or the second metal layer based on the first chip metal layer.

3. The power device of claim 2, wherein the top surface of the chip is provided with a second chip metal layer when the top surface of the chip is provided in bonding with the first metal layer or the second metal layer, the top of the chip being directly bonded on the first metal layer or the second metal layer based on the second chip metal layer.

4. The power device of claim 1, wherein the top surface of the chip makes contact with the first metal layer at a first contact location in an arrangement in which the top surface of the chip makes contact with the first metal layer;

the structure of the first metal layer at the first contact position is a plane, and the top surface of the chip is in contact with the plane of the first contact position, or the structure of the first metal layer at the first contact position is a groove, and the top surface of the chip is in contact with the bottom surface of the groove of the first contact position, or the structure of the first metal layer at the first contact position is a boss, and the top surface of the chip is in contact with the top surface of the boss of the first contact position;

under the arrangement mode that the top surface of the chip is in contact with the second metal layer, the top surface of the chip is in contact with the first metal layer at a second contact position;

the structure of the second metal layer at the second contact position is a plane, the top surface of the chip is in contact with the plane of the second contact position, or the structure of the second metal layer at the second contact position is a groove, the top surface of the chip is in contact with the bottom surface of the groove at the second contact position, or the structure of the second metal layer at the second contact position is a boss, and the top surface of the chip is in contact with the top surface of the boss at the second contact position.

5. The power device of claim 1, wherein the substrate pad is an insulating and thermally conductive pad.

6. The power device of claim 1, wherein the first substrate and/or the second substrate is a copper-clad ceramic substrate.

7. The power device according to any one of claims 1 to 6, wherein the number of the chips is two or more.

8. The power device of claim 7, wherein the types of two or more of the chips include a combination chip and/or a single chip;

the single chip comprises a chip body;

the combined chip comprises a chip body and chip cushion blocks, wherein the chip cushion blocks are arranged on the top surface of the corresponding chip body.

9. The power device of claim 8, wherein when the combined chip is in contact with or bonded to the first metal layer based on the corresponding chip pad and when the combined chip is bonded to the first metal layer based on the corresponding chip pad, the top surface of the chip pad is provided with a first pad metal layer, and the chip pad is bonded to the first metal layer based on the first pad metal layer;

or when the combined chip is in contact with or bonded with the second metal layer based on the corresponding chip cushion block and the combined chip is bonded with the second metal layer based on the corresponding chip cushion block, a second cushion block metal layer is arranged on the top surface of the chip cushion block, and the chip cushion block is bonded with the second metal layer based on the second cushion block metal layer.

10. The power device of claim 8, wherein the top and bottom surfaces of the chip pad are contact surfaces, and the side surfaces of the chip pad are convex toward the outside.

11. The power device of claim 7, wherein two or more of the chips comprise a first MOS transistor, a second MOS transistor, a first diode, and a second diode;

the power device is provided with three wiring terminals and two groups of control terminals;

the three wiring terminals are a P pole, an N pole and an O pole respectively;

the two groups of control terminals are respectively a first group of control terminals and a second group of control terminals, the first group of control terminals comprise a G1 pole and an S1 pole, and the second group of control terminals comprise a G2 pole and an S2 pole;

the drain electrode of the first MOS tube is connected with the P pole, the gate electrode of the first MOS tube is connected with the G1 pole, and the source electrode of the first MOS tube is respectively connected with the S1 pole and the O pole;

the drain electrode of the second MOS tube is connected with the O pole, the gate electrode of the second MOS tube is connected with the G2 pole, and the source electrode of the second MOS tube is respectively connected with the S2 pole and the N pole;

the anode of the first diode is connected with the P pole, the cathode of the first diode is connected with the O pole, the anode of the second diode is connected with the O pole, and the cathode of the second diode is connected with the N pole.

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