JPS6055633A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6055633A JPS6055633A JP58163141A JP16314183A JPS6055633A JP S6055633 A JPS6055633 A JP S6055633A JP 58163141 A JP58163141 A JP 58163141A JP 16314183 A JP16314183 A JP 16314183A JP S6055633 A JPS6055633 A JP S6055633A
- Authority
- JP
- Japan
- Prior art keywords
- plate
- electrode
- annular
- electrode plate
- control electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims description 10
- 241001474791 Proboscis Species 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract 4
- 238000000034 method Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 239000004809 Teflon Substances 0.000 description 2
- 229920006362 Teflon® Polymers 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- WTDRDQBEARUVNC-LURJTMIESA-N L-DOPA Chemical compound OC(=O)[C@@H](N)CC1=CC=C(O)C(O)=C1 WTDRDQBEARUVNC-LURJTMIESA-N 0.000 description 1
- 241000529569 Solena Species 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はトランジスタ、ゲートターンオフサイリスタ等
の微細電極パターンを南する半導体装1kに係り、特に
制御1は極部の月二接構造に関°Iるものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device 1k in which a fine electrode pattern such as a transistor, a gate turn-off thyristor, etc. It is something that
トランジスタ(以下T几Sと略+i+F、 )−やゲー
用・ターンオフサイリスタ(以下(] 1’ 0と略i
11: ) ’r&:l’、。Transistors (hereinafter referred to as TS and abbreviated as +i+F, )- and game turn-off thyristors (hereinafter referred to as 1' 0 and abbreviated as i)
11: ) 'r&:l',.
半導体基体におけるエミッタj−を微細な・え髪月li
t状に分割し、各エミツタ層にエミッタ電極膜やカソー
ド電極j摸を設けると共に、隣接ベース層にベース電極
膜、ゲート電極膜を各エミツタ層を取囲む様に設け、タ
ーンオフ時にベース層からキャリアの引出しを早め、高
速動作が行われる様にしている。The emitter in the semiconductor substrate is formed into a minute
The emitter layer is divided into T-shaped parts, and an emitter electrode film and a cathode electrode are provided on each emitter layer, and a base electrode film and a gate electrode film are provided on the adjacent base layer so as to surround each emitter layer. The withdrawal speed is accelerated to ensure high-speed operation.
TBS、GTOが大容量になると、エミッタ電極膜やカ
ソード電極膜に外部電極を中間滑動板を介して圧接する
と共に、ベース電極膜、ゲート電極膜に対してもベース
リード、ゲートリードを圧接して、部材間の熱膨張係数
の差によシ半導体塞体が破壊することや特性劣下を防止
し、また、電極構造の単純化を図っている。When TBS and GTO have a large capacity, external electrodes are pressed into contact with the emitter electrode film and cathode electrode film via an intermediate sliding plate, and base leads and gate leads are also pressed into contact with the base electrode film and gate electrode film. This prevents the semiconductor plug from being destroyed or from deteriorating its characteristics due to differences in thermal expansion coefficients between the members, and also simplifies the electrode structure.
この場合、外部電極に加えられる圧接力の一部をベース
リード、ゲートリード等に分けているが、半導体基体に
加わる圧接荷重が均一であシ、圧接部での電気抵抗が均
一であると、TBS、GTOの電気的特性、機械的特性
は均一化する、特に、大容量化すると、ベースリード、
ゲートリードの圧接部が各エミツタ層に対して偏ること
になシ、ベース電極膜、ゲート電極膜の内部抵抗を無視
できなくなり、動作の吻−性がj旧ンれがちである。In this case, part of the pressure force applied to the external electrode is divided into the base lead, gate lead, etc., but if the pressure force applied to the semiconductor substrate is uniform and the electrical resistance at the pressure contact part is uniform, The electrical and mechanical properties of TBS and GTO become uniform, especially as the capacity increases, the base lead,
If the pressure contact portion of the gate lead is biased against each emitter layer, the internal resistance of the base electrode film and gate electrode film cannot be ignored, and the characteristic of operation tends to deteriorate.
従って、本発明の目的は、圧接荷重が均一で、良好な電
気的1機械的特性を備えた半導体装1uを提供するにあ
る。Therefore, an object of the present invention is to provide a semiconductor device 1u with uniform pressure contact load and good electrical and mechanical properties.
本発明の特徴とするところは、短冊状の複数個のエミッ
タL−が同心状に群をなして分れて配置dされ、各群の
最外層に同心状に配置dされた環状中間滑動板がそれぞ
れ当接され、6環状中間滑動板と同心的に配置され市電
間滑動板の間を通1〜で制憫1電極板が当接され、各環
状中間f犀1Ilb仮には直接、そして、制御室&仮に
は皿ばねを介して外部電極が当接し、皿ばねは制御!極
板の幅中心のあたりに当接されていることにある。The present invention is characterized in that a plurality of strip-shaped emitters L- are arranged concentrically in groups, and an annular intermediate sliding plate is arranged concentrically in the outermost layer of each group. are in contact with each other, and are arranged concentrically with the 6 annular intermediate sliding plates, and the control 1 electrode plate is in contact with the inter-city tram sliding plates 1 through 1, and each annular intermediate f 1 Ilb is tentatively directly connected to the control room. &Temporarily, the external electrode comes into contact with the disc spring, and the disc spring is controlled! The reason is that it is in contact with the center of the width of the electrode plate.
以下、本発明をGTOを例に採って図面に示す実施例と
共に説明する。Hereinafter, the present invention will be explained using a GTO as an example, together with embodiments shown in the drawings.
第1図において、10oは気密容器で、これは、セラミ
ック筒101の両開口部にフランジ102〜104を介
して可撓性を持って、かつ気密に設けられた1対の外部
電極105,106から構成されている。In FIG. 1, 10o is an airtight container, which includes a pair of external electrodes 105 and 106 that are flexible and airtightly provided at both openings of a ceramic cylinder 101 via flanges 102 to 104. It consists of
外部電極105.106の間に半導体素子200が配置
されている。A semiconductor element 200 is arranged between the external electrodes 105 and 106.
半導体素子200は第2図(a)(b)に拡大して示す
ように半導体(シリコン)基体201とタングステンあ
るいはモリブデンの支持体202をろう材203で一体
化したものである。勿論、シリコン基体201のみであ
ってもよい。The semiconductor element 200 is made by integrating a semiconductor (silicon) substrate 201 and a tungsten or molybdenum support 202 with a brazing material 203, as shown enlarged in FIGS. 2(a) and 2(b). Of course, only the silicon substrate 201 may be used.
シリコン基体201は1対の主表面に導電型が順次異な
る4個の半導体層Nウ P s 、 N B。The silicon substrate 201 has a pair of main surfaces having four semiconductor layers Np, Nb having sequentially different conductivity types.
Pvを有し、Nr+層は短冊状に分割されて、放射状に
配置されている。更に、放射状の各Nw層はシリコン基
体201の中心側と周縁側の2群に分けられている。各
Nw層にはアルミニウムのカソード電極膜204が低抵
抗接触され、PB層には各Nv層を取囲むようにアルミ
ニウムのゲート電極膜205が低抵抗接触されている。Pv, and the Nr+ layer is divided into strips and arranged radially. Further, each radial Nw layer is divided into two groups, one on the center side and the other on the peripheral side of the silicon substrate 201. An aluminum cathode electrode film 204 is in low resistance contact with each Nw layer, and an aluminum gate electrode film 205 is in low resistance contact with the PB layer so as to surround each Nv layer.
尚第2図(a)では144純化のためツノソード、ゲー
トの各電極膜204,205や光面の酸化膜を省略して
いる。In FIG. 2(a), the electrode films 204 and 205 of the horn sword and gate, as well as the oxide film on the optical surface, are omitted for 144 simplicity.
半導体素子20()は外部′電極105、支持板202
間に保合するテフロンガ、イド206により位置決めさ
れ、また、シリコーンゴムのワニス207で端部表面処
理が行われている。The semiconductor element 20 () has an external electrode 105 and a support plate 202.
It is positioned by a Teflon gas and an id 206 held in between, and the end surface is treated with silicone rubber varnish 207.
中心側群の各NIIJ−上のカッ−ド電極204、周縁
側群の各N w )@ l:のカソード市1極204に
対して、タングステンの環状中間滑動41y :S (
11。A tungsten annular intermediate slide 41y: S (
11.
302が当接されている。両者間rlt動板301゜3
02は同心状に配置され、両省間にモリブデンの環状ゲ
ート1!極板303がや―り同心状に配置されている。302 is in contact. Rlt moving plate between both 301°3
02 is arranged concentrically, and the molybdenum ring gate 1 between the two provinces! The electrode plates 303 are also arranged concentrically.
中間滑動板301,302に外部電極106が直接当接
し、ゲート奄他板303には皿ばね304を介して外部
電極106が当接している。The external electrode 106 is in direct contact with the intermediate sliding plates 301 and 302, and the external electrode 106 is in contact with the gate and other plates 303 via a disc spring 304.
ゲート電極板303は中心側JJ’Pの各Nt層と周縁
側群の各Nw層の間のp m Jim にのゲート電極
膜に当接している。The gate electrode plate 303 is in contact with the gate electrode film at p m Jim between each Nt layer on the center side JJ'P and each Nw layer on the peripheral side group.
第3図は第1図の一点鎖線で囲んだA部の拡大図である
。FIG. 3 is an enlarged view of section A surrounded by the dashed line in FIG.
外部電極106には第4図に示すように、環状の溝10
6aが設けられており、皿ばね304はこの溝106a
に収容されている。皿ばね304には座金305が装着
され、ゲート電極板303との間にマイカの絶縁板30
6、銅のゲート端子板307が設けられている。ゲート
電極板303のゲート電極膜205との当接面、ゲート
端子板307との当接面以外の個所はテフロン308で
被覆され、中間滑動板301,302との混触を防止し
ている。ゲート端子板307は外部電極106の溝10
6a内に収容されているので、外部電極106との混触
をさけるため、やはシテフロン309で被覆されている
。ゲート端子板307は第5図に示すように環状の当接
部307aと接続部307bとからなシ、接続部307
bは外部電極106の半径方向の溝106bに収容され
る。接続部307bには変形自在な接続体310の一端
が固着され、また他端は、セラミック筒101を貫通し
て設けられたゲー ドパイブ107と固着されている。As shown in FIG. 4, the external electrode 106 has an annular groove 10.
6a is provided, and the disc spring 304 is inserted into this groove 106a.
is housed in. A washer 305 is attached to the disc spring 304, and a mica insulating plate 30 is placed between it and the gate electrode plate 303.
6. A copper gate terminal plate 307 is provided. The portions of the gate electrode plate 303 other than the contact surface with the gate electrode film 205 and the contact surface with the gate terminal plate 307 are coated with Teflon 308 to prevent contact with the intermediate sliding plates 301 and 302. The gate terminal plate 307 is connected to the groove 10 of the external electrode 106.
Since it is housed in the internal electrode 6a, it is covered with Citeflon 309 to avoid contact with the external electrode 106. As shown in FIG. 5, the gate terminal plate 307 consists of an annular contact portion 307a and a connecting portion 307b.
b is accommodated in the radial groove 106b of the external electrode 106. One end of a deformable connector 310 is fixed to the connecting portion 307b, and the other end is fixed to the gate pipe 107 provided through the ceramic tube 101.
ゲー ドパ・fプ1()7からIU #;t、部307
bにがけて、絶縁性の熱収縮チ:】−一−グ:目1が
設けられている。Game dopa・fpu1()7 to IU #;t, part 307
An insulating heat-shrinkable mesh 1 is provided over b.
外部電極105,106間で圧接力が加えられた場合、
フランジ102〜104がたわんで、各部材間が当接l
〜、圧接曲中が加わる。この時、皿ばね304が用いら
れているため、ゲート電極膜205−ゲート電極板3o
3−ゲート端子板307間は環状な全面で均等な荷11
を受けて相互に接触する。一部で片当りがあり、」d触
不艮部分があると、その部分ては、ゲート端子板307
からゲート電極膜205間の電気抵抗が高くなって、ゲ
ート電流が充分に流れず、ターンオン、ターンオフの動
作不良を起すが、本発明でしょ皿ばねを用いているから
、円周方向でそのような動作不良はなく、均一な特性が
44すられる。When pressure contact force is applied between the external electrodes 105 and 106,
The flanges 102 to 104 are bent, and each member is in contact with each other.
~, press-contact bending is added. At this time, since the disc spring 304 is used, the gate electrode film 205 - the gate electrode plate 3o
Between 3 and the gate terminal plate 307 is a uniform load 11 on the entire annular surface.
and contact each other. If there is uneven contact in some parts and there is a part that cannot be touched, the gate terminal board 307
Since the electrical resistance between the gate electrode film 205 becomes high and the gate current does not flow sufficiently, causing malfunctions in turn-on and turn-off, the present invention uses a disc spring, so that such a problem is prevented in the circumferential direction. There are no malfunctions and the characteristics are uniform.
また、皿ばね3()4の座金305、絶縁板306各介
してのゲート端子板:(07、ゲ町1・電極板303へ
の当J妾1固所をそれらの1lll、l jl匂しあた
りにしていることによって、圧接荷重は幅方向でも均一
化される。In addition, the gate terminal plate through the washer 305 and insulating plate 306 of the disc spring 3 () 4: (07, Gemachi 1, electrode plate 303, J concubine 1 fixed place, those 1 lll, l jl smell By applying this to the same area, the pressure contact load is made uniform in the width direction as well.
そして、第3図のように、ゲート電極板303の一部も
外部電極106の溝106aに収容させておくと、中間
滑動板301,302の位置合せも可能であり、また、
製作作業も容易になる。As shown in FIG. 3, if a part of the gate electrode plate 303 is also housed in the groove 106a of the external electrode 106, the intermediate sliding plates 301 and 302 can be aligned.
Manufacturing work is also easier.
ゲート電極膜205に加わる荷重が均一であるので、荷
重集中による特性劣下が、半導体素子の破壊がなく、良
好な電気的、機械的特性を有している。Since the load applied to the gate electrode film 205 is uniform, there is no deterioration in characteristics due to load concentration, but the semiconductor element is not destroyed, and has good electrical and mechanical characteristics.
シリコン基体201と支持板202のろう付により、半
導体素子200が彎曲したとしても、ゲート電極膜20
5にアルミニウムのごとき軟質材ゲート電極板303と
してモリブデン、タングステンのごとき硬質材を用いて
おけば、ゲート電極板303は、そのゲート電極膜20
5に喰い込む。Even if the semiconductor element 200 is bent due to brazing the silicon substrate 201 and the support plate 202, the gate electrode film 20
If a hard material such as molybdenum or tungsten is used as the gate electrode plate 303, the gate electrode plate 303 will be made of a soft material such as aluminum.
Dig into 5.
この場合、皿ばねがゲート電極板303の幅中心のあた
シに圧接荷重を作用させていると、ゲート電極膜205
とゲート電極板3030片当シは少なく、良好な接触が
得られる。In this case, if the disc spring applies a pressure load to the center of the width of the gate electrode plate 303, the gate electrode film 205
There is little contact between the gate electrode plate 3030 and good contact.
本発明は以上の実施例に限らず、ド叱の態様でも実施可
能である。The present invention is not limited to the above-described embodiments, but can also be implemented in other forms.
(1) エミツタ層が多重同心群VC分かれて配li&
され、各群の間に制φ(1電極板が配置aされ一部いる
もの。。(1) The emitter layer is divided into multiple concentric group VCs and
and between each group there is a control φ (one electrode plate is placed a).
例えばエミツタ層が4H1放射同心状に配置され、第2
群と第3群の間に制御L11電極扱が配置aされ、第1
#と第211Ti 、第3群と第4群のエミツタ層に中
間滑動板がそれぞれ一括しで当接しているもの。For example, the emitter layer is arranged in a 4H1 radial concentric manner, and the second
A control L11 electrode is placed between the group and the third group, and the first
# and #211Ti, intermediate sliding plates are in contact with the emitter layers of the third and fourth groups, respectively.
(2)ベース層がエッチダウンされずに、エミツタ層と
同一平面上にあるもの。(2) The base layer is not etched down and is on the same plane as the emitter layer.
(3)エミッタ層−ベース層のpn接合がゾレーナ構造
となっているもの。(3) The pn junction between the emitter layer and the base layer has a solena structure.
(4)アノード側エミツタ層が隣接ベース層と共に他方
の主表面に露出し、アノード電極膜で短絡されているG
TO8
(5)エミッタj−が円周方向に弧状に配置されている
もの。(4) G in which the anode side emitter layer is exposed on the other main surface together with the adjacent base layer and short-circuited by the anode electrode film.
TO8 (5) Emitters j- are arranged in an arc shape in the circumferential direction.
以上説明したように、本発明によれば、圧接荷重が均一
に加わり、良好な電気的、機械的%性を備えた半導体装
置を得ることができる。As explained above, according to the present invention, it is possible to obtain a semiconductor device in which a pressure contact load is applied uniformly and has good electrical and mechanical properties.
第1図は本発明の一実施例を示すGTOの断面図、第2
図は第1図に示すGTOの半導体素子を示してお、?、
(a)はシリコン基体の平面図、(b)は(a)の1−
1切断線に沿った断面図、第3図は第1図の一点鎖線で
囲んだA部分の拡大図、第4図は第1図の()TOで用
いられている外部電極の平面図、第5図は第1図のGT
Oで用いられているゲート端子板の半面図である。
】00・・・気密容器、101・・・セラミック筒、1
02〜104・・・フランジ、105,106・・・外
部電極、107・・・ゲートパイプ、201・・・シリ
コン基体、204・・・カソード電極膜、205・・・
ゲート電極膜、301.302・・・中間滑動板、30
3・・・ゲート電+ix&、304・・・皿バネ、30
7・・・ゲート端子板。
代理人 弁理士 高橋明夫
(11)
第10
第2図c月
第2図/I))
部3図
第1頁の続き
0発 明 者 桜 1) 修 六 日立市幸町3”内
159−Fig. 1 is a sectional view of a GTO showing one embodiment of the present invention;
The figure shows the semiconductor element of the GTO shown in Figure 1. ,
(a) is a plan view of the silicon substrate, (b) is 1- of (a)
1 is a cross-sectional view along cutting line 1, FIG. 3 is an enlarged view of part A surrounded by the dashed line in FIG. 1, FIG. 4 is a plan view of the external electrode used in ()TO in FIG. Figure 5 shows the GT in Figure 1.
It is a half view of the gate terminal board used in O. ]00...Airtight container, 101...Ceramic tube, 1
02-104... Flange, 105, 106... External electrode, 107... Gate pipe, 201... Silicon base, 204... Cathode electrode film, 205...
Gate electrode film, 301.302... intermediate sliding plate, 30
3...Gate electric +ix&, 304...Disc spring, 30
7...Gate terminal board. Agent Patent Attorney Akio Takahashi (11) 10 Figure 2 C Figure 2/I)) Continuation of Part 3 Figure 1 Page 1 Inventor Sakura 1) 159-3, Saiwai-cho, Hitachi City
Claims (1)
なる少くとも3個の半導体層を有しており、一方の主表
面には複数の短冊状最外層と各最外層に隣接する中間層
が露出し、各最外層は一方の主表面において同心状に群
をなして配置されておシ、各最外層には一方の主電極膜
がそれぞれ低抵抗接触されておシ、隣接中間層には各最
外層を取囲むように制御電極膜が低抵抗接触し、同心状
配置の各群の最外層の主電極膜には同心的に配置された
環状の中間滑動板がそれぞれ当接し、同心状配置の最外
層の各群の間の制御電極膜に環状の制御電極板が各環状
中間滑動板の間を通してそれらと同心的に配置されて当
接し、各環状中間滑動板には直接、そして環状制御電極
板には皿ばねを介して一方の外部電極が当接し、皿ばね
は環状制御電極の 板の幅中心jあたりに当接され、他方主表面の他方の主
電極に他方の外部電極が低抵抗接触し、両列部電極は絶
縁筒の開口にそれぞJ【気密かつ可撓的に設けられて半
導体基体を収納する気密容器を形成しており、環状制御
電極板口絶縁面會貝通して設けられた外部11jU呻電
極の容器内端と接続されていることを特徴とする半導体
層1自1゜2、上記第1項において、各環状中間層MI
11板と環状制御11L極板の間は制御電極板に設けた
絶縁′吻で絶縁され、皿ばねと制偵11電極板の間は両
者間に設けた環状絶縁板で絶縁されていることf:%徴
とする半導体装11゜[Claims] 1. The semiconductor substrate has at least three semiconductor layers having different conductivity types between its pair of main surfaces, and a plurality of strip-shaped outermost layers on one main surface. The intermediate layer adjacent to each outermost layer is exposed, and each outermost layer is arranged in a concentric group on one main surface, and one main electrode film is in low resistance contact with each outermost layer. A control electrode film is in low-resistance contact with the adjacent intermediate layer so as to surround each outermost layer, and a concentrically arranged annular main electrode film is in contact with the outermost main electrode film of each group in a concentric arrangement. An annular control electrode plate passes between each annular intermediate sliding plate and abuts the control electrode film between each group of the outermost layer, and an annular control electrode plate is arranged between and concentrically with each of the intermediate sliding plates. One external electrode contacts the sliding plate directly and the annular control electrode plate via a disc spring, and the disc spring contacts the width center j of the annular control electrode plate, and The other external electrode is in low-resistance contact with the main electrode, and both row electrodes are provided airtightly and flexibly in the opening of the insulating cylinder to form an airtight container for storing the semiconductor substrate. In the above item 1, each annular intermediate layer MI is characterized in that it is connected to the inner end of the container of the external electrode 11jU provided through the insulating surface of the control electrode plate opening.
The plate 11 and the annular control 11L electrode plate are insulated by an insulating proboscis provided on the control electrode plate, and the disc spring and the control 11 electrode plate are insulated by an annular insulating plate provided between them. Semiconductor device 11°
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58163141A JPS6055633A (en) | 1983-09-07 | 1983-09-07 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58163141A JPS6055633A (en) | 1983-09-07 | 1983-09-07 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6055633A true JPS6055633A (en) | 1985-03-30 |
Family
ID=15767988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58163141A Pending JPS6055633A (en) | 1983-09-07 | 1983-09-07 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6055633A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60150670A (en) * | 1984-01-17 | 1985-08-08 | Mitsubishi Electric Corp | Semiconductor device |
JPS60194565A (en) * | 1984-03-15 | 1985-10-03 | Mitsubishi Electric Corp | Semiconductor device |
JPS624330A (en) * | 1985-06-28 | 1987-01-10 | Mitsubishi Electric Corp | Semiconductor device |
JPS62229847A (en) * | 1986-03-29 | 1987-10-08 | Mitsubishi Electric Corp | Semiconductor device |
JPH01129422A (en) * | 1987-11-16 | 1989-05-22 | Fuji Electric Co Ltd | Thyristor |
US5093281A (en) * | 1988-07-13 | 1992-03-03 | Mitsubishi Denki Kabushiki Kaisha | method for manufacturing semiconductor devices |
US5777351A (en) * | 1995-05-31 | 1998-07-07 | Mitsubishi Denki Kabushiki Kaisha | Compression bonded type semiconductor element and semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57201077A (en) * | 1981-06-05 | 1982-12-09 | Hitachi Ltd | Semiconductor switching device |
JPS58148433A (en) * | 1982-02-26 | 1983-09-03 | Mitsubishi Electric Corp | Semiconductor device |
-
1983
- 1983-09-07 JP JP58163141A patent/JPS6055633A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57201077A (en) * | 1981-06-05 | 1982-12-09 | Hitachi Ltd | Semiconductor switching device |
JPS58148433A (en) * | 1982-02-26 | 1983-09-03 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60150670A (en) * | 1984-01-17 | 1985-08-08 | Mitsubishi Electric Corp | Semiconductor device |
JPS60194565A (en) * | 1984-03-15 | 1985-10-03 | Mitsubishi Electric Corp | Semiconductor device |
JPH0530076B2 (en) * | 1984-03-15 | 1993-05-07 | Mitsubishi Electric Corp | |
JPS624330A (en) * | 1985-06-28 | 1987-01-10 | Mitsubishi Electric Corp | Semiconductor device |
JPS62229847A (en) * | 1986-03-29 | 1987-10-08 | Mitsubishi Electric Corp | Semiconductor device |
JPH01129422A (en) * | 1987-11-16 | 1989-05-22 | Fuji Electric Co Ltd | Thyristor |
US5093281A (en) * | 1988-07-13 | 1992-03-03 | Mitsubishi Denki Kabushiki Kaisha | method for manufacturing semiconductor devices |
US5777351A (en) * | 1995-05-31 | 1998-07-07 | Mitsubishi Denki Kabushiki Kaisha | Compression bonded type semiconductor element and semiconductor device |
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