JPS60150670A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60150670A
JPS60150670A JP59006664A JP666484A JPS60150670A JP S60150670 A JPS60150670 A JP S60150670A JP 59006664 A JP59006664 A JP 59006664A JP 666484 A JP666484 A JP 666484A JP S60150670 A JPS60150670 A JP S60150670A
Authority
JP
Japan
Prior art keywords
electrode plate
electrode
plate
gate electrode
main
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59006664A
Other languages
Japanese (ja)
Inventor
Hiroyasu Hagino
萩野　浩靖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59006664A priority Critical patent/JPS60150670A/en
Priority to EP19840308970 priority patent/EP0158749A1/en
Publication of JPS60150670A publication Critical patent/JPS60150670A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

Abstract

PURPOSE:To obtain excellent pressure welding without trouble even when there are, more or less, dimensional errors on finishing in the thickness of each electrode plate and an insulating plate by pushing the insulating plate through a Bellville spring by a main-electrode metallic block. CONSTITUTION:Recessed sections are formed to sections opposite to ceramic rings 17 of a cathode copper block 19, and the ceramic rings 17 and gate electrode plates 15 are pushed against gate electrodes 11 in a GTO chip 13 through plain washers 22 and Bellville springs 23 inserted into the recessed sections. According to such constitution, the characteristic conditions of the Bellville spring 23 are brought to adequate ones, and the dispersion of the size of parts, such as the gate electrode plate 15, the ceramic ring 17 is absorbed. When the Bellville spring 23 is designed in a region of loading characteristic conditions of h/s=1.0-1.4 shown in solid lines in relationship such as one of loading and deflection using the ratio h/s of the height h to thickness s of the Bellville spring 23 as a parameter, the dispersion of size generated by precison on the processing of parts can be absorbed sufficiently.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体基体の一方の主面に第１の主電極と制
御電極とが設けられ、他方の主面ｆＣ第２の主電極が形
成され文形の半導体装置に係り、特にその制御電極端子
の収り出し構造の改良に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention provides a semiconductor substrate in which a first main electrode and a control electrode are provided on one main surface, and a second main electrode is formed on the other main surface fC. The present invention relates to a conventional semiconductor device, and in particular to an improvement in the structure for disposing a control electrode terminal therein.

以下、ゲートターンオフサイリスタ（ＧＴＯ）　を例に
とって説明する。A gate turn-off thyristor (GTO) will be explained below as an example.

〔従来技術〕[Prior art]

第１図は小電流容量の一般的なＧＴＯウェーハのカソー
ド側主面の平面図で、ｉｌｌ制御電極、＋２１　Ｆｉミ
ニミッタアイランド形成された第１の主電極であるカソ
ード電極である。電流容置の小さい場合ＶＣは、この工
うにセンターから制御電極＋１１を収り出すのが通常で
ある。しかし、最近ＧＴＯＯ大電流入電ともなって、制
御電極の収り出し点からのエミッタアイランド各部への
距離の均一性を改善するために、＃！２図に示す！５Ｋ
、多重に設けた工ミッタアイランドの電極（１２ａ）、
　（１２ｂ）の中間から制御電極（Ｊ２を下「中間制御
電極」という。）（川を取り出す方式が採用されるよう
になってき７ｊａ第３図はこの方式ＴＩｃよる従来の中
間制御電極の収り出し構造を一部破断して示す斜視図で
、（１３はｐｎｐｎ　４層構造のＧＴＯチップでゲート
成極（１１）およびカソード電極（１２ａ）、　（１２
ｂ）　ｉアルミニウム（Ａｔ）の蒸着等に裏って形成さ
れる。θ４１は陽極電極板、Ｏｏはリング状のゲート（
制御）電極板、（１６ａ）、　（１６ｂ）はカソード（
陰極）電極板、０７１はゲート電極板（ｌ［ｉｌの上に
ろう付けして設けられカソード電極板Ｈとの間の絶縁全
保持するセラミックリング、（１８１は銀（Ａｇ　）な
どの材料からなり、ゲート電極板（１６）にろう付けな
どの方法で固着され定ゲート外部引出し用ゲートリード
である。FIG. 1 is a plan view of the main surface on the cathode side of a general GTO wafer having a small current capacity, and shows the cathode electrode which is the first main electrode on which an ill control electrode and a +21 Fi minimitter island are formed. When the current capacity of the VC is small, the control electrode +11 is usually inserted from the center of the VC. However, recently, with the introduction of large current into GTOO, #! Shown in Figure 2! 5K
, multiple electrodes of the emitter island (12a),
(12b) Control electrode from the middle (J2 is called the "intermediate control electrode") (J2 is called the "intermediate control electrode"). (13 is a GTO chip with a pnpn four-layer structure, with a gate polarization (11), a cathode electrode (12a), (12)
b) Formed behind the vapor deposition of aluminum (At), etc. θ41 is the anode electrode plate, Oo is the ring-shaped gate (
control) electrode plates, (16a) and (16b) are cathodes (
The cathode) electrode plate 071 is a ceramic ring that is brazed onto the gate electrode plate (I) and maintains complete insulation between it and the cathode electrode plate H. (181 is made of a material such as silver (Ag). , which is fixed to the gate electrode plate (16) by a method such as brazing, and is a gate lead for external extraction of a fixed gate.

第４図はこの従来例のパッケージ分解組立断面図で、第
３図と同一符号は同等部分を示す。第４図（ａ）　Ｋ示
すＨに陰極鋼ブロックで、第４図（ｂ）Ｔ／ｉカソード
電極板（１５ａ）、　（１ｆ３ｂ）、ゲート電極板（＋
５１．セラミックリング同およびゲートリード９８１の
組立体、第４図（ｃ）はＧＴＯチップα沸、第４図れ）
は陽極電極板Ｑ４１ｅ示している。ところで、第４図（
ｂｌに示す組立体ｔ／ｉ第４図（ａ）　ＶＣ示す陰極銅
ブロックＱ９）ノ下面ＩＣ，１つてカソード電極板ｆ１
６ａ）、　（１６ｂ）　′Ｊ６Ｌびゲート電極板（Ｉ６
）を押圧してＧＴＯチップ（１３上に圧接するようにな
っている。従って、カソード電極板（１６ａ）、　（１
６ｂ）の下面（イ）およびゲート電極板ｔ１５１の下面
、並びにカソード電極板（ｍａ）、　（１６ｂ）の上面
２ηおよびゲート電極板（１５１を押圧するセラミック
リングαηの上面がそれぞれ同一平面にあることが重要
である。第５図は従来構造において発生し易い状態を示
す断面図で、第５図（ａ）Ｋ示すようにゲート電極板−
の下面またはセラミックリングＯηの上面がカソード電
極板（１６ａ）、　（１６ｂｌの主面より凹んでいる場
合Ｋｄゲート電極板（１６）のゲート電極（＋１１への
圧接が不十分となり、オーミック接触がとれなくなる。FIG. 4 is an exploded sectional view of this conventional package, in which the same reference numerals as in FIG. 3 indicate the same parts. Figure 4 (a) H shown in K is a cathode steel block, Figure 4 (b) T/i cathode electrode plate (15a), (1f3b), gate electrode plate (+
51. The assembly of the ceramic ring and gate lead 981, Fig. 4(c) is the GTO chip α, Fig. 4(c))
indicates the anode electrode plate Q41e. By the way, Figure 4 (
Assembly t/i shown in bl Figure 4 (a) Bottom surface of cathode copper block Q9) shown in VC, one cathode electrode plate f1
6a), (16b) 'J6L and gate electrode plate (I6
) is pressed onto the GTO chip (13). Therefore, the cathode electrode plate (16a), (1
The lower surface (a) of 6b) and the lower surface of the gate electrode plate t151, the upper surface 2η of the cathode electrode plate (ma), (16b) and the upper surface of the ceramic ring αη that presses the gate electrode plate (151) are on the same plane. FIG. 5 is a cross-sectional view showing a situation that is likely to occur in a conventional structure. As shown in FIG. 5(a)K, the gate electrode plate-
If the bottom surface of the ceramic ring Oη or the top surface of the ceramic ring Oη is recessed from the main surface of the cathode electrode plate (16a) (16bl), the pressure contact of the Kd gate electrode plate (16) to the gate electrode (+11) will be insufficient and ohmic contact cannot be established. It disappears.

ま几、第５図（ｂ）に示すように、ゲート鑵極板αｍの
下面をカン１６ｂ）の上面ｑυ工りも凸出し定状態では
、これらを陰極鋼ブロックａ喝に工ってＧＴＯチッグｌ
ｌ３ＩＶＣ加圧接すると、セラミックリングＵηが割れ
て電気絶縁機能が劣化するなどの問題がある。そして、
通常、セラミックリングａηを含むゲート電極板す５）
およびカソード４極板（１６ａ）、　（１６ｂ）　＃’
ｊ別イｖＡに作られ几上で組み会わされるので、両者間
の上下両面をそれぞれ一致させることは容易でない。As shown in Fig. 5(b), when the lower surface of the gate electrode plate αm is also protruded from the upper surface qυ of the can 16b), these are machined into the cathode steel block a and the GTO chip is l
13IVC pressure welding causes problems such as cracking of the ceramic ring Uη and deterioration of the electrical insulation function. and,
Typically, a gate electrode plate containing a ceramic ring aη5)
and cathode quadrupole plate (16a), (16b) #'
Since they are made separately and assembled together on a platform, it is not easy to match the top and bottom surfaces of the two.

〔発明の概要〕[Summary of the invention]

この発明ｉｊ以上のような点ＶＣ鑑みてなされｔもので
、陰極銅ブロックＫｊつてカソード成極板は直接、ゲー
ト電極板は弾性体を介して半導体チップに押圧すること
によって両電極板間１ｃ　１９１さの差異があっても正
常な圧接が得られる半導体装置の構成を提供するもので
ある。This invention was made in view of the above-mentioned points, and the cathode copper block Kj is pressed directly against the cathode polarization plate, and the gate electrode plate is pressed against the semiconductor chip through an elastic body, thereby forming a gap between the two electrode plates 1c191. The present invention provides a structure of a semiconductor device that can obtain normal pressure contact even if there is a difference in thickness.

〔発明の実施例〕[Embodiments of the invention]

第６図はこの発明の一実施例の構成を示す断面図で、従
来例と同一符号は同等部分？示し、その説明は重複を避
けるために省略する。この実施例では、陰極銅ブロック
（Ｉ場のセラミックリングＱ７１＃／ｃ対向する部分に
凹部が設けられ、この凹部に挿入され之平座金（２）お
工び皿ばね＠を介してセラミックリング１７１おＬびゲ
ート電極板（１５）全ＧＴＯチップＱ３１のゲート電極
（Ｉｌｌ　Ｖｃ弁押圧るようになっている。FIG. 6 is a cross-sectional view showing the configuration of an embodiment of the present invention, and the same reference numerals as in the conventional example indicate the same parts. The description is omitted to avoid duplication. In this embodiment, a recess is provided in the opposing part of the cathode copper block (I-field ceramic ring Q71#/c), and a flat washer (2) is inserted into the recess. L and gate electrode plate (15) are designed to press the gate electrode (Ill Vc valve) of all GTO chips Q31.

このような構成にすることによって、皿ばね（２）の特
性条件を適当にしてゲート電極板（＋５１　、セラミッ
クリング０７１などの部品の寸法のばらつき（通常の機
械加工では±１０〜１００１程ＪＪｔ１．）を吸収させ
ることは容易である。By adopting such a configuration, the characteristic conditions of the disc spring (2) can be appropriately set, and the variations in dimensions of parts such as the gate electrode plate (+51) and the ceramic ring 071 (with normal machining, JJt1. ) is easy to absorb.

第７図は皿はねの断面図、第８図はその加重曲線図で、
第７図に示す皿ばねの高さｈと肉厚ｅとの比ｈ／ｅ　ｌ
ｒパラメータとして加重と几わみとの関係を示している
。第８図の実線で示す加重特性条件（ｈ／θ−１，０〜
１．４）の領域で皿ばねを設計すれば、部品の加工精度
に工って生じる寸法のばらつきを十分吸収することが可
能である。Figure 7 is a cross-sectional view of the countersunk spring, Figure 8 is its weighted curve diagram,
The ratio h/e l of the height h and wall thickness e of the disc spring shown in Fig. 7
The relationship between weight and sharpness is shown as the r parameter. Weighted characteristic conditions (h/θ-1,0~
If a disc spring is designed in the region 1.4), it is possible to sufficiently absorb dimensional variations caused by machining accuracy of parts.

ま几、ゲート電極部分の圧接圧力が強すぎるとセラミッ
クリング（＋７１が割れ之り、長期の通電ＶＣよってゲ
ート電極板０５）とゲート電極（１１）とがくつつき。However, if the contact pressure on the gate electrode part is too strong, the ceramic ring (+71) will crack, and due to long-term energization, the gate electrode plate 05) and gate electrode (11) will crack.

素子破壊を招く原因となる。また、圧接圧力か弱すぎる
と、ゲート電極板０５１とゲート電極（川との間の接触
抵抗が太きくなり、通電発熱？生じ、熱疲労、ゲート通
電能力低下ＶＣよって素子破ａ！を招く原因となるので
、この圧接圧力が適当な値ＶＣなるように設計すること
が要求される０適当な圧接圧力としては単位面積あたり
８０〜２００ｋｇが一般的である。素子の総圧接圧力は
＋４ｔｈ作頭眠の面積によって決定さねるので、ゲート
電極板（１６）のゲート電極（１１）への当接面積が適
当な値になるよう設計する必要がある。第６図の平座金
＠は皿ばね＠とセラミックリング０７］お工び陰極鋼ブ
ロック０９１との接触を安定にする定めのものである。This may cause element destruction. In addition, if the contact pressure is too weak, the contact resistance between the gate electrode plate 051 and the gate electrode (river) will increase, causing heat generation due to energization, thermal fatigue, and a decrease in gate energization capacity VC, which may lead to element failure. Therefore, it is required to design so that this contact pressure is an appropriate value VC.The appropriate contact pressure is generally 80 to 200 kg per unit area.The total contact pressure of the element is +4th Since the contact area of the gate electrode plate (16) to the gate electrode (11) is determined by the area of the gate electrode (11), it is necessary to design it so that the contact area of the gate electrode plate (16) to the gate electrode (11) is an appropriate value. and the ceramic ring 07] are designed to stabilize the contact with the fabricated cathode steel block 091.

なお、このような構造にする定めに、ゲートリードθ（
２）はカソード電極板（１６１Ｌ）を貞通し、ノ（ツケ
ージ絶縁筒（ハ）を貫通して引き出されている。Note that in order to create such a structure, the gate lead θ(
2) passes through the cathode electrode plate (161L) and is drawn out through the cage insulating tube (c).

以−ヒ、ＧＴＯの場合を例にとって説明したが、一方の
主面に第１の主電極と制御電極とを有する半導体装置一
般にこの発Ｉｆｌは適用できる。Although the case of GTO has been explained below as an example, this generation Ifl can be applied to general semiconductor devices having a first main electrode and a control electrode on one main surface.

〔発明の効果〕〔Effect of the invention〕

この発明では半導体基体の一方の主面上に第１の主′＠
極と’＋ｔｉｌＩ御電極とが膜電極れ、上記第１０主電
極上に主電極板をその上から圧接する主電極金属ブロッ
クが同時に絶縁板を介して制御電極板を上記制−市極上
に圧接する工うＶｃ構成された半導体装置において、Ｌ
肥土電極金属ブロックが皿ばねを介して上記絶縁板を押
圧する工うにし九ので、各電極板および絶縁板の厚さに
多少の仕上げ寸法誤差があっても、支障なく良好な圧接
が得られる。In this invention, a first main body is formed on one main surface of a semiconductor substrate.
The main electrode metal block presses the main electrode plate onto the tenth main electrode from above, and simultaneously presses the control electrode plate onto the control electrode through the insulating plate. In a semiconductor device configured with Vc, L
Since the soil electrode metal block presses the insulating plate through the disc spring, good pressure contact can be achieved without any problem even if there is some finishing dimensional error in the thickness of each electrode plate and insulating plate. It will be done.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は小電流各社の一般的なＧＴＯウェーハのカソー
ド側主面の平面図、第２図は中間制御電極構造の電力用
ＧＴＯのカソード側主面の平面図、第３図は中間制御電
極構造の従来のＧＴＯの構成音一部破断して示す斜視図
、第４図はこの従来例のパッケージ分解組立断面図、第
５図はこの従来構造において発生し易い状態を示す断面
図、第６図はこの発明の一実施例の構成を示す断面図、
第７図は皿ばねの断面図、第８図はその加重特性図であ
る。 図において、（１１）は制御電極、（１２ａ）、　（１
，２ｂ）は第１の主゛鴫極（カソード電極）、０渇けＧ
ＴＯチップ（半導体基体）　、（＋ｓ＋ｈ制御電極板、
（１６ａ）、　（１６ｂ）　ｔｄ第１の主電極板、吻は
セラミックリング（絶縁板）、０匂は陰極銅ブロック（
第１主電極金属プロ゛ンク）、四は皿はねである。 なお、図中、同一符号は同一ま几は相当部分を示す。 代理人　大岩増雄 第１図 第２図 第３図 第４図Figure 1 is a plan view of the main surface on the cathode side of a typical GTO wafer from various small current companies, Figure 2 is a plan view of the main surface on the cathode side of a power GTO with an intermediate control electrode structure, and Figure 3 is a plan view of the main surface on the cathode side of a typical GTO wafer from various small current companies. 4 is an exploded cross-sectional view of the package of this conventional example; FIG. 5 is a sectional view showing conditions that are likely to occur in this conventional structure; FIG. The figure is a sectional view showing the configuration of an embodiment of the present invention.
FIG. 7 is a sectional view of the disc spring, and FIG. 8 is a load characteristic diagram thereof. In the figure, (11) is a control electrode, (12a), (1
, 2b) is the first main electrode (cathode electrode), 0 G
TO chip (semiconductor substrate), (+s+h control electrode plate,
(16a), (16b) td first main electrode plate, snout is ceramic ring (insulating plate), zero odor is cathode copper block (
The first main electrode metal block) and the fourth are countersunks. In addition, in the figures, the same reference numerals indicate corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 4

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基体の一方の主面上ＶＣ２つの領域に分割
されて第１の主電極が形成され、上記第１の主電極の２
つの領域の間に制御電極が形成され、上記第１の主電極
上に第１の主電極板をその上から圧接する第１の主電極
金属ブロックが同時に絶縁板を介して制御電極板を上記
制＃電極上に圧接する工うに構成されたものにおいて、
上記第１の主電極金属ブロックが皿ばねを介して上記絶
縁板を押圧するようにしたことを特徴とする半導体装置
。(1) A first main electrode is formed by dividing VC into two regions on one main surface of the semiconductor substrate, and two regions of the first main electrode are formed.
A control electrode is formed between the two regions, and a first main electrode metal block press-contacts the first main electrode plate onto the first main electrode from above, and simultaneously connects the control electrode plate above the first main electrode via an insulating plate. In a device configured to be pressure-contacted onto a control electrode,
A semiconductor device characterized in that the first main electrode metal block presses the insulating plate via a disc spring. （２）第１の主電極は円形の第１の領域とこれを囲む中
空円状の第２の領域とに分割され、制御電極は上記内領
域間に円環状に形成され几ことを特徴とする特許請求の
範囲第１項記載の半導体装置。(2) The first main electrode is divided into a circular first region and a hollow circular second region surrounding the first region, and the control electrode is formed in an annular shape between the inner regions. A semiconductor device according to claim 1. （３）　絶縁板は制御電極板にろう付は固着された仁と
を特徴とする特許請求の範囲第１項または第２項記載の
半導体装置。(3) The semiconductor device according to claim 1 or 2, characterized in that the insulating plate is a piece that is brazed or fixed to the control electrode plate.
JP59006664A 1984-01-17 1984-01-17 Semiconductor device Pending JPS60150670A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59006664A JPS60150670A (en) 1984-01-17 1984-01-17 Semiconductor device
EP19840308970 EP0158749A1 (en) 1984-01-17 1984-12-20 Semiconducteur device having pressure loaded members

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59006664A JPS60150670A (en) 1984-01-17 1984-01-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60150670A true JPS60150670A (en) 1985-08-08

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ID=11644643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59006664A Pending JPS60150670A (en) 1984-01-17 1984-01-17 Semiconductor device

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Country Link
EP (1) EP0158749A1 (en)
JP (1) JPS60150670A (en)

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EP0220698A2 (en) * 1985-10-25 1987-05-06 Siemens Aktiengesellschaft Thyristor with a disc-shaped housing
CN101916745A (en) * 2010-05-31 2010-12-15 江阴市赛英电子有限公司 Novel plate crimped dual-chip encapsulated ceramic package

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JPS60194565A (en) * 1984-03-15 1985-10-03 Mitsubishi Electric Corp Semiconductor device
JPS61113249A (en) * 1984-11-08 1986-05-31 Mitsubishi Electric Corp Semiconductor device
JPS62269322A (en) * 1986-05-17 1987-11-21 Toshiba Corp Power semiconductor device
EP0287770B1 (en) * 1987-03-25 1993-05-05 BBC Brown Boveri AG Semiconductor component having a control electrode
DE3826820A1 (en) * 1987-09-28 1989-04-06 Asea Brown Boveri PERFORMANCE SEMICONDUCTOR ELEMENT
JP2502386B2 (en) * 1989-04-11 1996-05-29 富士電機株式会社 Semiconductor device
JP3471880B2 (en) * 1994-02-23 2003-12-02 三菱電機株式会社 Pressure contact type semiconductor device
DE19530264A1 (en) * 1995-08-17 1997-02-20 Abb Management Ag Power semiconductor module
DE10041112B4 (en) * 2000-08-22 2006-05-24 eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG insulating

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0220698A2 (en) * 1985-10-25 1987-05-06 Siemens Aktiengesellschaft Thyristor with a disc-shaped housing
CN101916745A (en) * 2010-05-31 2010-12-15 江阴市赛英电子有限公司 Novel plate crimped dual-chip encapsulated ceramic package

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