GB2168529A - Electrical contacts for semiconductor devices - Google Patents
Electrical contacts for semiconductor devices Download PDFInfo
- Publication number
- GB2168529A GB2168529A GB8431952A GB8431952A GB2168529A GB 2168529 A GB2168529 A GB 2168529A GB 8431952 A GB8431952 A GB 8431952A GB 8431952 A GB8431952 A GB 8431952A GB 2168529 A GB2168529 A GB 2168529A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- contact
- electrical
- contact member
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Thyristors (AREA)
Abstract
In a contact arrangement providing a very low thermal and electrical impedance path to a semiconductor device, eg a thyristor, a compliant material (11), such as indium is squeezed between a contoured upper surface of the device and a pressure plate (8) so that the metal is forced into close contact with the electrodes (7). An insulating film (10) protects those areas to which electrical contact is not required, but allows good thermal contact. <IMAGE>
Description
SPECIFICATION
Electrical contact arrangements
This invention relates to an electrical contact arrangement in which the electrical contact also provides a thermal path typically to some form of heat sink. Such an arrangement is commonly used in the mounting and construction of electronic devices and components in order to prevent excessive temperatures occurring as the result of internal generation of heat. It is particularly important to provide a low impedance thermal path between a high power semiconductor device and a heat sink, as excessively high temperatures can seriousy and permanently damage semiconductors.The use of a pressure contact in which an electrically conductive member is held against an electrode surface of a device or component can result in a good thermal path being formed in addition to the formation of a good electrical path provided that the contact area is sufficiently great. It can, however, be difficult to provide a very good thermal contact to an electrode surface which is of a nonunitary or segmented nature.
The present invention seeks to provide an improved electrical contact arrangement which is capable of exhibiting very good thermal conduction properties.
According to a first aspect of this invention an electrical contact arrangement includes an electrical device having a localised electrode surface which is bounded by a patterned electrically insulating material; and a layer of compliant electrically and thermally conductive material which overlies said electrode surface and said insulating material so that its inner surface is profiled so as to be in intimate contact therewith, the outer surface of the layer being such as to cooperate with a pressure contact member.
According to a second aspect of this invention, a method of forming an electrical and thermal connection between an electrical device and a pressure contact member includes the steps of: forming at a surface of the electrical device an electrode at an area which is to be electrically connected to said contact member and an electrically insulating barrier at an area which is not to be electrically connected to said contact member; forming a layer of electrically and thermally conductive compliant material over said surface; and bringing said pressure contact member into contact with the outer surface of said layer so as to deform its inner surface into intimate contact with said electrode and said insulating barrier.
The invention is further described by way of example with reference to the accompanying drawings in which:
Figures 1 and 2 show alternative known ways of making contact to a thyristor, and
Figure 3 shows the contact arrangement in accordance with the invention.
Referring to Fig. 1, there is shown therein a thyristor 1 which is typically a four-layer semiconductor switching device. It consists of an anode layer 2 of Ptype silicon which is in contact with an electrically conductive and thermally conductive contact member 3. In practice, the underside of the Ptype anode 2 is provided with a thin surface metalisation 4 (which constitutes an anode electrode) to which it is permanently bonded, whereas the connection between the layer 4 and the contact member 3 is merely one of pressure, i.e.
there is no permanent bonding, so that the thyristor can be readily removed from the contact member 3. The upper surface of the thyristor consists partly of gate electrodes 5 mounted at different locations on a Ptype silicon region on which raised N+ emitter regions 6 are provided. The emitter regions are provided with cathode electrodes 7 in well known manner, and a contact member 8 is held against the electrodes 7 to make electrical connection therewith.
In operation very large currents pass through the anode and cathode electrodes and it is important to provide a very low impedance electrical path to the two contact members 3 and 8. Relatively low currents are applied to the gate electrodes 5. The thyristor shown is one which consists of a heavily interdigitated set of emitter and gate contacts, and such an interdigitation makes it very difficult to provide a satisfactory pressure contact.
An alternative known thyristor is shown in
Fig. 2 in which the emitter regions 6 are now flush with the Ptype region carrying the gate electrodes 5. A similar pressure contact member 8 is used but it carries projections 9 corresponding to the outline of the cathode electrodes 7 so that when the member 8 with its projections is brought into contact with the upper surface of the thyristor only the cathode electrodes make an electrical connection therewith.
It will be appreciated that in the arrangements shown in Figs. 1 and 2 there is a poor thermal contact to the upper cathode face of the thyristor and this can result in the thermal impedance of the cathode sides being twice that of the lower anode face where it will be seen that the whole of the surface is contacted by the contact member 3. An additional disadvantage is that because the emitter contact area is small, the cathode electrode metalisation is subject to a relatively high pressure, whereas of necessity, the anode face is subjected to a much lower pressure as its area is much greater. If the pressure on the cathode face is reduced to prevent problems such as creep or fracture of the cathode or emitter materials, then the pressure on the anode face may be so low as to give poor thermal or electrical contact.
Referring to Fig. 3, there is shown therein an electrical contact arrangement in accordance with the present invention, like parts are given the same reference numerals as in
Fig. 1. The anode contact arrangement is the same as is used in the conventional devices shown in Figs. 1 and 2, but the arrangement used to effect the cathode connection is rather different. The connections to the gate electrodes 5 are effected by use of tracks on the upper surface of the layer which carries the gate electrodes. Thereafter, a very thin electrically insulating layer of material 10 is formed over the entire upper surface of the device except for windows which are left coinciding with the position of the cathode electrodes 7.Either a continuous layer can be formed in which the windows are subsequently formed by selective removal of material 10, or the windows can be left open when the layer is produced. A suitable insulating material 10 is alumina or polyimide. Subsequently, a continuous layer 11 of soft compliant material which is electrically and thermally conductive is placed over the electrodes 7 and the material 10. This layer 11 may be for example, aluminium, silver of indium. Indium may be preferred as it is a very soft material, but it does not have quite such a good thermal conductivity as the other two metals. The pressure contact member 8 is then brought down into contact with the outer surface 12 of the layer, so as to bear against it and force its inner layer 13 into intimate contact with the upper surface of the thyristor. A typical pressure used is about 1 ton per square inch.As the material is soft and compliant, it readily deforms so as to give an excellent contact, although it may not be forced fully into deep recesses or acute corners. This layer 11 has a number of advantages. Firstly, it provides an excellent thermal path to all regions of the thyristor device, the thickness of the insulating material 10 being very thin so as to not significantly impair the thermal conduction but constituting an insulating barrier to electrically isolate the underlying semiconductor regions. Secondly, the electrical impedance is very low, since the material 11 has a very large area and being compliant makes an excellent electrical contact with the gate electrodes 7. Thirdly, as the material 11 extends over the whole of the surface of the thyristor, the pressure which it exerts upon the cathode face is the same as that exerted upon the lower anode face.
Although the invention has been described with particular reference to just one surface of a thyristor device it will be appreciated that it is applicable to other arrangements where selective electrical contact is to be made to localised electrode regions whilst maintaining good thermal contact with a heat sink and whilst distributing pressure applied by means of a pressure contact.
Claims (8)
1. An electrical contact arrangement including an electrical device having a localised electrode surface which is bounded by a patterned electrically insulating material; and a layer of compliant electrically and thermally conductive material which overlies said electrode surface and said insulating material so that its inner surface is profiled so as to be in intimate contact therewith, the outer surface of the layer being such as to cooperate with a pressure contact member.
2. A method of forming an electrical and thermal connection between an electrical device and a pressure contact member including the steps of: forming at a surface of the electrical device an electrode at an area which is to be electrically connected to said contact member and an electricaly insulating barrier at an area which is not to be electrically connected to said contact member; forming a layer of electrically and thermally conductive compliant material over said surface; and bringing said pressure contact member into contact with the outer surface of said layer so as to deform its inner surface into intimate contact with said electrode and said insulating barrier.
3. A method as claimed in claim 2 and wherein said compliant materal is a soft metal.
4. A method as claimed in claim 3 and wherein the metal is aluminium, silver or indium.
5. A method as claimed in claim 2, 3 or 4 and wherein a surface of said device opposite to that of said surface is supported over an area which is approximately equal to the area over which said pressure contact member exerts pressure on said layer.
6. A method as claimed in any of claims 2 to 5 and wherein said electrically insulating barrier consists of a layer in which apertures are present at the position of underlying electrode areas.
7. A method as claimed in any of claims 2 to 6 and wherein said device is a thyristor having a distributed cathode connection which is constituted by a plurality of said electrodes.
8. An electrical contact arrangement substantially as illustrated in and described with reference to Fig. 3 of the accompanying drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8431952A GB2168529B (en) | 1984-12-18 | 1984-12-18 | Electrical contacts for semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8431952A GB2168529B (en) | 1984-12-18 | 1984-12-18 | Electrical contacts for semiconductor devices |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8431952D0 GB8431952D0 (en) | 1985-01-30 |
GB2168529A true GB2168529A (en) | 1986-06-18 |
GB2168529B GB2168529B (en) | 1988-02-03 |
Family
ID=10571372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8431952A Expired GB2168529B (en) | 1984-12-18 | 1984-12-18 | Electrical contacts for semiconductor devices |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2168529B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1987007080A1 (en) * | 1986-05-14 | 1987-11-19 | Semikron Elektronik Gmbh | Semi-conductor component |
WO1987007081A1 (en) * | 1986-05-14 | 1987-11-19 | Semikron Elektronik Gmbh | Semi-conductor component |
EP0285074A2 (en) * | 1987-03-31 | 1988-10-05 | Kabushiki Kaisha Toshiba | Pressure-contact type semiconductor device |
DE10236455B4 (en) * | 2001-08-09 | 2013-02-28 | Denso Corporation | Semiconductor device having a power semiconductor element of a vertical type |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB768731A (en) * | 1953-10-16 | 1957-02-20 | Gen Electric | Improvements in junction type semiconductor electrical devices |
GB1200426A (en) * | 1968-03-22 | 1970-07-29 | Hughes Aircraft Co | Method for providing a planar transistor with heat-dissipating top base and emitter contacts |
GB1211978A (en) * | 1968-05-31 | 1970-11-11 | Westinghouse Electric Corp | Contact system for intricate geometry devices |
-
1984
- 1984-12-18 GB GB8431952A patent/GB2168529B/en not_active Expired
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB768731A (en) * | 1953-10-16 | 1957-02-20 | Gen Electric | Improvements in junction type semiconductor electrical devices |
GB1200426A (en) * | 1968-03-22 | 1970-07-29 | Hughes Aircraft Co | Method for providing a planar transistor with heat-dissipating top base and emitter contacts |
GB1211978A (en) * | 1968-05-31 | 1970-11-11 | Westinghouse Electric Corp | Contact system for intricate geometry devices |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1987007080A1 (en) * | 1986-05-14 | 1987-11-19 | Semikron Elektronik Gmbh | Semi-conductor component |
WO1987007081A1 (en) * | 1986-05-14 | 1987-11-19 | Semikron Elektronik Gmbh | Semi-conductor component |
EP0285074A2 (en) * | 1987-03-31 | 1988-10-05 | Kabushiki Kaisha Toshiba | Pressure-contact type semiconductor device |
EP0285074A3 (en) * | 1987-03-31 | 1989-03-15 | Kabushiki Kaisha Toshiba | Press-contact type semiconductor device |
DE10236455B4 (en) * | 2001-08-09 | 2013-02-28 | Denso Corporation | Semiconductor device having a power semiconductor element of a vertical type |
DE10236455B8 (en) * | 2001-08-09 | 2013-05-08 | Denso Corporation | Semiconductor device having a power semiconductor element of a vertical type |
Also Published As
Publication number | Publication date |
---|---|
GB2168529B (en) | 1988-02-03 |
GB8431952D0 (en) | 1985-01-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4700273A (en) | Circuit assembly with semiconductor expansion matched thermal path | |
US4918514A (en) | Press-contact type semiconductor device | |
TW430950B (en) | Semiconductor device having reduced effective substrate resistivity and associated methods | |
GB1426539A (en) | Multiple chip integrated circuits and method of manufacturing the same | |
KR970067716A (en) | Semiconductor device and manufacturing method thereof | |
US3753056A (en) | Microwave semiconductor device | |
KR950034599A (en) | Semiconductor device and method of fabricating same | |
KR900019261A (en) | Semiconductor device | |
US4314270A (en) | Hybrid thick film integrated circuit heat dissipating and grounding assembly | |
US4388635A (en) | High breakdown voltage semiconductor device | |
EP0476661B1 (en) | Press-contact type semiconductor device | |
JPS59121871A (en) | Semiconductor device | |
US5497013A (en) | Semi-conductor chip having interdigitated gate runners with gate bonding pads | |
JP3003452B2 (en) | Conductive contact structure of two conductors | |
EP0146928B1 (en) | Power semiconductor device with mesa type structure | |
GB2168529A (en) | Electrical contacts for semiconductor devices | |
US5279888A (en) | Silicon carbide semiconductor apparatus | |
JP2000029061A5 (en) | ||
JPS5784157A (en) | Resin seal type semiconductor device | |
EP0660396B1 (en) | Power MOS device chip and package assembly | |
JPH05152361A (en) | Heat sink and hybrid integrated circuit using it | |
US5798287A (en) | Method for forming a power MOS device chip | |
JPS5943830B2 (en) | Pressure contact type semiconductor device | |
US5063436A (en) | Pressure-contacted semiconductor component | |
JPH0617249U (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19971218 |