JPS6138864B2 - - Google Patents

Info

Publication number
JPS6138864B2
JPS6138864B2 JP54120827A JP12082779A JPS6138864B2 JP S6138864 B2 JPS6138864 B2 JP S6138864B2 JP 54120827 A JP54120827 A JP 54120827A JP 12082779 A JP12082779 A JP 12082779A JP S6138864 B2 JPS6138864 B2 JP S6138864B2
Authority
JP
Japan
Prior art keywords
polyimide
copper
copper plate
support
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54120827A
Other languages
Japanese (ja)
Other versions
JPS5645060A (en
Inventor
Yasutoshi Kurihara
Komei Yatsuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12082779A priority Critical patent/JPS5645060A/en
Publication of JPS5645060A publication Critical patent/JPS5645060A/en
Publication of JPS6138864B2 publication Critical patent/JPS6138864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

PURPOSE:To obtain a device having superior electrical insulation, heat radiation and small noise by uniting a semiconductor element substrate and a supporting substance through polyimide covered with the resin of ethylene fluoride group. CONSTITUTION:A polyimide insulating film 3 and adhesive layers of ethylene fluoride, 4,4' are placed in piles on a copper supporting substance 2. And a semiconductor element 1 is placed on a copper plate 5 by adhering the copper plate 5 for unification. The connector lead wire 8 of the element 1 is installed through the copper plate 5 and emitter and base lead wires 6, 7 are installed. In this composition, the ethylene fluoride 4,4' will flow when the supporting substance 2 and the copper plate 5 are united. And deterioration or transformation will not occur for the good insulating polyimide even if a thin film is locally generated. And high insulating dielectric strength will be noted by leaving the polyimide. Furthermore, the space between the supporting substance 2 and the copper plate 5 will be filled by the flow of the films 4,4' and thermal resistance will become low. Furthermore, heat fatigue is hard to generate because the supporting plate 2 will be insulted from the pellet 1, noise will be reduced owing to the possibility of ground and the coefficient reduced owing to the possibility of ground and the coefficient of thermal expansion for the united section is almost same.

Description

【発明の詳細な説明】 本発明は半導体装置、とくに少なくとも半導体
素子を支持体上に縁絶物を介して載置した構造の
半動体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semi-moving device having a structure in which at least a semiconductor element is mounted on a support with an insulator interposed therebetween.

半導体装置の一例である高出力トランジスタで
は、数アンペア以上のコレクタ電流が流れるが、
その際半導体素子としてのトランジスタペレツト
の内部において発熱を生ずる。この発熱に起因す
る特性の不安定性や寿命の加速的劣化を避けるた
め、トランジスタペレツトが許容制限温度を越え
て昇温するのを防止する方法がとられている。
In a high-output transistor, which is an example of a semiconductor device, a collector current of several amperes or more flows.
At this time, heat is generated inside the transistor pellet as a semiconductor element. In order to avoid instability of characteristics and accelerated deterioration of lifetime due to this heat generation, methods are used to prevent the temperature of the transistor pellet from rising beyond the permissible limit temperature.

温度上昇を防ぐ方法の1つとして、従来、トラ
ンジスタペレツトの支持体としてのステムを放熱
器に取付け、トランジスタペレツトで発生した熱
をステムや放熱器を介して外部へ放出させる方法
がとられてきた。
One method to prevent temperature rise has traditionally been to attach the stem, which serves as a support for the transistor pellet, to a radiator, and to release the heat generated by the transistor pellet to the outside via the stem and the radiator. It's here.

高出力トランジスタの場合、上述したように大
きなコレクタ電流を流すため、その電流路を確保
することや効率的に熱放散させる必要から、コレ
クタ領域が直接ステムに固着されるようにトラン
ジスタペレツトを載置しているが、この種のトラ
ンジスタは通常エミツタまたはベース接地にして
使用されるため、コレクタ端子即ちステムは多く
の場合接地状態におかれる放熱器(またはシヤー
シ)などに直接取付けることができない。
In the case of high-output transistors, a large collector current flows as described above, so it is necessary to secure a current path and efficiently dissipate heat, so the transistor pellet is mounted so that the collector region is directly fixed to the stem. However, since this type of transistor is usually used with the emitter or base grounded, the collector terminal or stem cannot be directly attached to a heat sink (or chassis) etc. which is often grounded.

このため、通常はステムと放熱器との間に例え
ばマイカまたはテレフタル酸ポリエステル(マイ
ラ)などの絶縁板をはさんで電気的に絶縁し、放
熱を助けるためにステム−絶縁板間および絶縁板
−放熱器間の空隙を埋めるためのグリースを介
し、かつステムと放熱器とを絶縁ワツシヤを介し
たネジ締めによつて固定した。
For this reason, an insulating plate such as mica or polyester terephthalate (Mylar) is usually sandwiched between the stem and the heatsink to electrically insulate the stem and the heatsink, and in order to aid heat dissipation, the stem and the insulating plate and between the insulating plate and The stem and the radiator were fixed by screwing through an insulating washer and using grease to fill the gap between the radiators.

しかしこの場合でも、コレクタ領域がステムに
電気的に接続されている(ステムを接地状態にで
きない)ため、このままでは電磁波妨害による雑
音の影響を避けることが困難である。
However, even in this case, since the collector region is electrically connected to the stem (the stem cannot be grounded), it is difficult to avoid the effects of noise due to electromagnetic interference.

一方、電気絶縁、効率的な熱放散および電磁波
妨害防止をはかる試みとして金属支持体上にベリ
リヤ磁器やアルミナ磁器を介して半導体装置を載
置した例がある。しかしながら、ベリリヤ磁器を
用いた場合は、 (1) ベリリヤ自体が強い毒性を有しているためそ
の取扱いに厳重な注意を要し、しかも入手困難
で高価である。
On the other hand, in an attempt to achieve electrical insulation, efficient heat dissipation, and prevention of electromagnetic interference, there are examples in which a semiconductor device is mounted on a metal support via beryllia porcelain or alumina porcelain. However, when using beryllia porcelain, (1) beryllium itself is highly toxic, so strict care must be taken when handling it, and it is difficult to obtain and expensive.

(2) ベリリヤ磁器の熱膨張係数は7.6×10-6/℃
と小さく、支持体やコレクタ電極を兼ねるペレ
ツト載置板として広く用いられる銅(18×
10-6/℃)やアルミニウム(25×10-6/℃)の
それとの差が大きいため、そのままではベリリ
ヤ磁器−支持体間あるいはベリリヤ磁器−載置
板間接着部に熱疲労を生じやすく、両者間の強
固な一体化が困難である。
(2) The coefficient of thermal expansion of Beryliya porcelain is 7.6×10 -6 /℃
Copper (18×
10 -6 /℃) and aluminum (25 x 10 -6 /℃), so if left as is, thermal fatigue is likely to occur at the bond between the Berylliya porcelain and the support or between the Beryllya porcelain and the mounting plate. Strong integration between the two is difficult.

(3) 接着部の熱疲労を緩和するには歪緩和のため
の緩衝領域を設ける必要があり、このためには
例えば接着部のソルダ層を厚くしたりあるいは
モリブデン(熱膨張係数5.2×10-6/℃)やタ
ングステン(同4.3×10-6/℃)などのスペー
サを絶縁板に加えて介する必要があるが、この
場合は一体化に要する部品点数や処理工数が多
くなるほか熱放散上も不利になる。
(3) To alleviate thermal fatigue at the bonded area, it is necessary to provide a buffer area for strain relief.For this purpose, for example, the solder layer at the bonded area may be made thicker, or molybdenum (thermal expansion coefficient: 5.2×10 - It is necessary to use a spacer made of tungsten (4.3 x 10 -6 /℃) or tungsten ( 4.3 will also be disadvantageous.

(4) 絶縁板としてベリリヤ磁器を用いた場合に不
可欠なスペーサとしてのモリブデンやタングス
テンは重い金属である(モリブデンの比重
10.27、タングステンの比重19.3)ことから、
半導体装置の軽量化をはかる際の障害となる。
(4) Molybdenum and tungsten, which are essential spacers when using Beryllium porcelain as an insulating plate, are heavy metals (the specific gravity of molybdenum is
10.27, and the specific gravity of tungsten is 19.3).
This becomes an obstacle when trying to reduce the weight of semiconductor devices.

などの問題がある。一方、アルミナ磁器を用いた
場合でも、毒性の問題を除いては前述したベリリ
ア磁器と同様の問題を伴なう。
There are problems such as. On the other hand, even when alumina porcelain is used, problems similar to those of beryllia porcelain mentioned above are involved, except for the problem of toxicity.

以上では、トランジスタを例にして、従来の半
導体装置の欠点を説明したが、トランジスタに限
らず、ダイオードやサイリスタなど他の半導体装
置あるいは混成集積回路を構成した半導体装置に
おいても同様の問題点を残していた。
In the above, we have explained the shortcomings of conventional semiconductor devices using transistors as an example, but similar problems remain not only in transistors but also in other semiconductor devices such as diodes and thyristors, or in semiconductor devices that constitute hybrid integrated circuits. was.

本発明は、前述の欠点を改善し、半導体素子と
支持体との間の優れた電気絶縁、効率的な熱放
散、電磁波妨害による雑音防止、支持体または載
置板と絶縁担体との強固な接合、そして軽量化、
低コスト化等がすべて可能な半導体装置を提供す
ることを目的とする。
The present invention improves the above-mentioned drawbacks, provides excellent electrical insulation between the semiconductor element and the support, efficient heat dissipation, noise prevention due to electromagnetic interference, and strong connection between the support or mounting plate and the insulating carrier. Bonding and weight reduction
The purpose of the present invention is to provide a semiconductor device that is capable of reducing costs.

上記目的を達成する本発明の半導体装置は、少
なくとも半導体素子と、該半導体素子を載置する
金属載置板と、該金属載置板を載置する金属支持
体と、そして少なくとも一方の面にフツ素化エチ
レン系樹脂を被覆したポリイミドフイルムとから
構成され、該フイルムを前記半導体素子の金属載
置板と金属支持体との間に介在させて一体化した
ことを特徴とする。
A semiconductor device of the present invention that achieves the above object includes at least a semiconductor element, a metal mounting plate on which the semiconductor element is mounted, a metal support on which the metal mounting plate is mounted, and at least one surface of the semiconductor device. A polyimide film coated with a fluorinated ethylene resin is characterized in that the film is interposed and integrated between the metal mounting plate of the semiconductor element and the metal support.

本発明は、ポリイミドが体積抵抗率1018Ωcm
(25℃)、絶縁破壊強さ約280kv/mm(25℃)、熱膨
張係数20×16-6/℃(常温)、密度1.42g/cm3であ
り、優れた電気絶縁性と、比較的大きな熱膨張係
数と、比較的軽量であるほか、10μm程度にまで
薄くできそして低コストであることなどの特長を
有し、一方フツ素化樹脂はポリイミドと同等の絶
縁性や熱膨張係数を有しているほか、ポリイミド
の変質を生じない温度(約250℃)で軟化し始め
るため、有効な接着剤として作用するなどの特長
を有する点に着目してなされたものである。
In the present invention, polyimide has a volume resistivity of 10 18 Ωcm.
(25℃), dielectric breakdown strength of about 280kv/mm (25℃), thermal expansion coefficient of 20×16 -6 /℃ (room temperature), and density of 1.42g/cm 3 . It has a large coefficient of thermal expansion, is relatively lightweight, can be made as thin as 10 μm, and is low cost. On the other hand, fluorinated resin has insulation properties and a coefficient of thermal expansion equivalent to that of polyimide. In addition to this, it begins to soften at a temperature (approximately 250°C) that does not cause deterioration of polyimide properties, so it acts as an effective adhesive.

とくに本発明では、半導体素子載置板と支持体
とをフツ素化エチレン系樹脂を被覆したポリイミ
ドを介して一体化しており、一体化のための接着
剤としてフツ素化エチレン系樹脂を用いたことに
最も大きな特徴がある。
In particular, in the present invention, the semiconductor element mounting plate and the support are integrated via polyimide coated with a fluorinated ethylene resin, and the fluorinated ethylene resin is used as an adhesive for integration. It has the most significant feature.

したがつて、一体化の際の熱処理により接着剤
としてのフツ素化エチレン系樹脂層に万一不均一
な部分が生じてもポリイミド層は均一な状態に保
持されるため、一体化部の電気絶縁性が損なわれ
ることがなく、半導体素子あるいは混成集積回路
素子とこれらを載置する支持体との電気絶縁を容
易に実現できる。
Therefore, even if uneven parts occur in the fluorinated ethylene resin layer as an adhesive due to heat treatment during integration, the polyimide layer remains uniform, so the electrical Electrical insulation between semiconductor elements or hybrid integrated circuit elements and the support on which they are mounted can be easily realized without impairing insulation properties.

また、絶縁のためのポリイミドやフツ素化エチ
レンの熱膨張係数が支持体や載置板として広く使
用される銅やアルミニウムのそれに極めて近接す
るため、接着部の熱疲労を生じにくい強固な一体
化が可能となる。さらに、絶縁層の重さは他の部
品に比べて事実上無視できるほど軽く、そして絶
縁層と支持体または載置板間に余分なスペーサを
介さなくてもよいため半導体装置の軽量化、小型
化に有効である。なお、絶縁材料そのものの熱伝
導率は〜5×10-4cal/cm・s・℃と小さいものの、
薄層化することによつて実用上支障の無い程度に
放熱性を確保できることなどが確認された。
In addition, the coefficient of thermal expansion of polyimide and fluorinated ethylene for insulation is extremely close to that of copper and aluminum, which are widely used as supports and mounting plates, making it possible to form a strong, integrated structure that is less likely to cause thermal fatigue at the bonded part. becomes possible. Furthermore, the weight of the insulating layer is so light that it can be virtually ignored compared to other parts, and there is no need to insert an extra spacer between the insulating layer and the support or mounting plate, which reduces the weight and size of semiconductor devices. It is effective for Although the thermal conductivity of the insulating material itself is small at ~5×10 -4 cal/cm・s・℃,
It was confirmed that by making the layer thinner, it was possible to ensure heat dissipation to a level that would not cause any practical problems.

本発明において用いられる接着剤としてのフツ
素化エチレンは、4フツ化エチレン−6フツ化プ
ロピレン重合体あるいはポリ4フツ化エチレンで
あることが望ましい。これに対し、一般的な絶縁
性接着剤として知られるエポキシ系あるいはアク
リル系接着剤は熱硬化性のもので、150℃前後の
温度で処理されるが、通常これより高い温度のも
とで行なわれる半導体プロセス(例えば、約200
〜350℃で行われるはんだ付工程)に適用するこ
とが困難であるばかりでなく、苛酷な温度条件下
での使用により絶えず硬化が進行する。この点、
前述のフツ素化エチレン系では、約400℃までの
温度で処理が可能であり、熱可塑性であつて硬化
が過度に進行することもない。
The fluorinated ethylene used as the adhesive in the present invention is preferably a tetrafluoroethylene-hexafluoropropylene polymer or polytetrafluoroethylene. In contrast, epoxy or acrylic adhesives, which are commonly known as insulating adhesives, are thermosetting and are processed at temperatures of around 150°C, but are usually processed at higher temperatures. semiconductor process (for example, approximately 200
Not only is it difficult to apply it to the soldering process (which is carried out at ~350°C), but also hardening progresses constantly due to use under severe temperature conditions. In this point,
The above-mentioned fluorinated ethylene type can be processed at temperatures up to about 400°C, and since it is thermoplastic, curing does not proceed excessively.

以下実施例により本発明を詳細に説明する。 The present invention will be explained in detail below with reference to Examples.

実施例 1 本実施例における半導体装置は、第1図に示す
ように、半導体素子としてのシリコントランジス
タペレツト1を銅支持体2上に絶縁層としてのポ
リイミド3および接着剤としてのフツ素化エチレ
ン4,4′を介して固着一体化した銅載置板5上
に載置したものである。
Example 1 As shown in FIG. 1, a semiconductor device in this example consists of a silicon transistor pellet 1 as a semiconductor element on a copper support 2, a polyimide layer 3 as an insulating layer, and a fluorinated ethylene layer as an adhesive. It is mounted on a copper mounting plate 5 which is fixed and integrated via 4 and 4'.

トランジスタペレツト1のエミツタおよびベー
ス領域はそれぞれアルミニウムリード線6および
7で電気接続され、そしてコレクタ領域は銅載置
板5を介してアルミニウムリード線8に電気接続
される。その後通常用いられる方法でアルミニウ
ムリード線6,7および8を銅リード(図示せ
ず)に接続し、そして銅支持体2および銅リード
の一部を除く少くとも前述の各部が完全に外気か
らしや断されるように、樹脂でモールド(図示せ
ず)する。
The emitter and base regions of the transistor pellet 1 are electrically connected by aluminum leads 6 and 7, respectively, and the collector region is electrically connected to an aluminum lead 8 via a copper mounting plate 5. The aluminum leads 6, 7 and 8 are then connected to the copper leads (not shown) in a conventional manner, and at least the aforementioned parts, except for the copper support 2 and a portion of the copper leads, are completely exposed to the outside air. It is molded with resin (not shown) so that it is cut off.

このような構成で得られた半導体装置では、銅
リード−銅支持体2間の絶縁耐圧は2000V以上、
トランジスタペレツト1−銅支持体2間の熱抵抗
は1℃/W以下が得られた。また、電磁波妨害に
よる雑音はトランジスタペレツト1−銅支持体2
間を電気絶縁しない場合より約30dB小さくな
り、そしてトランジスタペレツト1に常温〜125
℃間の熱変化を1000回与えたときの銅支持体2−
銅載置板5間の固着一体化部には何等の異常も見
出されなかつた。
In the semiconductor device obtained with such a configuration, the dielectric strength between the copper lead and the copper support 2 is 2000 V or more,
The thermal resistance between the transistor pellet 1 and the copper support 2 was less than 1°C/W. In addition, noise due to electromagnetic interference is caused by transistor pellet 1 - copper support 2.
It is about 30 dB lower than when there is no electrical insulation between the transistor pellets 1 and 125
Copper support 2- when subjected to 1000 thermal changes between ℃
No abnormality was found in the fixed and integrated portion between the copper mounting plates 5.

このように高い絶縁耐圧が得られたのは、銅支
持体2と銅載置板5が一体化される際に、接着剤
を兼ねるフツ素化エチレン4,4′が流動して万
一局部的に薄い部分を生じても、絶縁性に優れる
ポリイミド3は変質や変形を生ずることなく確実
に残存するためである。また、熱抵抗が小さいの
は、接着剤を兼ねるフツ素化エチレン4,4′
が、一体化熱処理の際にある程度流動して銅支持
体2と銅載置板5との間の空隙を埋める役割を果
す結果、薄く、しかも空隙の少ない絶縁層が形成
されたためである。
The reason why such a high dielectric strength voltage was obtained is that when the copper support 2 and the copper mounting plate 5 are integrated, the fluorinated ethylene 4, 4', which also serves as an adhesive, flows and is This is because even if a thin portion is formed, the polyimide 3, which has excellent insulating properties, will remain without deterioration or deformation. In addition, fluorinated ethylene 4,4', which also serves as an adhesive, has low thermal resistance.
However, during the integration heat treatment, it flows to some extent and fills the gap between the copper support 2 and the copper mounting plate 5, resulting in the formation of a thin insulating layer with fewer gaps.

雑音を低減できたのは、銅支持板2がトランジ
スタペレツト1から電気的に絶縁されているた
め、銅支持板2を接地することが可能になつたこ
とに起因する。また熱疲労の生じにくい堅牢な一
体化ができたのは、銅支持体2または銅載置板5
とポリイミド3やフツ素化エチレン4,4′がほ
ぼ同等の熱膨張係数を有しているため、一体化部
の温度変化に伴なう残留応力変化を軽減できたこ
とによる。
The reason why the noise can be reduced is that since the copper support plate 2 is electrically insulated from the transistor pellet 1, it becomes possible to ground the copper support plate 2. In addition, the copper support 2 or the copper mounting plate 5 was able to be integrated in a robust manner that does not cause thermal fatigue.
This is because the polyimide 3 and the fluorinated ethylene 4 and 4' have substantially the same coefficient of thermal expansion, so that changes in residual stress due to temperature changes in the integrated portion can be reduced.

なお、本実施例における半導体装置では、支持
板または載置板と絶縁担体間に重い金属板やソル
ダ金属を介していないため、従来の半導体装置の
同等品より20%程度軽量化されるとともに、一体
化に要する部品点数や処理工数が低減されたた
め、経済的に有利であることが確認された。
Note that the semiconductor device in this example does not have a heavy metal plate or solder metal interposed between the support plate or mounting plate and the insulating carrier, so it is approximately 20% lighter than the equivalent conventional semiconductor device, and It was confirmed that this method is economically advantageous because the number of parts and processing steps required for integration are reduced.

実施例 2 本実施例における半導体装置は、第2図に示す
ように、半導体素子としてのシリコンダイオード
ペレツト21a,21a′,21b,21b′を、銅
支持体22上に、絶縁層としてのポリイミド23
a,23bおよび接着剤としてのフツ素化エチレ
ン241a,242a,241b,242bを介
して一体化した銅載置板25a,25b上に載置
した混成集積回路装置である。
Example 2 As shown in FIG. 2, a semiconductor device according to this example includes silicon diode pellets 21a, 21a', 21b, and 21b' as semiconductor elements on a copper support 22 and a polyimide layer as an insulating layer. 23
This is a hybrid integrated circuit device mounted on copper mounting plates 25a, 25b which are integrated via a, 23b and fluorinated ethylene 241a, 242a, 241b, 242b as an adhesive.

各々のダイオードペレツトにはリード線26
a,26a′,26b,26b′を設け、そして銅載
置板25a,25bにもリード線27a,27b
を設け、4個のダイオードがそれぞれ整流回路の
一部を担うように電気接続し、さらに少くともシ
リコンダイオードペレツトが外気からしや断され
るように、レジンモールドしたものである。
Each diode pellet has a lead wire 26.
a, 26a', 26b, 26b', and lead wires 27a, 27b are also provided on the copper mounting plates 25a, 25b.
The four diodes are electrically connected so as to each serve as a part of a rectifier circuit, and are resin-molded so that at least the silicon diode pellets are isolated from the outside air.

このような構成で得られた半導体装置の絶縁
性、放熱性、雑音防止効果、耐熱疲労性は前記実
施例1と同等であつた。これは前記実施例1の場
合と同様の理由による。
The insulation properties, heat dissipation properties, noise prevention effects, and thermal fatigue resistance of the semiconductor device obtained with such a configuration were equivalent to those of Example 1. This is due to the same reason as in the first embodiment.

また、本実施例の場合、載置板25a,25b
に複数個の半導体素子が取付けられるため、絶縁
層の面積が広くなるにもかかわらず、絶縁性が阻
害されることはなかつた。これは、支持板22と
載置板25a,25bとが一体化される際に、接
着剤を兼ねるフツ素化エチレン241a,b,2
42a,bが流動して万一局所的に薄い部分を生
じても、絶縁性に優れるポリイミドフイルム23
a,bが変質や変形を生ずることなく確実に残存
したためである。
In addition, in the case of this embodiment, the mounting plates 25a, 25b
Since a plurality of semiconductor elements are attached to the insulating layer, the insulation properties are not impaired even though the area of the insulating layer becomes large. When the support plate 22 and the mounting plates 25a, 25b are integrated, the fluorinated ethylene 241a, b, 241b, which also serves as an adhesive,
The polyimide film 23 has excellent insulation properties even if 42a and 42b flow and create locally thin parts.
This is because a and b remained without alteration or deformation.

以上のように、フツ素化エチレンを被覆したポ
リイミドを絶縁担体として用いることは、半導体
素子を複数個集積した回路装置の場合にも有用で
あることが実証された。
As described above, it has been demonstrated that the use of polyimide coated with fluorinated ethylene as an insulating carrier is also useful in the case of a circuit device in which a plurality of semiconductor elements are integrated.

実施例 3 本実施例における半導体装置は、第3図aに示
すように、半導体素子としてのシリコンダイオー
ドペレツト31を、銅支持体32上に絶縁層とし
てのポリイミド34および接着剤としてのフツ素
化エチレン35,35′を介して一体化した銅載
置板33上に載置し、他方、銅載置板33が設け
られずにフツ素化エチレン35が露出した部分に
チツプ抵抗36、チツプコンデンサ37および銅
電極板38をそれぞれ載置した混成集積回路装置
である。
Example 3 As shown in FIG. 3a, a semiconductor device in this example includes a silicon diode pellet 31 as a semiconductor element, a polyimide layer 34 as an insulating layer, and fluorine as an adhesive on a copper support 32. The chip is placed on the integrated copper mounting plate 33 via the fluorinated ethylene 35, 35', and a chip resistor 36 and a chip are placed on the exposed portion of the fluorinated ethylene 35 without the copper mounting plate 33. This is a hybrid integrated circuit device in which a capacitor 37 and a copper electrode plate 38 are respectively mounted.

さらに、同図bに示すように、抵抗36とコン
デンサ37が直列に接続されると同時に、ダイオ
ード31が並列に接続された電気回路が構成され
るように、各素子間をアルミニウム線39a,3
9b,39cやリードフレーム40a,40b,
40cで結線し、さらに前述の諸回路素子をレジ
ンモールドする。
Further, as shown in FIG. 3B, aluminum wires 39a and 3 are connected between each element so that an electric circuit is formed in which the resistor 36 and the capacitor 37 are connected in series, and the diode 31 is connected in parallel.
9b, 39c and lead frames 40a, 40b,
40c, and the various circuit elements described above are resin molded.

このような構成で得られた半導体装置の絶縁
性、放熱性、雑音防止効果、耐熱疲労性等は前記
実施例1の場合と同等であつた。これは前記実施
例1と同様の理由による。
The insulation, heat dissipation, noise prevention effect, thermal fatigue resistance, etc. of the semiconductor device obtained with such a configuration were the same as those of Example 1. This is due to the same reason as in the first embodiment.

また、絶縁層としてのポリイミド34に、同じ
く絶縁層としての性質を有し、かつ接着剤として
も作用するフツ素化エチレン35,35′がコー
テイングされているため、その上にチツプ抵抗3
6やチツプコンデンサ37、電極板38を直接載
置でき、その結果これらの受動素子を載置するた
めのメタライズ処理が不要になり、経済性が一層
高まることが確認された。
Furthermore, since the polyimide 34 serving as the insulating layer is coated with fluorinated ethylene 35, 35' which also has properties as an insulating layer and also acts as an adhesive, the chip resistor 34 is coated thereon.
6, the chip capacitor 37, and the electrode plate 38 can be directly mounted, and as a result, metallization treatment for mounting these passive elements is no longer necessary, and it has been confirmed that the economical efficiency is further improved.

実施例 4 本実施例における半導体装置は、第4図に示す
ように、回路素子の中で最も発熱の著しいサイリ
スタ51,51′は、両面をフツ素化エチレンで
コーテイングしたポリイミドフイルムからなる絶
縁層53を介して、支持板52に固着一体化した
大面積の金属載置板54,54′上に直接合金化
処理して載置し、一方、発熱量の少ない受動素子
55,55′は載置板54,54′上に形成され、
前述と同様の構成をもつ絶縁層56上に直接載置
し、さらに発熱量の少ないダイオード57,5
7′は、載置板54,54′上に前述と同様の絶縁
層58,58′を介して固着一体化した小面積の
金属載置板59,59′に合金化処理して載置し
た電流制御用混成集積回路装置である。
Example 4 In the semiconductor device of this example, as shown in FIG. 4, the thyristors 51 and 51', which generate the most heat among the circuit elements, are made of an insulating layer made of a polyimide film coated on both sides with fluorinated ethylene. 53, the metal mounting plates 54, 54' with a large area fixedly integrated with the support plate 52 are directly alloyed and mounted, while the passive elements 55, 55', which generate less heat, are mounted. formed on the placing plates 54, 54';
Diodes 57, 5 which are placed directly on the insulating layer 56 having the same structure as described above and which generate less heat are provided.
7' was alloyed and placed on small-area metal mounting plates 59, 59' which were fixed and integrated on the mounting plates 54, 54' via insulating layers 58, 58' similar to those described above. This is a hybrid integrated circuit device for current control.

このような構成で得られた半導体装置の絶縁
性、放熱性、雑音防止効果、耐熱疲労性は前記実
施例1と同等であつた。これは前記実施例1と同
様の理由による。
The insulation properties, heat dissipation properties, noise prevention effects, and thermal fatigue resistance of the semiconductor device obtained with such a configuration were equivalent to those of Example 1. This is due to the same reason as in the first embodiment.

また、この半導体装置の場合、発熱量の大きな
回路素子は面積の広い載置板に載置し放熱をあま
り必要としない回路素子はさらにその上に積層し
た載置板に載置するというように、いわば縦方向
の空間を効率的に利用できる構造になつている点
に特徴がある。この結果、放熱が有効になされ、
そして縦方向へ回路部品を実装できたため、混成
集積回路装置の占有面積を小さくすることができ
た。
In addition, in the case of this semiconductor device, circuit elements that generate a large amount of heat are placed on a mounting plate with a large surface area, and circuit elements that do not require much heat dissipation are placed on a mounting plate that is stacked on top of that. , so to speak, is characterized by a structure that allows for efficient use of vertical space. As a result, heat dissipation is effective,
Since circuit components could be mounted vertically, the area occupied by the hybrid integrated circuit device could be reduced.

以上に実施例を用いて本発明を説明したが、本
発明はこれのみに限定されるものではなく、例え
ば次のような場合でも本発明の効果ないし利点を
享受できる。
Although the present invention has been described above using examples, the present invention is not limited thereto, and the effects and advantages of the present invention can be enjoyed even in the following cases, for example.

(1) 絶縁層の一部を構成するポリイミドフイルム
61は第5図aに示すように一方の面のみにフ
ツ素化エチレン62をコーテイングした構造、
または同図bに示すように一方の面にフツ素化
エチレン62を、また他方の面に金属63をメ
タライズした構造であつてもよい。
(1) The polyimide film 61 constituting a part of the insulating layer has a structure in which only one surface is coated with fluorinated ethylene 62, as shown in FIG. 5a.
Alternatively, as shown in FIG. 5B, it may have a structure in which fluorinated ethylene 62 is metallized on one surface and metal 63 is metallized on the other surface.

(2) 支持体または載置板が銅以外の金属、例えば
アルミニウムでもよい。
(2) The support or mounting plate may be made of metal other than copper, such as aluminum.

(3) 少くとも半導体素子を外気からしや断する方
法がレジンモールド法である必要はなく、他の
方法例えばキヤンシール法を用いてもよい。
(3) At least the method of insulating the semiconductor element from the outside air does not have to be the resin molding method, and other methods such as the can seal method may be used.

(4) 半導体素子がゲルマニウム、ヒ化ガリウム、
リン化ガリウム、炭化ケイ素など、シリコン以
外の半導体物質から構成される場合でもよい。
(4) Semiconductor elements are made of germanium, gallium arsenide,
It may be made of a semiconductor material other than silicon, such as gallium phosphide or silicon carbide.

以上まで説明したように、本発明によれば次の
ような利点ないし効果を奏することができる。
As explained above, according to the present invention, the following advantages and effects can be achieved.

(1) 絶縁層は、ポリイミドフイルムの少くとも片
面に、接着剤としての役割を兼ねるフツ素化エ
チレン系樹脂を被覆した構造をしているため、
フツ素化エチレン系樹脂が流動して万一局部的
に薄い部分を生じても、絶縁性に優れるポリイ
ミドは変質、変形することなく確実に残存す
る。この結果、半導体素子あるいは他の回路素
子を支持体から良好に電気絶縁できる。
(1) The insulating layer has a structure in which at least one side of the polyimide film is coated with a fluorinated ethylene resin that also serves as an adhesive.
Even if the fluorinated ethylene resin flows and some thin parts occur locally, the polyimide, which has excellent insulating properties, will remain without deterioration or deformation. As a result, the semiconductor element or other circuit element can be electrically insulated favorably from the support.

(2) 接着剤を兼ねるフツ素化エチレン系樹脂が一
体化熱処理の際にある程度流動して空隙を埋め
る役割を果す結果、薄くしかも空隙の少ない絶
縁層が形成され、半導体素子の放熱性がよくな
る。
(2) The fluorinated ethylene resin, which also serves as an adhesive, flows to some extent during the integration heat treatment and plays the role of filling the voids, resulting in the formation of a thin insulating layer with few voids, improving the heat dissipation of the semiconductor element. .

(3) 半導体素子が支持体から電気絶縁されている
ため、支持体を接地できる。この結果、半導体
装置の電気特性が電磁波妨害に影響されない。
(3) Since the semiconductor element is electrically insulated from the support, the support can be grounded. As a result, the electrical characteristics of the semiconductor device are not affected by electromagnetic interference.

(4) 支持体または載置板と絶縁層の熱膨張係数が
近接しているため、これらの一体化部における
熱疲労を避けることができる。
(4) Since the thermal expansion coefficients of the support or mounting plate and the insulating layer are close to each other, thermal fatigue at the integrated portion can be avoided.

(5) 絶縁層は薄くてもよく、そして絶縁層と支持
体または載置板間に他の金属スペーサを介さな
くてもよいため、半導体装置を軽量化すること
が可能であり、さらに部品点数や製作工数が少
なくなるため、経済的に半導体装置を製作でき
る。
(5) The insulating layer can be thin, and there is no need to interpose other metal spacers between the insulating layer and the support or mounting plate, so it is possible to reduce the weight of the semiconductor device and further reduce the number of parts. The semiconductor device can be manufactured economically because the number of manufacturing steps and the number of manufacturing steps are reduced.

(6) 絶縁層上に受動素子を直接載置できるため、
載置するためのメタライズ処理が不要で経済性
が高まる。
(6) Passive elements can be placed directly on the insulating layer, so
No metallization process is required for mounting, increasing economic efficiency.

(7) 複数の回路素子や回路部品を積層して載置で
きるため、効率的な熱放散、効率的な空間利用
が可能であり、混成集積回路装置を小形化でき
る。
(7) Since multiple circuit elements and circuit components can be stacked and mounted, efficient heat dissipation and efficient use of space are possible, allowing the hybrid integrated circuit device to be miniaturized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1,2,3および4図はそれぞれ本発明の実
施例の断面図、第5図は絶縁層の他の構成例の断
面図である。 1……シリコントランジスタペレツト、2……
銅支持体、3……ポリイミド、4,4′……フツ
素化エチレン、5……銅載置板。
1, 2, 3 and 4 are sectional views of embodiments of the present invention, and FIG. 5 is a sectional view of another example of the structure of the insulating layer. 1...Silicon transistor pellet, 2...
Copper support, 3... polyimide, 4,4'... fluorinated ethylene, 5... copper mounting plate.

Claims (1)

【特許請求の範囲】[Claims] 1 少なくとも半導体素子と、該半導体素子を載
置する金属載置板と、該金属載置板を載置する金
属支持体と、前記金属載置板と金属支持体との間
に介在させられ、少なくとも一方の面にフツ素化
エチレン系樹脂を被覆されたポリイミドフイルム
とを具備し、これが互いに固着一体化されたこと
を特徴とする半導体装置。
1 At least a semiconductor element, a metal mounting plate on which the semiconductor element is placed, a metal support on which the metal placement plate is placed, and interposed between the metal placement plate and the metal support, 1. A semiconductor device comprising a polyimide film whose at least one surface is coated with a fluorinated ethylene resin, and which are fixedly integrated with each other.
JP12082779A 1979-09-21 1979-09-21 Semiconductor device Granted JPS5645060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12082779A JPS5645060A (en) 1979-09-21 1979-09-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12082779A JPS5645060A (en) 1979-09-21 1979-09-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5645060A JPS5645060A (en) 1981-04-24
JPS6138864B2 true JPS6138864B2 (en) 1986-09-01

Family

ID=14795938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12082779A Granted JPS5645060A (en) 1979-09-21 1979-09-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5645060A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58138395U (en) * 1982-03-11 1983-09-17 電気化学工業株式会社 insulation fin
JPS603132A (en) * 1983-06-20 1985-01-09 Nitto Electric Ind Co Ltd Semiconductor device
JPS60102751A (en) * 1983-11-09 1985-06-06 Nitto Electric Ind Co Ltd Adhesive film for fixing semiconductor element
JPH0636416B2 (en) * 1983-11-09 1994-05-11 日東電工株式会社 Conductive adhesive film for fixing semiconductor elements
JPS60106471A (en) * 1983-11-15 1985-06-11 住友ゴム工業株式会社 Core for tennis ball
WO1996037915A1 (en) * 1995-05-26 1996-11-28 Sheldahl, Inc. Adherent film with low thermal impedance and high electrical impedance used in an electronic assembly with a heat sink
JP2007288054A (en) * 2006-04-19 2007-11-01 Toyota Motor Corp Power module
DE102021214247A1 (en) * 2021-12-13 2023-06-15 Robert Bosch Gesellschaft mit beschränkter Haftung Power module with high-voltage isolation

Also Published As

Publication number Publication date
JPS5645060A (en) 1981-04-24

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