JPS603132A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS603132A
JPS603132A JP58111287A JP11128783A JPS603132A JP S603132 A JPS603132 A JP S603132A JP 58111287 A JP58111287 A JP 58111287A JP 11128783 A JP11128783 A JP 11128783A JP S603132 A JPS603132 A JP S603132A
Authority
JP
Japan
Prior art keywords
fluorine
polymer
semiconductor element
die bonding
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58111287A
Other languages
Japanese (ja)
Inventor
Haruo Tabata
田畑　晴夫
Fujio Kitamura
北村　富士夫
Hideto Suzuki
秀人 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Electric Industrial Co Ltd filed Critical Nitto Electric Industrial Co Ltd
Priority to JP58111287A priority Critical patent/JPS603132A/en
Publication of JPS603132A publication Critical patent/JPS603132A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To enable to obtain a semiconductor device having favorable workability, and having favorable humidity resistant reliability by a method wherein fluorine-contained polymer of the specified fusion point is interposed between a substrate and a semiconductor element, and the semiconductor element is adhered to be fixed according to the polymer thereof. CONSTITUTION:A die bonding material 3 is consisting of fluorine-contained polymer of 200-320 deg.C of the fusion point, the polymer thereof is put on a lead frame 2a, and by fixing a semiconductor element 1 thereon according to contact bonding to be thermally fused, the element 1 is fixed to the lead frame 2a according to die bonding. According to this method, die bonding work can be attained in a short time. Moreover, because there exists no fear about generation of expansion at die bonding time, reduction of adhesion to be caused therefrom is not presented. Moreover, almost no reduction of humidity resistance is generated.

Description

【発明の詳細な説明】 この発明は半導体素子をステムやリードフレームの如き
基板上にフッ素系ポリマーを用いて接着固定した半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a semiconductor element is adhesively fixed onto a substrate such as a stem or a lead frame using a fluorine-based polymer.

従来、ステムやリードフレームの如き基板に半導体素子
を接着固定するだめのいわゆるグイボンディング用材料
として、基板と素子との間の電気的な接続機能を兼ね備
えだＡｕ−’Ｓｉ共晶や導電性銀ペースト組成物が知ら
れている。上記Ａｕ−５ｉ共晶とは基板上に予めＡｕメ
ッキを施しこの」ニに半導体素子としてのシリコンチッ
プを高温下で圧着してＡｕ−８ｌ共品合金からなる金属
接着層を形成するものであり、また導電性銀ペースト組
成物はエポキシ樹脂やポリイミド系樹脂の前駆体の溶液
に導電性材料としての銀粉を混練してペースト化しこれ
を基板と素子との間に介装塗着したのち加熱硬化させる
ものである。Conventionally, Au-'Si eutectic and conductive silver, which have the function of electrical connection between the substrate and the element, have been used as so-called "guibonding" materials for adhesively fixing semiconductor elements to substrates such as stems and lead frames. Paste compositions are known. The above-mentioned Au-5i eutectic is a material in which a substrate is plated with Au in advance, and a silicon chip as a semiconductor element is bonded to this eutectic under high temperature to form a metal adhesive layer made of an Au-8l eutectic alloy. In addition, a conductive silver paste composition is made by kneading silver powder as a conductive material into a solution of a precursor of an epoxy resin or polyimide resin to form a paste, which is applied as an intermediary between a substrate and an element, and then heated and cured. It is something that makes you

しかるに、半導体素子のなかにはｋｉＯ５Ｉｃ、ＬＳＩ
。However, some semiconductor devices include kiO5Ic, LSI
.

ＣＣＤ、バイポーラＩＣ，ＳＯ３などのように、ザブ電
極を半導体素子上のポンディングパッドより引き出すこ
とができ、半導体素子の裏面のメタライゼーション（基
板上に素子表面を電気的に接続すること）が不要な半導
体素子もある。かかる素子に前記従来の接着材料を適用
することは、高価なＡｕ。As in CCD, bipolar IC, SO3, etc., the sub electrode can be drawn out from the bonding pad on the semiconductor element, and metallization on the back side of the semiconductor element (electrical connection of the element surface to the substrate) is unnecessary. There are also semiconductor devices. Applying the conventional adhesive materials to such devices is expensive Au.

Ａｇを必要とすることから経済的に不利である。It is economically disadvantageous because it requires Ag.

一方、非電性銀ペースト組成物にあっては、銀粉のバイ
ンダとなるエポキシ樹脂およびポリイミド系樹脂の前駆
体に起因して本来下記の如き欠点があった。すなわち、
両樹脂共にその硬化に長時間を要し、Ａｕ−３ｉ共晶に
比しダイポンディングの作業性に劣り、またエポキシ樹
脂では高温での耐湿特性に欠は素子の配線パターンが経
時的に腐食しやすく、一方ポリイミド系樹脂の１］１■
駆体では加熱硬化（イミド化）するときに発生する水や
その他溶媒によって発泡して半導体素子の接着力が低下
しやすいという欠点があった。On the other hand, non-electroconductive silver paste compositions inherently have the following drawbacks due to the epoxy resin and polyimide resin precursors that serve as binders for silver powder. That is,
Both resins take a long time to harden and are inferior to Au-3i eutectic in terms of die bonding workability, and epoxy resin lacks moisture resistance at high temperatures, causing the wiring pattern of the device to corrode over time. On the other hand, polyimide resin 1] 1■
The precursor has a drawback in that it tends to foam due to water and other solvents generated during heat curing (imidization), which tends to reduce the adhesive strength of semiconductor elements.

しだがって、前記した裏面のメタライゼーションが不要
な半導体素子に対して」１記従来の銀ペースト組成物を
そのまま適用した場合は当然のこと、仮にこの組成物の
代りに銀粉を全く含まないエポキシ樹脂およびポリイミ
ド系樹脂の前駆体の溶液そのものをダイポンディング用
材料として用いたときでも、前記同様の欠点を免れない
。Therefore, it is natural that if the conventional silver paste composition described in 1. is applied as is to the semiconductor device that does not require metallization on the back side, it would be natural to use a method that does not contain any silver powder instead of this composition. Even when solutions of precursors of epoxy resins and polyimide resins themselves are used as die-ponding materials, the same drawbacks as described above are inevitable.

この発明者らは、以上の観点から、裏面のメタライゼー
ションが不要な半導体素子に対して好適なダイポンディ
ング用利料を探究するべく鋭意検討した結果、特定の融
点を持ったフッ素系ポリマーがこの種の材料としてきわ
めて適したものであることを知り、この発明をなすに至
った。From the above point of view, the inventors conducted extensive research to find suitable die-bonding materials for semiconductor devices that do not require backside metallization, and found that fluorine-based polymers with a specific melting point were found to be suitable for die-bonding. We discovered that it is extremely suitable as a material for seeds, and came up with this invention.

すなわち、この発明は、基板と半導体素子との間に融点
が２００〜・３２０°Ｃのフッ素系ポリマーを介在させ
、このポリマーにより上記素子を上記基板に接着固定し
てなる半導体装置に係るものである。That is, the present invention relates to a semiconductor device in which a fluorine-based polymer having a melting point of 200 to 320°C is interposed between a substrate and a semiconductor element, and the element is adhesively fixed to the substrate by this polymer. be.

以下、この発明を図面を参考にして説明する。This invention will be explained below with reference to the drawings.

第１図および第２図はこの発明の半導体装置の一例を示
したもので、１は半導体基板としてのリードフレーム２
ａ上に設けられた半導体素子、３は上記フレーム２ａと
素子１との間に介在されて素子１をフレーム２ａにタイ
ポンチインクつまり接着固定したダイボンデインク用利
別、４，４は」−記素子１上に形成された電極５，５と
他のリードフレーム２ｂ、２ｃとを接続したポンディン
グワイヤ、６は上記各構成要素を一体に包囲した封止樹
脂である。1 and 2 show an example of a semiconductor device of the present invention, in which 1 is a lead frame 2 serving as a semiconductor substrate.
3 is a semiconductor element provided on the frame 2a and the element 1 is interposed between the frame 2a and the element 1, and the element 1 is fixed to the frame 2a with tie punch ink, that is, a die bonding ink. A bonding wire 6 connecting the electrodes 5, 5 formed on the element 1 and the other lead frames 2b, 2c is a sealing resin that integrally surrounds each of the above components.

ダイポンディング用材料３ば、融点が２００〜３２０℃
のフッ素系ポリマーからなり、このポリマーの粉体やシ
ート状物などをリードフレーム２ａ−にに載置してこの
上に半導体素子１を上記ポリマーの融点以上の温度下で
圧着して熱融着させることにより、上記素子１をリード
フレーム２ａにダイボンデインクしたものである。Die-ponding material 3 has a melting point of 200-320℃
A powder or sheet-like material of this polymer is placed on the lead frame 2a-, and the semiconductor element 1 is bonded onto the lead frame 2a by pressure bonding at a temperature higher than the melting point of the polymer. By doing so, the element 1 is die-bonded to the lead frame 2a.

このように、この発明においては、半導体素子１を上記
フッ素系ポリマーの熱融着性を利用してダイポンティン
グしたことをもつとも大きな特徴としたもので、こｈに
よれば従来のエポキシ樹脂やポリイミド系樹脂のり「」
躯体を用いたものに較へてダイポンディング作業を短時
間のうちに行うことができ、またポリイミド系樹脂のｆ
）ｉ１駆体のようにダイボンデインク時に発泡する心配
がないだめこれζこ起因した接着力の低下がみられず、
さらにエポキシ樹脂の如き耐湿特性の低下をほとんどき
ださないという利点が得られる。加えて、従来のタイボ
ンデインク用材料における如き高価なＡｕ。As described above, a major feature of the present invention is that the semiconductor element 1 is die-ponted using the thermal adhesive properties of the fluorine-based polymer, and according to Polyimide resin glue ""
Die-ponding work can be done in a shorter time than when using a skeleton, and the f of polyimide resin
) Unlike the i1 precursor, there is no need to worry about foaming during die bond deinking, and there is no decrease in adhesive strength caused by this.
Furthermore, there is an advantage that the moisture resistance of epoxy resins hardly deteriorates. In addition, expensive Au as in conventional tie bond ink materials.

Ａｇを使用しないものであるため、半導体装置のコスト
低減に大きく寄与できる。Since it does not use Ag, it can greatly contribute to cost reduction of semiconductor devices.

この発明において使用する上記フッ素系ポリマーとして
はフッ素含有量が通常２０重景％以上、好ましくば５０
〜７６重量％のものが用いら力、る。The fluorine-based polymer used in this invention usually has a fluorine content of 20% or more, preferably 50% or more.
~76% by weight was used.

特にパーフルオロアルケンないしパーフルオロビニルエ
ーテルのホモポリマーまたはコポリマーが好適であり、
その代表例としてはテトラフルオロエチレン−ヘキサフ
ルオロプロピレン−ｘ重合体（以下、ＦＥＰという）、
構造式；モＣＦ　２　ＣＦ　２　ＣＦ２−ＣＦ　（ＯＲ
ｆ）晧（ただし、式中Ｒｆは炭素数７以下、好ましくは
１〜３のフッ化アルキル基を意味する）で表わされるテ
トラフルオロエチレン−パーフルオロビニルエーテル共
重合体（す、下、ＰＦＡという）を挙げることがてきる
。−に記Ｐ　Ｆ　Ａの市販品としてはタイキン工業社製
商品名ネオフロンＰＦＡ、デュポン社製商品名テフロン
ＰＦＡなどがある。Particularly suitable are homopolymers or copolymers of perfluoroalkenes or perfluorovinyl ethers,
Typical examples include tetrafluoroethylene-hexafluoropropylene-x polymer (hereinafter referred to as FEP),
Structural formula; MoCF 2 CF 2 CF2-CF (OR
f) Tetrafluoroethylene-perfluorovinylether copolymer (hereinafter referred to as PFA) represented by Rf (in the formula, Rf means a fluorinated alkyl group having 7 or less carbon atoms, preferably 1 to 3 carbon atoms) can be mentioned. - Commercially available products of PFA include Taikin Kogyo Co., Ltd.'s trade name Neoflon PFA and DuPont's trade name Teflon PFA.

その他の上記フッ素系ポリマーとして、」１記構造式で
表わされるＰ　Ｆ　Ａのフッ素の一部が水素に置換され
たものや、ポリクロロ“トリフルオロエチレン、エチレ
ン−テトラフルオロエチレン共重合体（以下、ＥＴＦＥ
という）、エチレン−クロルトリフルオロエチレン共重
合体なども使用可能てある。Other examples of the above-mentioned fluorine-based polymers include those in which part of the fluorine in PFA represented by the structural formula 1 has been replaced with hydrogen, polychlorotrifluoroethylene, and ethylene-tetrafluoroethylene copolymer (hereinafter referred to as ETFE
), ethylene-chlorotrifluoroethylene copolymer, etc. can also be used.

」１記フッ素系ポリマーの融点を２００〜３２０’Ｃの
範囲に限定した理由は、２００°Ｃより低くなると半導
体装置としての耐熱性に問題を生じ、また３２０’Ｃよ
り高くなるものでは半導体素子の基板表面への熱融着に
高温を要するためである。そして、上記特定範囲の融点
とされた上記フッ素系ポリマーは、常温では非接着性で
あるが融点以上に加熱すると金属などに対して容易に融
着する性質を有しているとともに、溶融時のポリマーの
流れが少ないという特徴を有している。The reason for limiting the melting point of the fluoropolymer to the range of 200 to 320°C is that if it is lower than 200°C, there will be problems with the heat resistance of the semiconductor device, and if it is higher than 320°C, it will not be suitable for semiconductor devices. This is because a high temperature is required for thermal fusion to the substrate surface. The fluoropolymer, which has a melting point within the specified range, is non-adhesive at room temperature, but when heated above its melting point, it easily fuses to metals, etc., and when melted, It has the characteristic that there is little polymer flow.

上記フッ素系ポリマーをリードフレーム２　ａ　ｌｌに
載置するに当だってシート状物とするときは、そのシー
ト厚みは通常５〜Ｉ　Ｑ　Ｑ　％ｎＺ程度とするのがよ
い。粉体として載置するときには、素子１の加熱圧着に
よってフィルム化されたときの厚みが上記シート状物の
厚みと同程度ないしやや薄くなるような適宜の量を選べ
ばよい。When the fluorine-based polymer is formed into a sheet-like material to be placed on the lead frame 2 a ll, the thickness of the sheet is preferably approximately 5 to IQQ%nZ. When placing it as a powder, an appropriate amount may be selected so that the thickness of the element 1 when formed into a film by heat-pressing is approximately the same as or slightly thinner than the thickness of the sheet-like material.

以上のように、この発明によれば、特定のグイボンディ
ング用材料を用いたことによって生産性良好にして高信
頼性の半導体装置を提供することができる。As described above, according to the present invention, by using a specific bonding material, it is possible to provide a highly reliable semiconductor device with good productivity.

以下に、この発明の実施例を記載してより具体的に説明
する。EXAMPLES Below, examples of the present invention will be described in more detail.

実施例１ ４２アロイ板からなるリードフレーム上に厚さ１．０ｆ
ｉｍのＦＥＰフィルム（融点２７０°Ｃ）を載置し、こ
の上に半導体素子（ＭＯ８ＩＣ）をのせ、３８．０″Ｃ
２５Ｋｇ／α１１，５秒の条件で加熱圧着してダイボン
ディングした。その後、所定のワイヤボンディングおよ
びエポキシ樹脂によるトランスファーモールド成形（樹
脂封止）を行って、第１図および第２図に示される如き
この発明の半導体装置を得た。Example 1 1.0f thick on lead frame made of 42 alloy plate
Im FEP film (melting point 270°C) was placed, a semiconductor element (MO8IC) was placed on top of this, and the temperature was heated to 38.0″C.
Die bonding was carried out by heating and pressing under the conditions of 25 kg/α11.5 seconds. Thereafter, predetermined wire bonding and transfer molding (resin sealing) with epoxy resin were performed to obtain a semiconductor device of the present invention as shown in FIGS. 1 and 2.

なお、前記グイボンディングによる半導体素子の接着力
を調べるだめ、別途前記同様のクイホンディングを行っ
たのち室温まで冷却し、素子を剥がそうとしてみたとこ
ろ容易に剥離できず、素子が破壊した。これより素子の
接着強度がきわめで大きいものであることが判った。In order to examine the adhesive strength of the semiconductor element due to the above-mentioned bonding, we separately performed the same bonding as above, cooled it to room temperature, and tried to peel the element, but it was not easy to peel and the element was destroyed. It was found from this that the adhesive strength of the element was extremely high.

また、前記方法で得だ半導体装置にっき、１２ドＣ２２
気圧下での加圧浸水テスト（プレッシャークツカーテス
ト）を行い、経時的な配線腐食を調べたところ、１．（
］０００時の経過後においても配線腐食数は４０個中Ｏ
個であった。In addition, when the semiconductor device obtained by the above method is manufactured, 12 de C22
A pressurized water immersion test under atmospheric pressure (pressure test) was conducted to investigate wiring corrosion over time, and the following results were found: 1. (
]Even after 000 hours, the number of wiring corrosion is O out of 40
It was.

実施例２ ＦＥＰフィルムの代りに厚さ１５μｍのＰＶＡフィルム
（融点３０５°Ｃ）を使用し、加熱圧着条件を４００　
’Ｃ、５Ｋｙ／ｃ＋７　、５秒とした以外は、実施例１
と全く同様イこしてこの発明の半導体装置をつ（つた。Example 2 A 15 μm thick PVA film (melting point 305°C) was used instead of the FEP film, and the heat and pressure bonding conditions were set to 400°C.
Example 1 except that 'C, 5Ky/c+7, and 5 seconds.
The semiconductor device of this invention was constructed in exactly the same manner as above.

この装置につき実施例１と同様の加圧浸水テストを行っ
たところ、９００時間経過後も配線腐食数は４０個中Ｏ
個であった。まだ、グイボンディング後の接着強度につ
いても実施例１の場合と同様の良好な結果が得られた。When this device was subjected to the same pressurized water immersion test as in Example 1, even after 900 hours, the number of wiring corrosion was 0 out of 40.
It was. However, the same good results as in Example 1 were obtained regarding the adhesive strength after bonding.

実施例３ ＦＥＰフィルムの代りに厚さｌ５１ｔｎｔのＥＴＦＥフ
ィルム（融点２６０°Ｃ）を使用し、実施例１と同様に
してこの発明の半導体装置をつくった。この装置につき
実施例１と同様の加圧浸水テストを行ったところ、９０
０時間経過後も配線腐食数は４０個中３個と良好であっ
た。また、ダイホンディング後の接着強度についても実
施例１の場合と同様の良好な結果が得られた。Example 3 A semiconductor device of the present invention was produced in the same manner as in Example 1 except that an ETFE film (melting point: 260°C) having a thickness of 151 tnt was used instead of the FEP film. When this device was subjected to the same pressurized water immersion test as in Example 1, it was found that the
Even after 0 hours had elapsed, the number of wiring corrosion was 3 out of 40, which was good. Furthermore, good results similar to those in Example 1 were obtained regarding the adhesive strength after die bonding.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の半導体装置の一例を示す断面図、第
２図は同平面図である。 １・・・・・・半導体素子、２ａ・・・・リードフレー
ム、３　・・・フッ素系ポリマーからなるダイボンティ
ング用材料。 特許出願人　日東電気工業株式会社FIG. 1 is a sectional view showing an example of a semiconductor device of the present invention, and FIG. 2 is a plan view thereof. 1...Semiconductor element, 2a...Lead frame, 3...Die bonding material made of fluorine-based polymer. Patent applicant Nitto Electric Industry Co., Ltd.

Claims (1)

【特許請求の範囲】 （＋）基板と半導体素子との間に融点が２００〜３２０
°Ｃのフッ素系ポリマーを介在させ、このポリマーによ
り上記素子を」−記基板に接着固定してなる半導体装置
。 （２）フッ素系ポリマーがパーフルオロアルケンないし
パーフルオロビニルエーテルのホモ、ｆ’　ＩＪママ−
たはコポリマーからなる特許請求の範囲第（１）項記載
の半導体装置。[Claims] (+) The melting point between the substrate and the semiconductor element is between 200 and 320.
A semiconductor device in which the above-mentioned element is adhesively fixed to a substrate by means of a fluorine-based polymer having a temperature of 10°C. (2) The fluorine-based polymer is a perfluoroalkene or perfluorovinyl ether homo, f' IJ mom-
The semiconductor device according to claim (1), comprising a copolymer or a copolymer.
JP58111287A 1983-06-20 1983-06-20 Semiconductor device Pending JPS603132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58111287A JPS603132A (en) 1983-06-20 1983-06-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58111287A JPS603132A (en) 1983-06-20 1983-06-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS603132A true JPS603132A (en) 1985-01-09

Family

ID=14557398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58111287A Pending JPS603132A (en) 1983-06-20 1983-06-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS603132A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3179634A (en) * 1962-01-26 1965-04-20 Du Pont Aromatic polyimides and the process for preparing them
JPS5645060A (en) * 1979-09-21 1981-04-24 Hitachi Ltd Semiconductor device
JPS57128933A (en) * 1981-02-02 1982-08-10 Nec Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3179634A (en) * 1962-01-26 1965-04-20 Du Pont Aromatic polyimides and the process for preparing them
JPS5645060A (en) * 1979-09-21 1981-04-24 Hitachi Ltd Semiconductor device
JPS57128933A (en) * 1981-02-02 1982-08-10 Nec Corp Semiconductor device

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