JP3257173B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device,
The present invention relates to an all-pixel readout solid-state imaging device having three layers of transfer electrodes and supplying three-phase drive pulses having different phases to each transfer electrode.

[0002]

2. Description of the Related Art Conventionally, a vertical transfer electrode in a vertical register of a CCD solid-state image pickup device, for example, has a conductor portion extending in the horizontal direction and an electrode portion projecting along the vertical register formed integrally by, for example, a polycrystalline silicon layer. The wiring is made.

More specifically, a CCD solid-state image pickup device of an all-pixel readout type having three layers of vertical transfer electrodes and supplying three-phase drive pulses having different phases to each transfer electrode is shown in FIG. As shown, the first vertical transfer electrode 101 formed of the first polycrystalline silicon layer has a first conductive line portion 101a extending in the horizontal direction between the vertical light receiving portions 114 (region indicated by the width Ws). And the vertical register 112
(A region indicated by a width Wr) and a first electrode portion 101b protruding downward in the drawing (see the solid line).
The second vertical transfer electrode 102 formed of the second polycrystalline silicon layer includes a second conductive line portion 102a extending in the horizontal direction on the first conductive line portion 101a and a vertical register 1
The second electrode part 10 protruding upward along the drawing in FIG.
2b (see broken line).

A third vertical transfer electrode 103 formed of a third polycrystalline silicon layer is connected to a vertical register 112.
It is formed in a vertical direction along the vertical register 112 so as to cover the upper part (see a dashed line).
Note that this is a region channel / stopper region indicated by Wc.

[0005]

However, in the above-mentioned conventional CCD solid-state imaging device, the third vertical transfer electrode 103 is connected to the electrode portion 1 of the second vertical transfer electrode 102.
02b, and in another area, the first
Of the vertical transfer electrode 101, the area of the other vertical transfer electrodes 101 and 102, which overlaps the third vertical transfer electrode 103 in a plane, increases. However, there is a problem that the parasitic capacitance added to the portion overlapping with.

That is, the increase in the parasitic capacitance is caused by the first vertical transfer clock V1 and the second transfer electrode 102 applied to the first transfer electrode 101, as shown in the waveform diagram of FIG.
, The propagation delay of the second vertical transfer clock V2 applied to the vertical register 112 becomes large (see the rounding of the waveform indicated by a), causing a defective charge or poor charge transfer in the handling of the vertical register 112, thereby significantly deteriorating the image quality. Occurs.

Further, the increase in the parasitic capacitance causes a problem that effective amplitudes D1 and D2 at the time of charge transfer in the first transfer electrode 101 and the second transfer electrode 102 become small, and it becomes difficult to secure a dynamic range. cause.

Here, the signal charges accumulated in the light receiving section 114 are transferred to, for example, the third transfer electrode 1 during the readout period.
03, and transferred to the first to third vertical transfer clocks V1 to V3 to the first to third transfer electrodes 101 to 103, respectively, as shown in FIG.
Is applied, the signal charges transferred from the light receiving unit 114 are sequentially transferred to the horizontal register side.

At this time, for example, as shown in the waveform diagram of the second vertical transfer clock V2 in FIG. 9, when the second vertical transfer clock V2 applied to the second transfer electrode 102 is at a high level, The third vertical transfer clock V3
At the moment when the potential of the third transfer electrode 10 becomes low.
3, the second vertical transfer clock V2 is drawn into the third vertical transfer clock V3 by coupling due to parasitic capacitance between the electrode lead-out part in No. 3 and the electrode part 102b in the second transfer electrode 102. The amplitude will decrease.

In the conventional case, since the parasitic capacitance is large, the decrease in the amplitude D2 due to the coupling of the parasitic capacitance becomes very large. In particular, in the central part of the imaging region, the specified amplitude change level of the clock is low. For example, when the voltage is 9 V, the amplitude change level becomes 6 due to the decrease in the amplitude.
There is a problem that the voltage drops to around V.

Therefore, the signal charge is transferred to the second transfer electrode 102.
When transferring from the bottom to below the third transfer electrode 103, the amount of the transferred signal charge decreases due to the decrease in the amplitude level, and the dynamic range when the signal charge is converted into an imaging signal in the output circuit at the subsequent stage. Becomes narrow, and it becomes difficult to secure a predetermined dynamic range.

The present invention has been made in view of the above problems, and has as its object to reduce the parasitic capacitance caused by planar overlap of transfer electrodes.
An object of the present invention is to provide a solid-state imaging device capable of suppressing a decrease in the effective amplitude of a vertical transfer clock during transfer of signal charges and reducing a propagation delay of the vertical transfer clock.

[0013]

According to the present invention, a large number of light receiving portions 14 for converting light incident on an image pickup area into electric charges of an amount corresponding to the light amount are arranged in a matrix and arranged in a column direction. The vertical register 1 common to the light receiving unit 14
2 are formed on the horizontal register side.
An electrode group having three layers of vertical transfer electrodes 1, 2, and 3 as a set has a structure in which a large number of sets are arranged along the vertical register 12, and each of the vertical transfer electrodes 1, 2, and 3 is in phase with each other. Signal charges are applied to the vertical register 1 by applying the three-phase vertical transfer clocks V1, V2 and V3 different from each other.
In the solid-state image pickup device of the all-pixel readout system configured to transfer data to the horizontal register side along the line 2, the vertical transfer electrodes 1, 2, and 3 of the three layers are horizontally connected between the light receiving units 14 in the vertical direction. And the electrode portions 1b, 2b and 3b arranged on the vertical register 12 and contributing to the charge transfer of the signal charges, and are formed by the conductive wires of the vertical transfer electrode 3 in the uppermost layer. The portion 3a is formed continuously from a part of the upper surface of the vertical transfer electrode 2 of the intermediate layer to at least a side surface of the vertical transfer electrode 2 of the intermediate layer opposite to the side from which the electrode portion 2b extends.

In this case, the three vertical transfer electrodes 1 and 2 are used.
3 and 3, the lowermost vertical transfer electrode 1 may be formed by continuously forming the conductive portion 1a and the electrode portion 1b in the horizontal direction with the same width W1.

[0015]

In the solid-state imaging device according to the present invention, first,
The light incident on the imaging region is converted into charges of an amount corresponding to the amount of light in the plurality of light receiving units 14. And
The signal charges photoelectrically converted by the light receiving unit 14 are applied to the vertical register 12 by applying three-phase vertical transfer clocks V1, V2, and V3 having different phases to the vertical transfer electrodes 1, 2, and 3, respectively. Along the horizontal register.

At this time, in the solid-state imaging device according to the present invention, the three layers of vertical transfer electrodes 1, 2, and 3 are connected to the conductors 1a, 2a, and 3a extending in the horizontal direction between the light receiving units 14 in the vertical direction. , Electrode unit 1 arranged on vertical register 12 and contributing to the transfer of the signal charges
In particular, unlike the conventional case, the uppermost vertical transfer electrode 3 only overlaps the electrode portion 1b of the lowermost vertical transfer electrode 1 because it is formed of b, 2b and 3b. For this reason, the area of the overlapping portion in the plane is smaller than that of the conventional configuration. That is, the parasitic capacitance added between the uppermost vertical transfer electrode 3 and the other vertical transfer electrodes 1 and 2 is reduced.

In general, when the uppermost vertical transfer electrode 3 is formed on the intermediate vertical transfer electrode 2, the width of the uppermost vertical transfer electrode 3, especially the width of the uppermost vertical transfer electrode 3, is taken into account in consideration of misalignment. It is necessary to make the width W3 of the conductor portion 3a narrower than that of the vertical transfer electrode 2 in the intermediate layer.
Although the inconvenience that the wiring resistance of the uppermost vertical transfer electrode 3 is increased occurs, in the solid-state imaging device according to the present invention, in addition to the above-described configuration, the lead portion 3a of the uppermost vertical transfer electrode 3 The vertical transfer electrode 2 of the uppermost layer is formed continuously from at least part of the upper surface of the vertical transfer electrode 2 of the layer to at least the side surface of the vertical transfer electrode 2 of the intermediate layer opposite to the side from which the electrode portion 2b extends. 3, the width W3 of the conductor 3a does not need to be narrower than that of the conductor 2a in the vertical transfer electrode 2 of the intermediate layer.
An increase in wiring resistance in the uppermost vertical transfer electrode 3 can be prevented.

Accordingly, the propagation delay of the three-phase drive pulses V1, V2, and V3 applied to the transfer electrodes 1, 2, and 3 can be reduced, and the charge transfer efficiency of the vertical register 12 can be improved. In addition to the above, it is possible to avoid deterioration in image quality due to propagation delay.

Further, since the parasitic capacitance is reduced, the driving pulses V1 and V2 generated by the coupling of the parasitic capacitance at the rise or fall of the three-phase drive pulses V1, V2 and V3, respectively.
, The change in the amplitude levels D1 and D2 of the vertical register 12 can be suppressed small, and the reduction in the amount of charge handled by the vertical register 12 during the charge transfer can be effectively suppressed.

In particular, of the three vertical transfer electrodes 1, 2, and 3, the lowermost vertical transfer electrode 1 is formed by continuously forming the conductive portion 1a and the electrode portion 1b in the horizontal direction with the same width W1. Since the area of the planar overlap between the uppermost vertical transfer electrode 3 and the lowermost vertical transfer electrode 1 is further reduced, an additional space is provided between the uppermost vertical transfer electrode 3 and the other vertical transfer electrodes 1 and 2. The parasitic capacitance to be produced is further reduced.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the solid-state imaging device according to the present invention will be described below with reference to FIGS.

The solid-state image pickup device according to this embodiment is, for example, an all-pixel read-out type C in which a vertical register is driven in three phases.
CD solid-state imaging device, for example, interline transfer (IT)
Taking the structure of the method as an example, a large number of light receiving units that convert light incident on the imaging region into electric charges of an amount corresponding to the light amount are arranged in a matrix, and the light receiving units arranged in the column direction are arranged. A plurality of common vertical registers are formed to extend on the horizontal register side, and a group of three vertical transfer electrodes is arranged along the vertical register. The signal charges transferred from the section to the corresponding vertical register are transferred to the horizontal register side by row along the vertical register by applying three-phase vertical transfer clocks having mutually different phases to the respective vertical transfer electrodes. It is configured as follows.

The function of the vertical transfer in the three-phase drive will be specifically described. As shown in FIG. 1, the vertical transfer electrodes 1, 2, and 3 have different phases from each other, for example, as shown in FIG.
By applying the three-phase vertical transfer clocks V1, V2, and V3 shown in FIG. 3, as shown in FIG. 3, the signal charge e sequentially passes below the first to third vertical transfer electrodes 1 to 3 along the vertical register. Will be transferred.

That is, in the period T1, since the first and third vertical transfer clocks V1 and V3 are at a low level and the second vertical transfer clock V2 is at a high level, as shown in FIG. A potential well is formed below the transfer electrode 2, and the signal charge e is transferred and accumulated in the potential well.

In the next period T2, since the first vertical transfer clock V1 is at a high level, a potential well is formed below the first vertical transfer electrode 1, and the signal charge e becomes the first and second signal charges e. It is transferred and accumulated in a potential well formed continuously below the vertical transfer electrodes 1 and 2.

In the next period T3, since the second vertical transfer clock V2 goes low, a potential barrier is formed below the second vertical transfer clock V2, and the signal charge e
Are transferred and accumulated in a potential well formed below the first vertical transfer electrode 1. By this series of operations, the signal charge e has been moved by one vertical transfer electrode. Thereafter, the same operation is performed in the periods T4 to T7.

That is, the first to third vertical transfer clocks V1
By applying V3, the signal charge e is moved by one set (three) of the vertical transfer electrodes as indicated by the arrow. In this manner, the signal charges e are sequentially transferred to the horizontal register side in a row unit along the vertical register.

By the way, like the conventional CCD solid-state image pickup device, between the third vertical transfer electrode 3 and the first vertical transfer electrode 1 and between the third vertical transfer electrode 3 and the second vertical transfer electrode 2.
In FIG. 3, for example, in the period S in which the second vertical transfer clock V2 is at a high level in FIG. 3, a time t when the third vertical transfer clock V3 changes from a high level to a low level in FIG. Then, the second vertical transfer clock V2 is pulled into the third vertical transfer clock V3, and the amplitude thereof is reduced as shown in FIG.

Therefore, the CCD solid-state imaging device of the present embodiment has the following structure to reduce the parasitic capacitance.

In the solid-state imaging device according to the present embodiment, as shown in FIG. 4, a vertical register 12 composed of an N-type impurity diffusion region is formed on a P-type silicon substrate or a P-type well region 11. Oxide film 13 on vertical register 12
, Three layers of vertical transfer electrodes 1, 2 and 3 each made of multilayer silicon are sequentially formed.

As shown in FIG. 5, the first vertical transfer electrode 1 formed of the first polycrystalline silicon layer is entirely between the light receiving portions 14 (regions indicated by the width Ws) in the vertical direction. , A portion (hereinafter, referred to as a first electrode portion 1b) that is formed continuously in the horizontal direction and continuously overlaps with the vertical register 12 (a region indicated by the width Wr) and another portion (hereinafter, referred to as a first electrode portion 1b). (Referring to a solid line) with the same width in the horizontal direction. In addition, the second vertical transfer electrode 2 formed of the second-layer polycrystalline silicon layer is formed on the first vertical transfer electrode 1 along the second conductive line portion 2 a extending in the horizontal direction and the vertical register 12. In the drawing, the second electrode portion 2b protrudes upward (see the broken line).

The third vertical transfer electrode 3 formed of the third polycrystalline silicon layer is provided on the first vertical transfer electrode 1 and the second conductive line portion 2a in the second vertical transfer electrode 2.
It has a third conducting wire portion 3a extending upward in the horizontal direction and a third electrode portion 3b projecting downward along the vertical register 12 in the drawing (see a dashed line). That is, when the third conductor portion 3a of the third vertical transfer electrode 3 is viewed in a vertical cross section, as shown in FIG. (The side surface of the second vertical transfer electrode 2 on the side opposite to the lead-out side of the electrode portion 2b), and is formed continuously over the upper surface of the first conductive wire portion 1b exposed at the upper portion. Note that this is a region channel / stopper region indicated by Wc.

In particular, in the present embodiment, the width W1 of the first vertical transfer electrode 1 is made substantially the same as the width Wr of the vertical register 12, and the width W1 of the second conductor 2a in the second vertical transfer electrode 2 is further reduced. The width W2 (<W1) and the width W3 (<W1) of the third conductor portion 3a in the third vertical transfer electrode 3 are made substantially the same, and the second conductor portion 2a and the third conductor portion 3a are The first vertical transfer electrodes 1 are formed so as to overlap each other at the center in the width direction.

In this case, the width W1 of the first vertical transfer electrode 1
Is increased, there is a concern that the opening length of the light receiving portion 14, that is, the opening length Ls in the vertical direction is reduced. However, based on the light focusing simulation of the microlens shown in FIGS. It has been confirmed that the decrease in the length Ls does not affect the sensitivity degradation.

That is, FIG. 6 shows the case where the exit pupil is 15 mm, F1.
2. Spot diagram at 40% aperture efficiency, FIG.
FIG. 6B shows a spot diagram at an exit pupil of 15 mm, F16, and an aperture efficiency of 100%.
7 ( a) and 7 (a) , the display of the condensed portion by the microlens 22 in the light receiving unit 14 at the center of the imaging region 21 shown in FIG. Image height Hy = 1.8 in the vertical direction from the center of region 21
The display of the condensed spot by the microlens 22 in the light receiving unit 14 in the periphery separated by mm (indicated by the hatched area a) and the image in the horizontal direction from the center of the imaging area 22 shown in FIGS. 6C and 7C As can be seen from the display of the condensed portion by the microlenses 22 in the light receiving unit 14 in the periphery separated by the high Hx = 2.4 mm (indicated by the hatched area c), all the incident light is substantially at the center of the opening in each light receiving unit 14. It is understood that the light is focused at the position, and even if the vertical opening length Ls of the light receiving unit 14 is increased, it does not contribute to the improvement of the sensitivity.
This is equivalent to reducing the vertical opening length Ls of the light receiving section 14 without affecting the sensitivity.

Therefore, even if the width W1 of the first vertical transfer electrode 1 is substantially the same as the width Wr of the vertical register 12, the problem of deteriorating the sensitivity does not occur.

Here, the aperture efficiency refers to an area ratio between a central incident light flux and a peripheral incident light flux on a plane perpendicular to the optical axis. In the above simulation, F = 1.2.
In the case of (i.e., when the stop is opened), in the periphery, the so-called blur of the incident light by the objective lens or the like increases, so that the aperture efficiency at the image height Hy = 1.8 mm and Hx = 2.4 mm is 40. Calculated as%. Similarly, when F = 16 (that is, when the aperture is squeezed), the image height Hy = 1.8 mm, H
The calculation was performed on the assumption that the aperture efficiency was 100%, assuming that no shaking occurred with the objective lens or the like even around x = 2.4 mm.

As described above, the third vertical transfer electrodes 3 are connected to the conductor portions 3a extending in the horizontal direction between the light receiving portions 14 in the vertical direction and the vertical registers 12 and contribute to the transfer of signal charges. Particularly, since the third vertical transfer electrode 3 is formed by the electrode portion 3b, the third vertical transfer electrode 3 only overlaps the electrode portion of the first vertical transfer electrode 1 in a plane unlike the conventional case. Therefore, the area of the portion overlapping in a plane becomes smaller than that of the conventional configuration. That is, the third vertical transfer electrode 3 and other vertical transfer electrodes (first and second
The parasitic capacitance added between the transfer powers 1 and 2 is greatly reduced.

By the way, usually, the second vertical transfer electrode 2
When the third vertical transfer electrode 3 is formed thereon, the width of the third vertical transfer electrode 3, in particular, the width W3 of the conductive wire portion 3 a is determined in consideration of misalignment and the like. In the solid-state imaging device according to the present embodiment, in addition to the above-described configuration, there is a disadvantage that the wiring resistance of the third vertical transfer electrode 3 is increased. The conductor 3a of the third vertical transfer electrode 3 is
The third vertical transfer electrode 2 is formed continuously from a part of the upper surface of the second vertical transfer electrode 2 to at least a side surface of the second vertical transfer electrode 2 opposite to the side from which the electrode portion 2b extends. 3, the width W of the conductor portion 3a
3 does not need to be narrower than that of the conductor portion 2a in the second vertical transfer electrode 2, and an increase in wiring resistance in the third vertical transfer electrode 3 can be prevented.

Accordingly, the propagation delay of the three-phase drive pulses V1, V2, and V3 applied to the transfer electrodes 1, 2, and 3 can be reduced, and the charge transfer efficiency of the vertical register 12 can be improved. In addition to the above, it is possible to avoid deterioration in image quality due to propagation delay.

Further, since the parasitic capacitance is reduced, the driving pulses V1 and V2 generated by the coupling of the parasitic capacitance at the rising or falling of the three-phase driving pulses V1, V2 and V3, respectively.
, The change in the amplitude level of the vertical register 12 during the charge transfer can be effectively suppressed.

In particular, among the first to third vertical transfer electrodes 1 to 3, the first vertical transfer electrode 1 is formed so that the conductor portion 1a and the electrode portion 1b thereof are continuously formed in the horizontal direction with the same width W1. ,
The area of the planar overlapping portion between the third vertical transfer electrode 3 and the first vertical transfer electrode 1 is further reduced, and the third vertical transfer electrode 3 and other vertical transfer electrodes (first and second vertical transfer electrodes 1) are formed. The parasitic capacitance added between the transfer electrodes 1 and 2) is further reduced.

Accordingly, in the solid-state image pickup device according to the present embodiment, defective charge handling and defective charge transfer of the vertical register 12 are improved, image quality can be improved, and a dynamic range can be secured. .

[0044]

As described above, according to the solid-state imaging device according to the present invention, a large number of light receiving portions for converting light incident on the imaging region into electric charges of an amount corresponding to the amount of light are arranged in a matrix. A large number of vertical registers common to the light-receiving units arranged in the column direction are formed on the horizontal register side, each of which extends to the horizontal register side, and an electrode group having a set of three layers of vertical transfer electrodes is formed along the vertical register. By applying a three-phase vertical transfer clock having a different phase to each of the vertical transfer electrodes, signal charges are transferred to the horizontal register side along the vertical register. In the configured all-pixel readout solid-state imaging device, the three-layer vertical transfer electrodes are respectively disposed on a conductor portion extending in the horizontal direction between the light-receiving portions in the vertical direction, and on the vertical register. One of the electrode portions contributing to the charge transfer of the signal charge, and the conductor portion of the uppermost vertical transfer electrode is formed at least from the part of the upper surface of the intermediate layer vertical transfer electrode to the electrode in the intermediate layer vertical transfer electrode. The transfer electrodes are formed continuously on the side opposite to the side from which the parts are drawn, so that the parasitic capacitance caused by the planar overlap of the transfer electrodes can be reduced, and the effective amplitude of the vertical transfer clock during signal charge transfer And the propagation delay of the vertical transfer clock can be reduced.

[Brief description of the drawings]

FIG. 1 shows an embodiment in which a solid-state imaging device according to the present invention is applied to an all-pixel readout CCD solid-state imaging device in which a vertical register is driven in three phases (hereinafter, referred to as a solid-state imaging device according to an embodiment). 3 is a plan view schematically showing a structure in which a large number of electrode groups each including three vertical transfer electrodes are arranged along a vertical register. FIG.

FIG. 2 is a diagram showing waveforms of a three-phase vertical transfer clock applied to each transfer electrode of the solid-state imaging device according to the embodiment.

FIG. 3 is an operation conceptual diagram showing a vertical transfer operation of signal charges in a vertical register of the solid-state imaging device according to the embodiment.

FIG. 4 is a schematic sectional view illustrating a main part of the solid-state imaging device according to the embodiment.

FIG. 5 is a schematic plan view illustrating a main part of the solid-state imaging device according to the embodiment.

FIG. 6 is a diagram showing a light focusing simulation of a micro lens, in which an exit pupil is 15 mm, F1.2, and aperture efficiency is 40.
The spot diagram in% is shown.

FIG. 7 is a diagram showing a light focusing simulation of a microlens, where an exit pupil is 15 mm, F16, and aperture efficiency is 100.
The spot diagram in% is shown.

FIG. 8 is a schematic plan view illustrating a main part of a solid-state imaging device according to a conventional example.

FIG. 9 is a waveform diagram showing a three-phase vertical transfer clock applied to each vertical transfer electrode of a solid-state imaging device according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st vertical transfer electrode 1a 1st conductor part 1b 1st electrode part 2 2nd vertical transfer electrode 2a 2nd conductor part 2b 2nd electrode part 3 3rd vertical transfer electrode 3a 3rd conductor Unit 3b Third electrode unit 12 Vertical register 14 Light receiving unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/14 H04N 5/335

Claims (2)

(57) [Claims] 1. A light-receiving unit for converting light incident on an imaging area into an electric charge of an amount corresponding to the amount of light is arranged in a matrix, and is shared by light-receiving units arranged in a column direction. A plurality of vertical registers are formed to extend on the horizontal register side, respectively, and a plurality of sets of electrode groups each including three layers of vertical transfer electrodes are arranged along the vertical registers. A three-phase vertical transfer clock having a different phase from each other to transfer signal charges along the vertical register to the horizontal register side. Vertical transfer electrodes each have a conductor portion extending in the horizontal direction between the light receiving portions in the vertical direction, and an electrode portion arranged on the vertical register and contributing to the charge transfer of the signal charges. The conductive portion of the uppermost layer vertical transfer electrode is formed continuously from at least a part of the upper surface of the intermediate layer vertical transfer electrode to at least the side surface of the intermediate layer vertical transfer electrode opposite to the lead-out side of the electrode portion. A solid-state imaging device characterized by the above. 2. The vertical transfer electrode of the lowermost layer of the three vertical transfer electrodes, wherein the conductive portion and the electrode portion are formed in the same width and continuously in the horizontal direction. Item 2. The solid-state imaging device according to Item 1.