JP3252967B2 - Vertical sync separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronization separating circuit for a television receiver.

[0002]

2. Description of the Related Art As shown in FIG. 4, a vertical synchronizing separation circuit of a television receiver is composed of a capacitor C1 and a resistor R1.
1, a transistor Q1, and a current source I1. The clamp level of the clamp circuit 1 is equal to the voltage V of the power supply connected to the base of the transistor.
The voltage is lower than 1 by 1 Vbe of the transistor, and the sync tip is clamped at this level. Then, the transistor Q1 conducts during the synchronizing signal section of the input video signal, and current flows to the collector, and the load resistance R1 '
The section where the collector current flows is detected by the comparator 2 and converted into a pulse. This pulsed signal contains a horizontal synchronizing component and a vertical synchronizing component. This pulse is integrated by the integrator 3 and only the vertical synchronizing component is frequency-separated. Output a signal.

When a normal signal shown in FIG. 2 is input to this circuit, the signal is sliced by the clamp circuit 1 and a normal vertical synchronizing signal is output from the comparator 4. As shown in FIG. In a signal where the vertical synchronization section is shortened due to distortion, weak electric field, ghost, etc. during propagation of broadcast radio waves,
Since the normal vertical synchronizing signal cannot be obtained without reaching the slice level of the clamp circuit 1, this causes a vertical synchronizing flow. The contraction of the vertical synchronization signal during propagation is due to the fact that the propagation energy is small because the frequency is lower than that of the horizontal synchronization signal.

Therefore, when the slice level is made deeper, the noise margin is eliminated and the noise component N on the flat portion of the vertical synchronizing signal is easily detected, and the noise resistance is deteriorated. Conventionally, the slice level is determined while maintaining the balance between the two, but the performance satisfying both performances has not been obtained.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a vertical synchronizing separation circuit for a television receiver, which expands a signal whose vertical synchronizing section has been shortened due to distortion or a weak electric field during the propagation of a broadcast radio wave and stabilizes it. And a circuit for obtaining a vertical synchronization signal.

[0006]

SUMMARY OF THE INVENTION A vertical synchronization separation circuit according to the present invention is provided.
Path separates the horizontal synchronization signal from the supplied video signal
Synchronization separating means, and a peak of the separated horizontal synchronization signal.
Peak that holds the peak while attenuating the voltage at a predetermined slope
Comparing the holding means with the attenuated peak voltage,
A comparison means for generating an output signal when the voltage falls below a constant voltage;
The output signal generated by the comparing means is included in the video signal.
Expanding means for expanding the vertical synchronizing signal to be received,
The vertical synchronizing signal expanded by the stage is separated from the video signal.
And a vertical synchronization separating means.

[0007]

FIG. 1 shows a vertical sync separation circuit according to the present invention.
FIG. 2 shows operation waveforms of the circuit. In FIG. 1, a block A includes a vertical synchronization separation circuit similar to the conventional one shown in FIG. 4, and a block B includes a clamp circuit including a capacitor C2, a resistor R2, a transistor Q2, a current source I2, and a comparator 5. The horizontal sync separation circuit, block C
Represents a peak hold circuit including a transistor Q3, a capacitor C3, and a current source I3, and the block D represents a comparator 6,
This is an expansion circuit including a transistor Q4 and a resistor R.

The horizontal sync separation circuit B includes a resistor R2 and a capacitor C
2. Since a clamp circuit including the transistor Q2 and the current source I2 is provided, the input signal is clamped by the clamp circuit at the sync tip. Here, the time constant of the clamp is set short according to the horizontal frequency (C2 · R
2 <C1 · R1), there is no vertical synchronization component, and only the horizontal synchronization signal is extracted.

For this purpose, the horizontal synchronizing signal pulsed and outputted by the comparator 5 is taken out as a solid line waveform shown in FIG. 2 and inputted to the base of the transistor Q3 constituting the peak hold circuit C. . From the emitter of the transistor Q3, a peak hold waveform shown by a dotted line in FIG. 2 is obtained. This peak hold waveform is compared with the slice level setting voltage Ve by the comparator 6.
, A voltage lower than the slice level is detected, and is pulsed into a waveform as shown in FIG. The output of the comparator 6 is input to the base of the transistor Q4 of the expansion circuit D.

The operation of the vertical synchronizing signal reaching the slice level and the operation when the vertical synchronizing signal shrinks and does not reach the slice level will be described below with reference to FIG. As described above, the horizontal synchronization signal of the video signal is separated by the horizontal synchronization separation circuit B, and the vertical synchronization signal is separated by the vertical synchronization separation circuit A. When the vertical synchronizing signal has not reached the slice level (the waveform shown in FIG. 2), the emitter potential of the transistor Q1 also changes between the base and the emitter during the vertical synchronizing period t2 as shown in FIG. Since the potential is not sufficient to turn on the transistor Q1, the transistor Q1 is turned off, and in the vertical synchronization section t1 in which the transistor Q4 of the expansion circuit D is not turned on, as shown by a dotted line in FIG. Are supplied to the current source I1 from the video signal input side which is a low impedance source.

From this state, in a section t3 (the waveform shown in FIG. 2) in which the transistor Q4 of the expansion circuit D is turned on, the video signal input side, which is a low impedance source,
A current is drawn toward the current source I1 and the collector of the transistor Q4 of the expansion circuit D, the emitter potential of the transistor Q1 drops, and the potential of the sink chip starts to expand. At this time, when the potential of the transistor Q1 has not reached the clamp level, the current is supplied to the current source I1 and the transistor Q4 of the expansion circuit D as indicated by the solid line in FIG. Then, the current from the video signal input side is forcibly drawn into the collector of the transistor Q4, the current is also drawn into the current source I1, the capacitor C1 is charged, and the emitter potential of the transistor Q1 is pulled in the negative direction. When the emitter potential of the transistor Q1 drops and the emitter potential of the transistor Q1 reaches the clamp level, the transistor Q1 is turned on and the current is changed to the power supply Vcc as shown by the solid line in FIG.
Flows through the transistor Q1 to the current source I1 and the transistor Q4 of the expansion circuit D. The vertical synchronizing section that has reached the clamp level is a section t during which the expansion circuit D is turned on.
Sliced at 3.

As described above, the transistor Q of the expansion circuit D
4, in the section t3 of the waveform shown in FIG. 2, the current is forcibly drawn, whereby the contracted vertical synchronizing signal is pushed down, and the waveform shown in FIG. The waveform is expanded as shown and reaches the slice level from the middle of the vertical synchronization section. Therefore, the expanded vertical synchronizing signal can be sliced at a predetermined slice level, sent to the integrator 3 via the comparator 2, and extracted as a vertical synchronizing signal.

On the other hand, when the vertical synchronizing signal reaches the slice level and does not contract, the emitter potential of the transistor Q1 always reaches the clamp potential and the transistor Q1
1, the current flows from the power supply Vcc to the current source I1 and the expansion circuit D via the transistor Q1, and the clamp circuit operates normally. The level of the extension is determined by the amount of current forcibly drawn into the transistor Q4, and this amount of current can be set by the resistance value of the resistor R connected to the collector of the transistor Q1.

[0014]

According to the present invention, it is possible to expand a contracted vertical synchronizing signal, so that it is not necessary to set a slice level deeply, so that noise immunity is improved. As a whole, a vertical sync separation circuit that can be built in an integrated circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a vertical sync separation circuit of the present invention.

FIG. 2 is a diagram showing operation waveforms of the present invention.

FIG. 3 is an explanatory diagram of the operation of the vertical sync separation circuit of the present invention.

FIG. 4 is a diagram showing a conventional vertical separation circuit.

[Explanation of symbols]

A: Vertical sync separation circuit B: Horizontal sync separation circuit C
..Peak hold circuit D..Expansion circuit

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Satoshi Miura 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-54-63612 (JP, A) JP-A Sho 59-30372 (JP, A) JP-A-63-90978 (JP, A) JP-A-63-244977 (JP, A) JP-A-59-132284 (JP, A) JP-A-60-186765 (JP, A) U) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (1)

(57) [Claims] A horizontal synchronizing signal is separated from a supplied video signal.
Separating horizontal synchronization separating means, and separating the peak voltage of the separated horizontal synchronization signal by a predetermined slope.
Peak holding means for holding the peak while attenuating , and comparing with the attenuating peak voltage,
Comparison means for generating a can output signal, to the video signal by an output signal said comparing means generates
Decompression means for decompressing a vertical synchronization signal included in the video signal,
A vertical sync separation circuit for separating the signal from a signal .