KR860001146B1 - Noise eliminated circuit - Google Patents

Abstract

Noise elimination circuit, which eliminates a noise from nobroadcasting channel reception and a voice signal from a closed channel and a noise generated in scattered synchronization, comprises an AFC voltage detector, a reference voltage generator varied by a resistor(R1) and a variable resistor(VR1), a synchronizing circuit(11), first comparator(13) which compares a voltage from AFC voltage and a reference voltage, second comparator(14) which makes a pulse generated by comparing a horizontal synchronizing signal and a pulse from AFC detection signal, and a switching circuit(15) which makes a connection between an audio amplifier and an intermediate freq. discriminanter.

Description

Broadcasting channel reception noise cancellation circuit

1 is an operation block diagram of a voice circuit of a conventional television receiver.

2 is a block diagram of an audio circuit operation of the television receiver according to the present invention.

3 is a block diagram of an AFC voltage detection circuit during normal and abnormal reception of a television receiver according to the present invention.

4 is a concrete circuit diagram of FIG.

5 is a block diagram of a broadcast-free channel reception noise canceling circuit.

6 is a detailed circuit diagram of FIG.

7 (a) to 7 (e) are operational waveform diagrams in respective parts of FIG.

8 (a) to 8 (g) are operational waveform diagrams in respective parts of FIG.

＊ Explanation of symbols on main parts of drawing

4: voice intermediate frequency detection circuit 5: voice amplification circuit

10: no-broadcast reception noise cancellation circuit 11: horizontal synchronization signal detection circuit

12: reference voltage generation circuit 13: the first comparator

14: second comparator 15: second switching circuit

20: high level comparator 21: low level comparator

22: first switching circuit 24: high level reference voltage generating circuit

25: low level reference voltage generation circuit

The present invention relates to a noise canceling circuit of a television receiver, and in particular, when a channel that is not broadcasted on a television receiver is received or a channel where a broadcast is received but synchronization is not fully adjusted, the noise and adjacent channels that occur when synchronization is disturbed. A circuit for removing audio signal components is provided.

In the conventional television receiver, as shown in the block diagram of FIG. 1, the radio wave inputted through the antenna 1 is tuned to the amplified video and audio signal after a specific channel is selected in the tuner circuit 2 and amplified by high frequency. After mixing the frequencies generated by the local oscillator in the furnace (2), amplifying again in the intermediate frequency amplification circuit (3), and separating the audio signal and the video signal, the voice signal is detected by the voice intermediate frequency detection circuit (4) After that, the sound amplifier amplifies the speaker 6 by sound amplification in the audio amplification circuit 5, while the separated video signal is detected by the image detection circuit 7 and then the first video amplification circuit 8. After the first image amplification, the image was displayed on the screen of the television receiver according to the video portion block diagram 9 of the television receiver.

Therefore, in the circuit of the conventional television receiver as described above, when the screen does not come out or the screen collapses even when the broadcast comes out, a large noise occurs to give the viewer of the television receiver an uncomfortable channel. When trying to find a specific channel with the sweep function, it was impossible to mute all channels without a broadcast individually.

Accordingly, an object of the present invention is to provide a noise canceling circuit capable of removing noise and voice signal components in adjacent channels that occur when a channel is not being broadcast on a television receiver or when synchronization is disturbed due to incomplete broadcasting reception. To provide.

Therefore, in order to achieve the above object of the present invention, the AFC detection output from a known automatic frequency control circuit (AFC circuit) of a television receiver and the horizontal synchronization signal output from a known horizontal synchronous separation circuit are made negative. Use as input signal of.

According to the present invention, the AFC voltage detection circuit in the normal and abnormal operation that detects the AFC voltage in the normal and abnormal operation of the television receiver and outputs a pulse corresponding thereto among the output voltages of the AFC circuit, and is variable by the variable resistor. A reference comparator for generating a constant reference voltage, a first comparator for inputting the AFC detection voltages during the normal and abnormal operation and the reference voltages to generate pulses according to the comparison of the two voltages, and horizontal synchronization A horizontal synchronous signal detection circuit for inputting a signal and detecting a horizontal synchronous signal input time and an output of the first comparator and the horizontal synchronous signal detection circuit are inputted to simultaneously input a horizontal synchronous signal and an AFC detection signal during normal operation. A second comparator that detects a time and outputs a pulse, and an AFC detection signal during normal operation by inputting an output of the second comparator Only when the input horizontal synchronization signal is provided to an audio intermediate frequency detection circuit and a non-broadcast channel reception noise cancellation circuit of claim 2 characterized by consisting of a switching circuit to each other by connecting the audio amplifier circuit.

In the embodiment of the present invention, the AFC voltage detection circuit in the normal and abnormal operation includes a high level comparator, a low level comparator, and a first switching circuit so that the normal and abnormal voltages of the AFC detection voltage of the television receiver are provided. Is detected and a corresponding pulse is generated.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a block diagram in which the broadcast free noise canceling circuit 10 according to the present invention is adapted between the voice intermediate frequency detection circuit 4 and the voice amplifier circuit 5 among the voice circuits of a conventional television receiver.

3 is a block diagram of an AFC voltage detection circuit in normal and abnormal operation of a television receiver, and includes a high level reference voltage generator 24, a low level reference voltage generator 25, a high level comparator 20, and a low level. The comparator 21 and the first switching circuit 22 are constituted.

4 is a circuit diagram embodying FIG. 3, in which resistors R ₂₀ and R ₂₁ correspond to the high level reference voltage generating circuit 24 of FIG. 3, and resistors R ₂₆ and R ₂₇ correspond to the low level reference voltage of FIG. The generator circuit 25, resistors R ₂₂ -R ₂₄ and diodes D ₄ and NPN transistors Q ₁₃ -Q ₁₅ are the high level comparators 20 of FIG. 3, resistors R ₂₈ -R ₃₀ and NPN transistors Q ₁₆ -Q ₁₉ And diode D _{5 corresponds} to the low level comparator 21 of FIG. 3, resistors R ₃₁ to ₃₅ and NPN transistors Q _{20 to} Q ₂₃ respectively correspond to the first switching circuit 22 of FIG.

7 (a) to 7 (e) are operating waveform diagrams of the respective parts of FIG. The waveform of FIG. 7 (a) is an AFC voltage waveform diagram outputted from the AFC circuit of FIG. 3 or the conventional television receiver and input to the input terminal 26 of FIG.

In Fig. 7 (a), H is an upper limit value of the AFC voltage during normal operation of the television receiver adjusted by the resistor R ₂₁ of the high level reference voltage generator 24, and L is a low level reference voltage generator 25. Are the voltages input to the high level comparator 20 and the low level comparator 21 as reference voltages which become the lower limit values of the AFC voltage in the normal operation of the television receiver adjusted by the resistor R ₂₇ .

Wherein the 7 (a) If the AFC voltage is input to the input terminal 26, such as help, the time T ₁ during the NPN transistor Q ₁₇ of the low-level comparator 21 is off times T ₂ and T ₃ while since the on-the NPN The selector voltage of transistor Q ₁₇ is as shown in FIG. 7 (b).

On the other hand, since time T ₁ and T ₂ are turned off during NPN transistor Q ₁₄ of high-level comparator 20 and turned on during time T ₃ , the NPN transistor Q ₁₄ collector voltage becomes as shown in FIG. 7 (c) and the first switching circuit 22. ) Is input to the base of the NPN transistor Q ₂₁ , which is a component part of the?

In addition, the circuit composed of the NPN transistors Q ₁₉ and Q ₂₀ is a current repeater circuit (current miller), so that when the NPN transistor Q ₁₇ of the low level comparator 21 is turned off (during time T ₁ ), the resistance R ₃₁ current does not flow. When the NPN transistor Q _{23, which} is a component of the switching circuit 22, is turned off and the NPN transistor Q _{17 is turned} on (during time T ₂ T ₃ ), the resistor R ₃₁ current flows and the voltage drop causes the NPN transistor Q _{23 to be turned} on. That is, the transistor Q ₂₃ base voltage becomes the same waveform as the seventh (d).

Therefore, the output terminal of NPN transistor Q ₁₄ collector output waveform of claim 7 (c) a separate waveform with a high level the comparator 20 input to the base of the input terminal of NPN transistor Q ₂₁ of the first switching circuit 22, the time T ₁ during the off NPN transistors Q ₂₃ NPN transistor Q ₂₁ off, so the NPN transistor Q ₂₁ collector voltage is high, the time T ₂ while the collector voltage of NPN transistors Q _21, so the whole all the NPN transistors Q ₂₁ and Q ₂₃ are low Since the NPN transistors Q ₂₃ and Q _{21 are turned} off during the time T ₃ , the NPN transistor Q ₂₁ collector voltage becomes high. As shown in FIG. 7E, the AFC voltage detection circuit when the waveform is normal or abnormal operation is performed. It outputs from the output terminal 27 of and the voltage in time T2 is _{shown as} the voltage in normal operation. 5 is a non-broadcast reception noise canceling circuit for inputting the horizontal synchronization signal and the voltage waveform of FIG. 7 (e) output from the output terminal 27 of the AFC voltage detection circuit during normal or abnormal operation according to the present invention. 10 is an internal block diagram.

As shown in FIG. 5, the broadcast-free reception noise canceling circuit 10 includes a horizontal synchronous signal input terminal 16 for inputting the horizontal synchronous signal, and an AFC detection voltage during normal and abnormal operation. An input terminal 17 input from the output terminal 27, a horizontal synchronous signal detection circuit 11 that inputs a horizontal synchronous signal input to the horizontal synchronous signal input terminal 16, and the normal and abnormal operation. A first comparator 13 for inputting the AFC detection signal during normal and abnormal operation inputted to the AFC detection voltage input terminal 7 of the controller and the output signal of the reference voltage generator 12, and the horizontal synchronous signal detection circuit; The second comparator 14 having the output of the first comparator 13 and the output of the first comparator 13 and the output of the second comparator as an input, and the voice intermediate frequency detection circuit 4 of air For switching the negative amplifier circuit 5 of the second switch It consists of a circuit 15.

6 is an actual circuit diagram incorporating the block diagram of the broadcast-free reception noise canceling circuit 10 of FIG. 5 according to the present invention, and FIGS. 8 (a)-8 (g) are the broadcast-free reception according to the present invention. 6 is an operation waveform diagram of each part of FIG. 6 which is a detailed circuit diagram of the noise canceling circuit 10.

The circuit composed of resistor R ₁ variable resistor VR ₁ of FIG. 6 corresponds to the reference voltage generating circuit 12 of FIG. 5, and the circuit composed of resistors R ₉ -R ₁₂ and capacitors C ₁ and NPN transistors Q ₇ , Q ₈ is provided. The circuit consisting of the horizontal synchronizing signal detection circuit 11 of 3 degrees, the resistors R ₂ -R ₆ , the diodes D _1, and the NPN transistors Q _1- Q ₃ consists of the first comparator 13 of FIG. 3 and the resistors R ₅ -R ₈ . The circuit composed of diode D ₁ and NPN transistors Q ₄ -Q ₆ consists of the second comparator 14 of FIG. 5, the circuit composed of resistors R ₁₃ -R ₁₈ and diode D ₂ NPN transistors Q ₉ -Q ₁₁ of FIG. 2 are circuits corresponding to the switching circuits 15, respectively.

Operational waveforms of the respective parts of the broadcast-free reception noise canceling circuit 10 of FIG. 6 shown in FIGS. 8A to 8E are described below. It demonstrates in detail with reference to FIG.

8 (a) is a waveform diagram a inverted from FIG. 7 (e), and the variable resistor VR ₁ is adjusted in the reference voltage generating circuit 12 composed of the resistor R ₁ and the variable resistor VR ₁ to adjust the television set of the television receiver. A waveform diagram showing a constant reference voltage waveform b in which the reference voltage is set slightly smaller than the AFC detection voltage in normal operation.

Therefore, by adjusting the value of the variable resistance VR ₁ of the reference voltage generating circuit 12, the reference voltage b is slightly lower than the base voltage of the NPN transistor Q ₂ (waveform a in FIG. 8 (a)) (the AFC detection voltage during normal operation). It can be set low so that the AFC detection state can be detected.

Therefore, in the case of abnormal reception, the variable resistance VR ₁ can be adjusted as shown in FIG. 8 (a) so that the AFC detection voltage is equal to or less than the reference voltage which is the base input voltage of the NPN transistor Q ₁ . Therefore, the base voltage V _Q1B of the NPN transistor Q ₁ becomes as follows when the power supply voltage is Vcc.

As can be seen from Equation (1), the reference voltage b inputted to the base of the NPN transistor Q ₁ of FIG. 8 (a) can be set slightly smaller than the AFC detection voltage during normal operation by adjusting the variable resistance VR ₁ . do.

Therefore, when the AFC detection voltage a and the reference voltage b during normal and abnormal operation as in the eighth (a) are input to the bases of the NPN transistors Q ₂ and Q _1, the base of the NPN transistors Q ₁ during the times T ₁ and T ₃ , respectively. input voltage, the reference voltage b is the NPN transistor Q ₂ is larger than the AFC detection voltage a at the time of the base input voltage of the abnormal reception of the NPN transistor Q ₂ is turned off the NPN transistor Q ₁ is turned on, and the time T ₂ In contrast, since the NPN transistor Q ₂ is turned on and the NPN transistor Q ₁ is turned off during T ₄ , the output waveform of the first comparator output from the collector of the NPN transistor Q ₂ becomes as shown in FIG. The input is made to the base of the NPN transistor Q ₄ , which is an input of the comparator.

On the other hand, the NPN transistor Q ₃ , diode D _1, and resistors R ₃ , R ₅ , and R ₆ constitute a constant current circuit, so that the collector current of NPN transistor Q ₃ is called I _Q3S and the voltage drop during conduction of diode D ₁ is V _D1 . The collector current I _Q3S of the NPN transistor Q ₃ becomes as follows.

Therefore, the above equation (2) NPN transistor Q ₂ is turned ON NPN transistor Q ₁ is the base input voltage V _Q4BL of the collector voltage of which is the off time T ₂ and T ₄ the NPN transistor in the Q ₂ that is, NPN transistor Q ₄ Since the voltage drop of the resistor R ₂ due to the current of is subtracted from the power supply voltage Vcc, the following equation is obtained.

Therefore, the output voltage output from the collector of Claim 8 (b) time as separate waveform T ₁ and T _3, so during the state in which the NPN transistor Q ₂ off transistor Q ₂ is substantially a value close to the voltage the voltage Vcc, the time T ₂ and T ₄ during the first 8 (b) a separate low (low) output voltage the resistance R ₂ as can be seen in V _Q4BL of the formula (3), output from the collector of the NPN transistor Q ₂ R _5, R ₅ It can be controlled by R ₆ and V _D1 .

On the other hand, when the negative horizontal synchronization signal as shown in FIG. 8 (c) is inputted to the horizontal synchronization signal input terminal 16 of the horizontal synchronization signal detection circuit 11 and input to the base of the NPN transistor Q ₈ of FIG. during the time T ₁ is when there is no signal input is the base voltage of the NPN transistor Q ₈ is high the NPN transistor Q ₈ is in the on state, and the base voltage of the NPN transistor Q ₇ is set to 0 V the NPN transistor Q ₇ is turned off since in a state where the base input voltage of the NPN transistor Q ₅ of the second comparator 14 is almost zero volts. However, when the horizontal sync signal to be able to enter the base voltage of the horizontal synchronizing signal input NPN transistor Q ₈ via the terminal 16 is therefore decreased to a low state of approximately 0 volts at high the NPN transistor Q ₈ is in the off state the base voltage of the NPN transistor Q ₇ is so nearly approaches the power supply voltage Vcc, the NPN transistor Q ₇ is to be turned on. In this case therefore it is to be rapidly charged in accordance with the capacitor C ₁ the resistance R _9, the time constant determined by the capacitance of the resistor R ₉ and a capacitor C ₁ through the NPN transistor Q _7. When the horizontal synchronization signal goes from the low state to the high state, the NPN transistor Q is turned on and the NPN transistor Q ₇ is turned off, so that the voltage charged in the capacitor C ₁ is discharged through the resistor R ₁₁ and the NPN transistor Q ₈ . . The discharge time T _CRD at this time is as follows.

Therefore, the value of the discharge time T _CRD of Equation (4) is set to about 630 μs at about 10 times one cycle of the horizontal synchronization signal. Therefore, during the time T ₂ and T ₃ when the horizontal synchronous signal is input, the voltage becomes smooth due to the rapid charging time set by the capacitance of the resistor R ₉ and the capacitor C ₁ and the discharge time T _CRD .

Therefore, time T ₂ and T ₃ of, that is, the horizontal sync signal when the input base voltage of the NPN transistor Q ₅ is at a high state, again time the horizontal synchronizing signal is not input T ₄ while the capacitor C ₁ as during and the time T ₁ The charging voltage of is discharged through the resistor R ₁₁ and the NPN transistor Q ₈ to attenuate to almost 0 volts.

Therefore, the waveform as shown in FIG. 8 (d) is input to the base of the NPN transistor Q ₅ .

As described above, when the waveforms as shown in FIG. 8 (b) and the waveforms as in FIG. 8 (d) are input to the NPN transistors Q ₄ and Q _{5 which} are inputs of the second comparator, respectively, the eighth among T ₁ , T ₃ , and T Since the base input voltage of the NPN transistor Q ₄ as shown in (b) is greater than the base input voltage of the NPN transistor Q ₅ as shown in FIG. 8 (d), the NPN transistor Q ₄ is turned on and the NPN transistor Q ₅ is turned off. The input voltage output from the collector of the NPN transistor Q ₅ and applied to the base of the NPN transistor Q ₉ becomes a voltage near the power supply voltage Vcc.

On the other hand, during the time T ₂ , the low voltage as shown in FIG. 8 (b) becomes V _Q4BL given in Equation (3). Thus, as described above, the value of V _Q4BL is input during the time T _{2 when the} horizontal synchronous signal in FIG. 8 (d) is input. Since the NPN transistor Q ₄ is set to be smaller than the horizontal synchronous signal detection voltage, the NPN transistor Q ₄ is turned off and the NPN transistor Q ₅ is turned on so that the voltage output from the collector of the NPN transistor Q ₅ and input to the base of the NPN transistor Q ₉ can be set to a low state. .

Therefore, the base input voltage of the NPN transistor Q ₉ during the time T ₂ is referred to as V _Q9BL , and the collector of the NPN transistor Q ₆ of the constant current circuit composed of the resistors R ₅ , R ₆ , R ₇ and the diode D ₁ and the NPN transistor Q ₆ . If the constant current is I _Q6S , I _Q6S and V _Q9BL become as follows.

Therefore, time as help claim _{8 (e) T 1, T} 3, T 4 has to be a little voltage close to Vcc time T ₂ during a has a value of V _Q9BL given by the formula (6) Since the time T ₂ the low voltage value of Can be adjusted by the resistors R ₅ , R ₆ , R ₈ , R ₉ and VD ₁ .

Therefore, as described above, the waveform as shown in FIG. 8 (e) is input to the base of the NPN transistor Q ₉ , which is the input of the second switching circuit 15.

Meanwhile, the collector constant current of the NPN transistor Q ₁₀ of the constant current circuit composed of the resistors R ₁₃ , R ₁₄ , R ₁₆ and the diode D ₂ and the NPN transistor Q ₁₀ , which are components of the switching circuit 15, is referred to as I _Q10S , and the diode D ₂ Also, if the voltage drop is V _D2 , I _Q10S becomes as follows.

Therefore, the constant current I _Q10S flowing through the collector of the NPN transistor Q ₁₀ given in Equation (7) can be adjusted to accurately turn on or off the NPN transistor Q ₁₁ .

Now, during the times T ₁ , T ₃ and T ₄ , the NPN transistor Q ₉ is turned on because the base input voltage of the NPN transistor Q ₉ is almost close to Vcc as shown in FIG. 8 (e). The voltage drop of the resistor R ₁₅ and the base of the NPN transistor Q ₉ by the sum of the current flowing through the base of the NPN transistor Q ₁₁ when the constant current I _Q10S flowing through the collector of the NPN transistor Q ₁₀ and the NPN transistor Q ₁₁ are on. The value obtained by subtracting the meter-to-meter saturation voltage from the base applied voltage of the NPN transistor Q ₉ is applied as the base voltage of the NPN transistor Q ₁₁ . At this time, the constant current I _Q10S given by Equation (7) is adjusted so that the NPN transistor Q ₁₁ is turned on. The time T ₂ during the first 8 (e) degree of time T ₂ the resistance R ₁₅ of the voltage drop across the base emitter saturation voltage of the NPN transistor Q ₈ by the constant current I _Q10BL the base voltage V _Q9BL of NPN transistor Q ₉ takes the The subtracted voltage is applied to the base of the NPN transistor Q ₁₁ and the voltage is set by adjusting the value of the constant current I _Q10S so that the NPN transistor Q ₁₁ can be turned off.

Therefore, the base voltage of the NPN transistor Q ₁₁ as described above, the 8 (f) during T _1, T ₃ and T ₄ as assist will have a voltage that may be on the NPN transistor Q ₁₁ time T ₂ during the NPN transistor It will have a value of almost 0 volts to turn Q ₁₁ off.

Therefore, as described above, during the times T ₁ , T _3, and T ₄ , the NPN transistor Q ₁₁ is turned on, so that the voice detection output detected by the voice intermediate frequency detection circuit 4 among the voice circuits of a known television receiver is a resistor R _18. , The NPN transistor Q _{11 is} bypassed through the resistor R ₁₇ , so that the signal input to the known voice amplifier circuit is extremely small, and during the time T ₂ , the NPN transistor Q ₁₁ is turned off. The voice detection output from the input is input to the well-known voice amplification circuit 5 through the resistor R ₁₈ and is soundproofed through the speaker 6, so that the voice detection signal as shown in FIG. 8 (g) at the collector of the NPN transistor Q ₁₁ . You get

Therefore, the present invention detects only when the horizontal synchronous signal and the AFC detection output are operated in a fully received state so that the voice intermediate frequency detection output is transmitted to the input of the voice amplifier circuit, thereby eliminating a channel that is not broadcasted by the television receiver. When receiving or receiving a broadcast channel, but not completely adjusted, the noise generated when the synchronization is disturbed and the component of the audio signal of the adjacent channel has the advantage that the viewer of the television receiver can watch cheerfully without discomfort.

Claims (4)

A circuit for removing noise generated when receiving a broadcast-free channel, wherein the output voltage of the AFC circuit detects AFC voltages in normal and abnormal operation of the television receiver and outputs corresponding pulses in normal and abnormal operation. A reference voltage generation circuit (12) comprising a detection circuit, a resistor (R ₁ ) and a variable resistor (VR ₁ ) for generating a variable reference voltage, and the AFC detection voltage during normal and abnormal operation described above. A first comparator 13 for inputting one reference voltage to generate a pulse according to the comparison of the two voltages, a horizontal synchronous signal detection circuit 11 for inputting a horizontal synchronous signal and detecting a horizontal synchronous signal input; A second comparator (1) which detects when a horizontal synchronous signal for inputting the output of the first comparator and the horizontal synchronous signal detection circuit 11 and an AFC detection signal for normal operation are simultaneously inputted and outputs a pulse 4) and a second switching circuit which connects the audio intermediate frequency detection circuit and the audio amplifier circuit only when the AFC detection signal and the horizontal synchronization signal in normal operation are inputted by the output of the second comparator. 15) a non-broadcast channel reception noise cancellation circuit, characterized in that. The high voltage reference circuit 24, the low level reference voltage generator 25, the high level comparator 20, the low level comparator 21, and the AFC voltage detection circuit in normal and abnormal operation. And a first switching circuit (22) for detecting normal and abnormal voltages of the AFC detection voltage of the television set and generating a pulse corresponding thereto. The horizontal synchronous signal detection circuit (11) according to claim ₁ , further comprising a discharge circuit connected in series by a resistor (R ₁₁ ), a capacitor (C ₁ ), and a transistor (Q ₈ ) of the horizontal synchronous signal detection circuit (11). No-broadcast channel reception noise cancellation circuit, characterized in that it has a double discharge time constant. 2. The broadcast free channel reception noise canceling circuit according to claim 1, characterized in that the second switching circuit (15) comprises a constant current circuit to accurately turn on or off the transistor (Q ₁₁ ) by the constant current of the constant current circuit.

Images