JPS602824B2 - Synchronous separation circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a synchronization separation circuit for a television receiver.
In particular, the present invention relates to a synchronization separation circuit that stably obtains a vertical synchronization signal.

If noise enters the video signal, the slice level of the sync separation circuit becomes shallow, or if there is an effect such as coasting, the amplitude of the vertical sync part of the video signal becomes 4.0% lower than that of the horizontal sync part. It is known that there is.

In a normal case, the video signal output from the detection circuit has approximately the same amplitude in the vertical synchronization part V and the horizontal synchronization part as shown in FIG. 1A. Therefore, when detected at the slice level (dashed line), normal vertical and horizontal synchronization signals as shown in FIG. 1C can be obtained. However, if the amplitude of the vertical synchronization part of the video signal decreases due to ghosting, etc., or if the slice level becomes shallow due to noise, the vertical synchronization part will no longer exceed the slice level, as shown in Figure 1B. The equal number separation signal is one in which the vertical synchronization signal as shown in FIG. 1D is omitted. Therefore, if the video signal contains noise or is affected by ghosts, vertical synchronization may be lost even though the screen is good. Therefore, the following efforts have been made to improve the above-mentioned problems by improving the AGC, improving the performance of the noise canceller, and deepening the slice level of the synchronization separation circuit. However, satisfactory performance could not be obtained in either case. In view of the above, this invention has an improved synchronization signal separation circuit that can stably obtain a vertical synchronization signal even when the slice level becomes shallow or the level of the vertical synchronization part of the video signal is lower than that of the horizontal one. is intended to provide.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In this figure, a received signal obtained by an antenna 1 passes through a high frequency amplifier circuit 2, and is mixed with the output from a local oscillation circuit 4 in a mixing circuit 3. Ru.

The intermediate frequency signal thus obtained passes through an intermediate frequency amplification circuit 5 and is detected by a detection circuit 6. The video signal obtained by detection is sent to a picture tube 8 via a video amplifier circuit 7. The video signal from the detection circuit 6 is further sent to a sync separation circuit 9 to obtain a horizontal sync signal and a vertical sync signal. The vertical synchronizing signal passes through the vertical deflection circuit 10 to the vertical deflection yoke of the picture tube 8.
The horizontal synchronization outputs are sent to the horizontal deflection yoke of the picture tube 8 via the horizontal deflection circuit 11, respectively. The configuration of the synchronization separation circuit 9 is as follows.

A clamp circuit 20 is connected to the output side of the detection circuit 6, and this clamp circuit 20 is connected to the level detection circuit 6 via an OR circuit 50. A clamp circuit 40 is further connected to the output side of the detection circuit 6 via a low-pass filter 30, and is connected to a level detection circuit 60 via an OR circuit 50. The output side of this level detection circuit is connected to the vertical deflection circuit 10 via the integrating circuit 70 and to the horizontal deflection circuit 11 via the differentiating circuit 80.
is connected to. Clamp circuit 20 includes resistors 21 and 22
, a capacitor 23 and a diode 24. The low-pass filter 30 consists of a resistor 31 and a capacitor 32, and the clamp circuit 40 consists of a resistor 42, a resistor 41 and a diode 43. The anodes of the diodes 24 and 43 are both connected to the base of a level detection transistor 63 to form an OR circuit 50. The level detector 60 includes a transistor 63 and a base bias resistor 61
, 64 and a collector resistor 62. Integrating circuit 70
consists of a resistor 71 and a capacitor 72. Further, the differentiating circuit 80 includes a resistor 81 and a capacitor 82. FIG. 3 is a block diagram showing the synchronization separation circuit 9 in FIG. 2 using blocks with the same reference numerals, and FIG. 4 shows signals at points A, B, C, and D in FIGS. 2 and 3. FIG.

The operation will be explained with reference to FIGS. 3 and 4 and FIGS. 1 and 2. In FIG. 2, a video signal is input to a clamp circuit 20 and the signal is clamped to a potential V.

Further, the video signal is clamped to V2 after the vertical synchronization part is emphasized more than the horizontal synchronization part via the low-pass filter 30. By the way, from Figure 2, V, = V2 = Vc
c-VBB-Vr Vcc; power supply voltage VBE; base-emitter voltage Vf of transistor 63
; This is the voltage drop caused by the diodes 24 and 43, and the signals at points A and C in FIG. 2 above are at the same level V=Vcc-
It is clamped at VB8-Vf.

Here, the amplitude of the vertical synchronization part as shown in FIG.
・Input the video signal.

First, the video signal is clamped to V=Vcc - V88 - Vr by the clamp circuit 20 while the vertical synchronization part is small.
A signal as shown in FIG. 4A is obtained at point A (FIGS. 2 and 3). In addition, the video signal becomes a signal (FIG. 4B) in which the vertical synchronizing part is emphasized by the low-pass filter 30, and this emphasized vertical synchronizing part is clamped to V=Vcc-VB8-Vr to point C (second 3), the signal shown in FIG. 4C is obtained. The signals at points A and C in FIGS. 2 and 3 are combined via an OR circuit 50. The vertical synchronization part and the horizontal synchronization part of the combined signal are at the same level as shown by the circle in FIG. 4. Therefore, the synchronization separated output obtained by passing this combined signal through the detection circuit 60' becomes clear as shown in FIG. 1C. Also, the video signal is
Of course, even in the normal case shown in FIG. 1C, the above operation can produce the output shown in FIG. 1C. As described above, according to the present invention, even if the amplitude of the vertical synchronizing part of a video signal becomes small due to some abnormality, a stable signal having almost equal amplitudes in the vertical synchronizing part and the horizontal synchronizing part can be synthesized.

Therefore, omission of the vertical synchronization signal can be prevented.
Furthermore, in the circuit shown in Figure 2, the diode 24 discharges only through the capacitor 23 and resistor 21, so there is almost no change in the slice level due to the average picture level, which was likely to occur when there were many whites in the conventional synchronous separation circuit. It is possible to prevent the mixing of video signals into the synchronization signal and the loss of vertical synchronization that tends to occur when there are many black areas. Furthermore, since the signal and the slice level are as stable as if they were ordered, the vertical synchronization signal does not drop out, the slice level can be made shallow, and it is possible to prevent the video signal from being mixed into the synchronization signal. Furthermore, the diode 24 lengthens the storage time of the transistor 63, and this storage time can be adjusted using the resistors 61 and 64. If the adjustment is made to prevent the transistor 63 from turning FF due to noise, a clean synchronization signal can be obtained. Furthermore, on the clamp circuit 20 side in FIG.
- A combing high-frequency filter may be configured, and by doing so, it is possible to remove fluctuations in the synchronization signal caused by fluctuations in the heron wave. Therefore, it is possible to provide an undisturbed screen. Note that the present invention is not limited to the above embodiments,
In short, any circuit may be used as long as it has circuit functions as shown in the blocks in FIG.

That is, for example, in order to deal with problems such as the output level of the video signal, a configuration as shown in FIG. 5 can be used. In the circuit shown in Fig. 5, the clamp circuit on the horizontal synchronization side cannot be configured with a Takagi filter, so the AG becomes weak outside the flat.
It is desirable to speed up the response of C. The synchronous separation circuit according to the present invention includes first and second clamp circuits, a low-pass filter inserted before the second clamp circuit, and a signal connected to the outputs of the first and second clamp circuits. a synthesis circuit;
Since the second clamp circuit is configured to include a synchronization signal detection circuit connected to the output of the signal synthesis circuit, a video signal with an emphasized vertical synchronization portion is provided to the second clamp circuit through a reduction filter. , in addition to the clamping of the horizontal synchronization section that is mainly performed by the first clamp circuit, the vertical synchronization section is clamped by the second clamp circuit, and the vertical synchronization section has an amplitude of 4 mm compared to the horizontal synchronization section. Even in the case of a video signal, a vertical synchronization signal can be stably obtained from a signal obtained by combining the separately clamped signals.

[Brief explanation of drawings]

Figure 1 is a waveform diagram for explaining the problems of the conventional example.
B is a video signal, C and D are each A. FIGS. 2, 3, and 4 show the synchronization signals obtained in B.
FIG. 2 is a circuit diagram of this embodiment, FIG. 3 is a block diagram showing the synchronization separation circuit of FIG. 2, and FIG. 4 is a waveform diagram. B, C, and D are points A and D in FIG. 2 or 3, respectively. Waveforms at B, C, and D are shown, and FIG. 5 is a circuit diagram of a modified example. 1...Antenna, 2...High frequency amplification circuit, 3...Mixing circuit, 4...Local oscillation circuit, 5...Intermediate frequency amplification circuit , 6...detection circuit, 7...video amplifier circuit, 8...picture tube, 9...synchronous separation circuit, 10...vertical deflection circuit, 11. ...Horizontal deflection circuit, 20, 40...
... Clamp circuit, 30 ... Low frequency filter circuit, 5
0...OR circuit, 60...Level detection circuit, 70...Differential circuit, 80...Integrator circuit. Many drawings Many drawings 2 scales A drawing Many drawings 9 drawings Many drawings

Claims (1)

[Claims] 1 a first clamp circuit to which a video signal is input; a low-pass filter to which the video signal is input; a second clamp circuit to which an output signal of the low-pass filter is supplied; A synchronization separation circuit comprising a signal synthesis circuit for synthesizing the output signals of the clamp circuits, and a synchronization signal detection circuit to which the output signals of the signal synthesis circuit are supplied and obtain horizontal and vertical synchronization signals.