JPS6115652Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical synchronization separation circuit used in television receivers and the like, and is designed to more reliably obtain particularly good vertical synchronization separation signals.

2. Description of the Related Art A conventional vertical synchronization separation circuit for television receivers as shown in FIG. 1 is generally used. In FIG. 1, numeral 1 indicates a video signal input terminal to which a composite video signal from a video detection circuit is supplied, and this video signal input terminal 1 is connected to a series circuit of a resistor 2 and a capacitor 3 for synchronous separation. is connected to the base of the pnp transistor 4. The base of this transistor 4 is connected via a bias setting resistor 5 to a power supply terminal +B to which a positive DC voltage is supplied, and the base of this transistor 4 is grounded via a bias setting resistor 6. Also, the emitter of this transistor 4 is connected to the power supply terminal +B, and the collector of this transistor 4 is connected to the resistor 7.
The collector of this transistor 4 is connected to the ground via a resistor 8a which constitutes an integrating circuit 8 for obtaining a vertical synchronizing signal, and the connection point between the collector of this transistor 4 and a resistor 7 is connected to the ground through a resistor 8a to obtain a synchronizing signal. is connected to a vertical synchronizing signal output terminal 9 that supplies a vertical synchronizing signal to a vertical oscillation circuit, and the connection point between this resistor 8a and the vertical synchronizing signal output terminal 9 is grounded via a capacitor 8b that constitutes this integrating circuit 8. .

In this case, the slice level for separating the synchronization signal from the composite video signal is determined by the resistance values of resistors 2, 5, and 6, the capacitance value of capacitor 3, and the internal impedance of the composite video signal supplied to video signal input terminal 1. However, considering that the depth of this slice level (level based on the peak value of the synchronization signal) is to provide a margin to eliminate so-called video in-sync, where noise in the image signal enters the synchronization signal, it is necessary to Considering the conflicting conditions of wanting to make the depth as shallow as possible in order to have as much level difference as possible from the signal, and wanting to make it as deep as possible considering the stability of synchronization (such as when the synchronization signal of the transmitted television signal is originally small). , will be determined appropriately. Another thing to consider when determining the slice level is that when the quality of the transmitted television signal is poor, or when you want to receive the television broadcast signal with a rod antenna, the output side of the video detection circuit as shown in Figure 2. The synchronization signal of the vertical synchronization part of the composite video signal obtained in the vertical synchronization pulse 1
0 and the equalization pulse 11 are often small compared to the level of other synchronization signals, that is, the horizontal synchronization pulse 12. In this case, this slice level is set to a relatively shallow level, for example,
If it is made shallower than V _S shown in the figure, there is a problem that vertical synchronization cannot be applied. Therefore, this slice level is V
For example, as shown in FIG. 2, it should be set to V _O as deep as possible than _S.

In this case, when a normal composite video signal is supplied to the video signal input terminal 1 and this vertical synchronization separation circuit operates ideally, the waveform obtained at the output side of the integrating circuit 8 is as shown by the broken line in FIG. 3A. , when the synchronization threshold level V _h is reached, a vertical synchronization signal as shown in FIG. 3D is supplied to the vertical oscillation circuit. However, when the slice level is set deeper than V _S in this way, the synthesized video signal is normal, but when a weak electric field is supplied, noise is superimposed on the synchronization signal, and in particular, the equalization pulse 11 is Since it exists every 1/2 horizontal period, there will be a lot of noise riding on the equalization pulse 11 of the signal obtained at the collector of the transistor 4, and at this time, the integration circuit 8 will accelerate the rise due to this noise, and the output side, that is, the output side. Terminal 9 has a peak 13a of the original vertical synchronizing signal as shown by curve 13 in FIG. 3A.
This equalization pulse 13b appears before the synchronization pulse 13b, and when the synchronization threshold level is V _h , the vertical synchronization signal obtained by this small peak 13b as shown in FIG. Not only is the synchronization slow and the phase of the image and the raster deviate, but since this small peak 13b is mainly made up of noise, there is an inconvenience that vertical jitter occurs depending on the amount of this noise.

In view of this point, the present invention is based on this slice level V _S
This is to prevent phase shift between the image and the raster and vertical jitter from occurring even when the depth is sufficiently deep.

An embodiment of the vertical synchronization separation circuit of the present invention will be described below with reference to FIG. In FIG. 4, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 4, the collector of transistor 4 constituting the synchronous separation circuit is connected to coil 10 and resistor 7.
This transistor 4 is grounded through a series circuit of
The connection point between the collector and the coil 10 is connected to the integrating circuit 8.
It is connected to the vertical synchronization signal output terminal 9 via. The rest of the structure is the same as in FIG.

In the present invention, the synchronous signal obtained at the collector of the transistor 4 constituting the synchronous separation circuit is passed through a series circuit of a coil 10 and a resistor 7, and an integrating circuit 8.
is supplied to. Therefore, in the present invention, when the slice level is set to V _O deeper than V _S in FIG. 2, a weak electric field composite video signal with noise superimposed on the synchronization signal is supplied to the video signal input terminal 1. Even when the frequency component forming the small peak 13b is lower than the frequency component forming the peak 13a of the vertical synchronization signal, the overall filter characteristics of the series circuit of the coil 10 and the resistor 7 and the integrating circuit 8 are vertically synchronized. Since the configuration is such that the component of the peak 13a of the signal is sufficiently passed through and the component of the small peak 13b is attenuated more than the component of the peak 13a, the output side of the integrating circuit 8 has a curve 13' shown in FIG. 3B. The peak 13b, which is smaller than the curve 13 in FIG. 3A, is attenuated. Note that the vertical synchronization signal peak 13a and small peak 13b
If C and D in Figure 3 are Fourier expanded, the frequency component difference between C and D in Figure 3 is as follows.
It is clear that it contains lower frequency components than a. Therefore, according to the present invention, even if the slice level V _O is sufficiently deep, there is no problem such as phase shift between the image and raster or vertical jitter.

Incidentally, in Figure 4, the resistance values of resistors 2, 5, 6, 7, and 8a are 390Ω, 39kΩ, and 390k, respectively.
Ω, 1.2kΩ and 3.9kΩ, the capacitance values of capacitors 3 and 8b are 4.7μF and 0.047μF, coil 1
When the zero inductance value is 1.5mH and the slice level V _O is approximately 50% of the synchronization signal of the video signal output from the video detection circuit, a phase shift between the image and the raster and vertical jitter occur. I was able to always get a good picture screen without any problems.

As described above, according to the present invention, even when the slice level is set sufficiently deep, it is possible to more reliably obtain a good vertical synchronization signal that does not cause a phase shift between the image and the raster and vertical jitter. There is profit.

Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and that various other configurations may be adopted without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an example of a conventional vertical synchronization separation circuit, FIGS. 2 and 3 are diagrams for explaining the present invention, and FIG. 4 shows an embodiment of the vertical synchronization separation circuit of the present invention. FIG. 1 is a video signal input terminal, 3 is a capacitor, 4 is a transistor, 5, 6 and 7 are resistors, 8 is an integrating circuit, 9 is a vertical synchronizing signal output terminal, and 10 is a coil.

Claims (1)

[Scope of utility model registration request] It has a sync separation circuit that separates a sync signal from a composite video signal, and connects the output signal of the sync separation circuit to a reference potential point via a series circuit of a coil and a resistor, and connects this output signal to a resistor and a capacitor. 1. A vertical synchronization separation circuit, characterized in that a vertical synchronization separation signal is obtained through an integrating circuit comprising: