JPS5939173A - Vertical deflector - Google Patents
Vertical deflectorInfo
- Publication number
- JPS5939173A JPS5939173A JP14966682A JP14966682A JPS5939173A JP S5939173 A JPS5939173 A JP S5939173A JP 14966682 A JP14966682 A JP 14966682A JP 14966682 A JP14966682 A JP 14966682A JP S5939173 A JPS5939173 A JP S5939173A
- Authority
- JP
- Japan
- Prior art keywords
- vertical
- signal
- synchronizing signal
- terminal
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はテレビジョン受像機における垂直偏向装置に関
するっ
従来例の構成とその問題点
たとえば、テレビジョン受像機において同期分離回路で
分離された垂直同期信号は垂直の同期をつかさどるため
に重要であるが、例えば外来雑音が同期成分に混入する
ことによって垂直、水平の同期信号が犯され同期が乱さ
れる。特に垂直同期信号に雑音（たとえば自動車雑音、
映像信号が混入する等）が混入すると、垂直の同期信号
が乱され、垂直の同期がかからず、垂直ローリングある
いは垂直ジッター等の現象が発生し、性能を著しく劣化
させる。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a vertical deflection device in a television receiver. is important for controlling vertical synchronization, but for example, when external noise mixes into the synchronization component, the vertical and horizontal synchronization signals are violated and the synchronization is disrupted. In particular, the vertical synchronization signal may be affected by noise (e.g. automobile noise,
If a video signal (such as a video signal is mixed) is mixed in, the vertical synchronization signal is disturbed, vertical synchronization is not achieved, and phenomena such as vertical rolling or vertical jitter occur, significantly degrading performance.
第１図に集積回路化された垂直同期回路Ａおよび垂直出
力回路Ｂの従来例を示す。第１図Ａに示すように同期分
離回路より得られた同期信号がトランジスタＱ１のベー
スに供給され、垂直同期信号は抵抗、Ｒ１，Ｒ２および
端子（ピン）１８に接続された外付コンデンサＣ１によ
って積分され、端子１８には図示するごとき垂直同期信
号が形成される。一方、第１図Ｂに示す垂直出力回路構
成において、端子（ピン）１６には、トランジスタＱ２
．Ｑ３でＮＰＮダーリントン回路を構成し、トランジス
タＱ４．Ｑ６．Ｑ６でＰＮＰダーリントン回路を構成し
てなる垂直出力回路が接続され、したがって端子１６に
は図示するように垂直出力波形が現われ、偏向コイル１
に供給される。FIG. 1 shows a conventional example of a vertical synchronization circuit A and a vertical output circuit B which are integrated circuits. As shown in FIG. 1A, the synchronization signal obtained from the synchronization separation circuit is supplied to the base of transistor Q1, and the vertical synchronization signal is generated by resistor R1, R2 and an external capacitor C1 connected to terminal (pin) 18. The signal is integrated, and a vertical synchronizing signal as shown is formed at the terminal 18. On the other hand, in the vertical output circuit configuration shown in FIG. 1B, the terminal (pin) 16 has a transistor Q2.
．． Q3 constitutes an NPN Darlington circuit, and transistors Q4. Q6. A vertical output circuit configured as a PNP Darlington circuit is connected to Q6, so a vertical output waveform appears at terminal 16 as shown in the figure, and deflection coil 1
is supplied to
このような回路構成において、上記したように垂直同期
信号に雑音が混入すると、垂直の同期が乱される問題が
生じる。In such a circuit configuration, if noise is mixed into the vertical synchronization signal as described above, a problem arises in that vertical synchronization is disturbed.
発明の目的
本発明は上記したような雑音による垂直同期の乱れを軽
減し、より一層安定した垂直同期信号を作り出すことの
できる回路を提供することを目的とする。OBJECTS OF THE INVENTION It is an object of the present invention to provide a circuit that can reduce disturbances in vertical synchronization due to noise as described above and can produce a more stable vertical synchronization signal.
発明の構成
本発明は、垂直出力波形の同期信号成分をコンデンサを
介して垂直同期信号に重畳させることによ−て、垂直同
期信号の立−トがりを急峻にし、またパルスｒｊＪを鋭
利にし、かつ垂直同期信号自体の振幅を大きくして安定
した動作を得るものであるっ実施例の説明
以下本発明の実施例を第２図を用いて説明する。Structure of the Invention The present invention makes the rising edge of the vertical synchronizing signal steeper and the pulse rjJ sharper by superimposing the synchronizing signal component of the vertical output waveform on the vertical synchronizing signal via a capacitor. In addition, the amplitude of the vertical synchronizing signal itself is increased to obtain stable operation.Description of an EmbodimentAn embodiment of the present invention will be described below with reference to FIG.
第２図において、２は垂直発振回路、３は積分回路、４
は垂直増幅回路で、これらは図示していない他の回路と
ともに集積回路化されており、端子１８には垂直同期信
号が現われ、端子１６には垂直偏向出力信号が現われる
。本発明では、図示するように端子１８と端子１５とを
コンデンサ６で接続して、端子１５に得られる垂直偏向
出力波形の同期信号成分を上記コンデンサ６を介して端
子１８に得られる垂直同期信号に重畳させようとするも
のである。In Figure 2, 2 is a vertical oscillation circuit, 3 is an integration circuit, and 4 is a vertical oscillation circuit.
1 is a vertical amplifier circuit, which is integrated with other circuits (not shown), a vertical synchronizing signal appears at a terminal 18, and a vertical deflection output signal appears at a terminal 16. In the present invention, as shown in the figure, the terminal 18 and the terminal 15 are connected by a capacitor 6, and the synchronizing signal component of the vertical deflection output waveform obtained at the terminal 15 is passed through the capacitor 6 to the vertical synchronizing signal obtained at the terminal 18. It is intended to be superimposed on the
垂直同期信号ＶＳに雑音Ｎが混入した場合、第３図Ａ、
Ｈに示すように垂直同期信号が乱され、垂直同期信号の
それぞれのピーク点でｉｌｊｌ問直がかかろうとするだ
め垂直同期が不安定となる。したがって画像の垂直がが
たつく現象、ずなわち垂直ジッタリングが発生したり、
捷たは垂１（１の同期がとれず垂直が流れる現象、すな
わち垂直ローリングが発生するが、第２図の構成によれ
は、垂直出力波形の同期信号成分をコンデンサ６を介し
て垂直同期信号に重畳することによって垂直同期信号の
立上がりを急峻にし、まだパルス巾を鋭利にし、かつ垂
直同期信号自体の振幅を大きくすることにより、垂直同
期信号に雑音が混入しても、上記した利点をもつ垂直同
期信号によ−て垂直同期が一点で同期し画像が安定する
ようになる。When noise N is mixed into the vertical synchronization signal VS, Fig. 3A,
As shown in H, the vertical synchronization signal is disturbed and the vertical synchronization becomes unstable as iljl correction is attempted at each peak point of the vertical synchronization signal. Therefore, a phenomenon in which the vertical part of the image becomes jittery, that is, vertical jittering, may occur.
Vertical rolling occurs, which is a phenomenon in which vertical signals are not synchronized due to vertical rolling. However, with the configuration shown in FIG. By superimposing the vertical synchronization signal on the vertical synchronization signal, the rise of the vertical synchronization signal is made steeper, the pulse width is made sharper, and the amplitude of the vertical synchronization signal itself is increased, so that even if noise is mixed into the vertical synchronization signal, the above advantages can be achieved. The vertical synchronization signal synchronizes the vertical synchronization at one point, making the image stable.
第４図はこの作用を説明するだめの波形図で、Ａは垂直
同期信号、Ｂは垂直偏向出力信号、Ｃが垂直同期信号Ａ
に垂直偏向出力Ｂの同期信号成分を重畳したときの垂直
同期信号である。Figure 4 is a waveform diagram to explain this effect, where A is the vertical synchronization signal, B is the vertical deflection output signal, and C is the vertical synchronization signal A.
This is the vertical synchronizing signal obtained by superimposing the synchronizing signal component of the vertical deflection output B on the vertical deflection output B.
発明の詳細
な説明したように本発明によれば、垂直偏向出力信号の
同期信号成分をコンデンサを介して垂直同期信号に重畳
させることにより、雑音が混入しても安定した垂直同期
動作が行われ、常に安定した画像を得ることができる。DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by superimposing the synchronizing signal component of the vertical deflection output signal on the vertical synchronizing signal via a capacitor, stable vertical synchronizing operation can be performed even when noise is mixed. , you can always get stable images.
第１図Ａ、Ｂは従来の垂直偏向装置の回路図、第２図は
本発明の−★施例における垂直偏向装置の回路図、第３
図Ａ、Ｂおよび第４図Ａ、 Ｂ 、Ｃは本発明の作用効
果を説明するだめの波形図である０
１・・・・・・偏向コイル、２・・・・・・垂直発振回
路、３・・・・・・積分回路、４・・・・・・垂直増幅
回路、５・・・・・・コンデンサ、Ｒ１，Ｒ２，Ｃ１・
・・・−・積分回路を構成する抵抗。
コンデンサ。
Ｎ埋入の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
１２図
第 ３ 図
ム
第４１１Ｉ1A and 1B are circuit diagrams of a conventional vertical deflection device, FIG. 2 is a circuit diagram of a vertical deflection device in a -★ embodiment of the present invention, and 3.
Figures A, B and Figures 4A, B, and C are waveform diagrams for explaining the effects of the present invention.0 1...deflection coil, 2...vertical oscillation circuit, 3...Integrator circuit, 4...Vertical amplifier circuit, 5...Capacitor, R1, R2, C1.
・・・−・Resistance that makes up the integration circuit. capacitor. Name with N embedded Patent attorney Toshio Nakao and 1 other person 1st
Figure 12 Figure 3 Figure 411I
Claims (1)
垂直同期信号に重畳させるようにした垂直偏向装置。A vertical deflection device in which a synchronization signal component of a vertical deflection output signal is superimposed on a vertical synchronization signal via a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14966682A JPS5939173A (en) | 1982-08-27 | 1982-08-27 | Vertical deflector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14966682A JPS5939173A (en) | 1982-08-27 | 1982-08-27 | Vertical deflector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5939173A true JPS5939173A (en) | 1984-03-03 |
Family
ID=15480184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14966682A Pending JPS5939173A (en) | 1982-08-27 | 1982-08-27 | Vertical deflector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5939173A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8715585B2 (en) | 2008-06-16 | 2014-05-06 | Isel Co., Ltd. | Mixing unit, mixing device, agitation impeller, pump mixer, mixing system and reaction device |
| WO2018070630A1 (en) | 2017-03-20 | 2018-04-19 | 주식회사 지세븐홀딩스 | Fluid stirring-based liquefaction promoting apparatus installed on pipe path of heat pump system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53144216A (en) * | 1977-05-23 | 1978-12-15 | Hitachi Ltd | Vertical synchronous signal generator circuit |
| JPS5437421A (en) * | 1977-08-29 | 1979-03-19 | Hitachi Ltd | Vertical synchronous circuit |
-
1982
- 1982-08-27 JP JP14966682A patent/JPS5939173A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53144216A (en) * | 1977-05-23 | 1978-12-15 | Hitachi Ltd | Vertical synchronous signal generator circuit |
| JPS5437421A (en) * | 1977-08-29 | 1979-03-19 | Hitachi Ltd | Vertical synchronous circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8715585B2 (en) | 2008-06-16 | 2014-05-06 | Isel Co., Ltd. | Mixing unit, mixing device, agitation impeller, pump mixer, mixing system and reaction device |
| WO2018070630A1 (en) | 2017-03-20 | 2018-04-19 | 주식회사 지세븐홀딩스 | Fluid stirring-based liquefaction promoting apparatus installed on pipe path of heat pump system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6350911B2 (en) | ||
| JPS5939173A (en) | Vertical deflector | |
| KR930011507B1 (en) | Tv-receiver having gate pulse generator | |
| JP2517603Y2 (en) | Vertical contour correction circuit for video signals | |
| JPH0317505Y2 (en) | ||
| KR930007502Y1 (en) | Horizontal-sync signal generating apparatus of camcoder | |
| KR960008054B1 (en) | Synchronization signal expansion circuit for monitor | |
| JP3221794B2 (en) | Line ident circuit for chroma signal processing | |
| JPS5942780Y2 (en) | transistor circuit device | |
| JPH0767144B2 (en) | Image signal synchronization circuit | |
| JPH056145A (en) | Blanking control device | |
| KR940006304Y1 (en) | Noise preventing circuit of vcr | |
| JPH0269077A (en) | False synchronizing pulse generator | |
| JPS592425B2 (en) | vertical deflection device | |
| JP3385821B2 (en) | Horizontal blanking generation circuit | |
| JP2841392B2 (en) | Video signal circuit | |
| JPS6115652Y2 (en) | ||
| JPH0429478A (en) | Video signal masking device | |
| JPS60259077A (en) | Signal switching device | |
| JPH0461566A (en) | Contour correction circuit for video signal | |
| JPS58178669A (en) | Synchronization separating device | |
| JPS6323716B2 (en) | ||
| JPS63146668A (en) | Picture quality adjusting device | |
| JPS602824B2 (en) | Synchronous separation circuit | |
| JPS6211834B2 (en) |