JPS6129583B2 - - Google Patents

Info

Publication number
JPS6129583B2
JPS6129583B2 JP54117509A JP11750979A JPS6129583B2 JP S6129583 B2 JPS6129583 B2 JP S6129583B2 JP 54117509 A JP54117509 A JP 54117509A JP 11750979 A JP11750979 A JP 11750979A JP S6129583 B2 JPS6129583 B2 JP S6129583B2
Authority
JP
Japan
Prior art keywords
transistor
output
electrode
noise
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54117509A
Other languages
Japanese (ja)
Other versions
JPS5640368A (en
Inventor
Kenji Terasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP11750979A priority Critical patent/JPS5640368A/en
Publication of JPS5640368A publication Critical patent/JPS5640368A/en
Publication of JPS6129583B2 publication Critical patent/JPS6129583B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising
    • H04N5/12Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/123Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal directly commands a frequency generator

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Description

【発明の詳細な説明】 本発明は周波数シンセサイザ方式等の自動探局
機能を備えるテレビジヨン受像機に使用される水
平同期信号検出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a horizontal synchronization signal detection circuit used in a television receiver having an automatic station searching function such as a frequency synthesizer system.

前述の如きテレビジヨン受像機ではチユーナで
受信された信号がテレビジヨン信号であるか否か
の判別に水平同期信号を利用しているものがあ
る。その場合、受像機内の同期分離回路から導出
される水平同期信号を検出すればよい訳である
が、通常の同期分離回路では所謂振幅分離動作に
よる比較的簡単な回路が使用されているため、テ
レビジヨン信号を受信していないときでも上記同
期分離回路からは水平同期信号と略同程度のレベ
ルのノイズが発生しており、上記同期分離回路の
出力を前記判別に利用することは困難であつた。
そのため、このような点に留意してノイズの検出
をおさえ、水平同期信号だけを検出できる水平同
期信号検出回路を本件出願人の出願に係る実願昭
53―154203号において提案済であるが、この先技
術は第1図に示すようにNPN型の第1トランジ
スタTR1のエミツタにダイオードD1とコンデンサ
C1を直列に接続し、このダイオードD1とコンデ
ンサC1の接続中点a及び第1トランジスタTR1
ベースに抵抗R1,R2をそれぞれ介して入力端子
1からの複合映像信号を印加し、第1トランジス
タTR1のコレクタを抵抗R3を介して電源電圧(+
B)に接続していることにより、そのコレクタに
導出される負極性パルスをPNP型の第2トランジ
スタTR2のベースに該第2トランジスタのベー
ス・エミツタ逆耐防止用ダイオードD2を介して
印加し、そのエミツタに端子2からのフライバツ
クパルスを抵抗R4,R5で適当な大きさに分圧し
て印加し、コレクタを抵抗R6を介してアースに
接続することにより該コレクタから水平同期信号
に同期したパルスを得るようにしたものであつ
て、前記コンデンサC1と抵抗R1で決まる時定数
を水平周波数(15.75KHz)に比べて充分大きく
選定しているのでa点の電位は第2図破線のよう
になり、上記第1のトランジスタTR1はそベース
電位が上記a点の電位にダイオードD1及びトラ
ンジスタTR1のベース・エミツタ間の各立上り電
圧を加えた値よりも大きくなる複合映像信号〔第
2図イ〕中の水平同期信号に対してのみ導通し、
従つて第1トランジスタTR1のコレクタには第2
図ロに示す負極性パルスが得られる。今、前記パ
ルスロとフライパツクパルスハが第2図の関係に
なるように前記抵抗R4,R5の分圧比を選んでお
くと、第2トランジスタTR2のコレクタとその負
荷抵抗R6の接続点b、即ち端子3からは第2図
ニのように前記複合映像信号イ中の水平同期信号
に同期したパルスが得られる。そこで、このパル
スニを積分回路等によつて直流電圧に変換すれば
選局装置の探局動作の停止用信号として使用する
ことができる。そして、端子1にノイズが到来し
た場合に、そのようなノイズの繰り返し周波数数
は水平周波数に対して充分低いと考えられるか
ら、この場合にa点に発生する電位とそのノイズ
のピーク電位の差はダイオードD1と第1トラン
ジスタTR1のベース・エミツタ間の各立上り電圧
の和(約1.2V)を越えるほど大きくならず、従
つてそのようなノイズによつて第1トランジスタ
TR1のコレクタにパルスが現われることはなく、
たとえそのようなパルスが現われたとしても第2
図ロ,ハ間の電位差△Vが確実に動作する範囲
で、できるだけ小さくなるようにパルスハを選ん
でおくことにより第2トランジスタTR2のコレク
タに前記ノイズによるパルスが発生する可能性は
少なくなり、ノイズが水平同期信号として検出さ
れるという誤動作は皆無に近くなる。
Some of the above-mentioned television receivers utilize a horizontal synchronization signal to determine whether a signal received by a tuner is a television signal. In that case, it is sufficient to detect the horizontal synchronization signal derived from the sync separation circuit inside the receiver, but since the normal sync separation circuit uses a relatively simple circuit with so-called amplitude separation operation, Even when the horizontal synchronization signal is not being received, the sync separation circuit generates noise at a level approximately the same as that of the horizontal sync signal, making it difficult to use the output of the sync separation circuit for the determination. .
Therefore, with these points in mind, the present applicant's application for a horizontal synchronization signal detection circuit that suppresses noise detection and can detect only horizontal synchronization signals has been proposed.
Although it was proposed in No. 53-154203, the future technology is to add a diode D1 and a capacitor to the emitter of the first NPN transistor TR1 , as shown in Figure 1.
C 1 is connected in series, and a composite video signal from input terminal 1 is applied to the connection midpoint a of this diode D 1 and capacitor C 1 and the base of the first transistor TR 1 via resistors R 1 and R 2 , respectively. The collector of the first transistor TR 1 is connected to the power supply voltage (+
B), the negative pulse derived from the collector is applied to the base of the PNP type second transistor TR 2 via the base-emitter reverse protection diode D 2 of the second transistor. Then, by applying the flyback pulse from terminal 2 to the emitter after dividing it into an appropriate voltage using resistors R 4 and R 5 , and connecting the collector to ground via resistor R 6 , horizontal synchronization is obtained from the collector. It is designed to obtain pulses synchronized with the signal, and the time constant determined by the capacitor C1 and resistor R1 is selected to be sufficiently large compared to the horizontal frequency (15.75KHz), so the potential at point a is As shown by the broken line in Figure 2, the base potential of the first transistor TR1 becomes greater than the sum of the potential at point a and the respective rising voltages between the base and emitter of the diode D1 and the transistor TR1 . Conductive only for the horizontal synchronizing signal in the composite video signal [Figure 2 A],
Therefore, the collector of the first transistor TR1 has a second
The negative polarity pulse shown in Figure B is obtained. Now, if the voltage dividing ratio of the resistors R 4 and R 5 is selected so that the pulse LO and flypack pulse HA have the relationship shown in FIG. 2, the connection between the collector of the second transistor TR 2 and its load resistor R 6 is From point b, that is, terminal 3, a pulse synchronized with the horizontal synchronizing signal in the composite video signal A is obtained as shown in FIG. 2D. Therefore, if this pulse 2 is converted into a DC voltage using an integrating circuit or the like, it can be used as a signal for stopping the station searching operation of the station selection device. When noise arrives at terminal 1, the repetition frequency of such noise is considered to be sufficiently low compared to the horizontal frequency, so in this case, the difference between the potential generated at point a and the peak potential of the noise is is not large enough to exceed the sum of the respective rising voltages (approximately 1.2 V) between the diode D 1 and the base-emitter of the first transistor TR 1 , and therefore, such noise will cause the first transistor to
No pulse appears at the collector of TR 1 ,
Even if such a pulse appears, the second
By selecting the pulse C so that the potential difference △V between B and C in the figure is as small as possible within the range that ensures reliable operation, the possibility that a pulse due to the noise will be generated at the collector of the second transistor TR2 is reduced. Malfunctions in which noise is detected as a horizontal synchronization signal are almost eliminated.

ところで、第1図に示す先行技術の回路では通
常のテレビ信号の場合は問題ないが画面全体が黒
く均一な場合は複合映像信号の波形は第3図のA
のようになつて通常時の場合に比し、その積分出
力のレベルBが上がるので水平同期信号が小さい
と、ダイオードD1の電圧降下を考慮した場合、
水平同期信号部分において第1トランジスタTR1
のコレクタにパルスが得られず、本来の水平同期
信号の検出ができないという欠点を生じる。尚、
画面が黒く均一な場合は実際の画面では少ない
が、このような稀有な場合についても適切な考慮
を払うべきである。工場における調整工程で格子
状パターンを映出する場合にも画面が黒く均一な
状態として把握される。
By the way, with the prior art circuit shown in Figure 1, there is no problem with normal TV signals, but when the entire screen is black and uniform, the waveform of the composite video signal is A in Figure 3.
As a result, the level B of the integrated output increases compared to the normal case, so if the horizontal synchronization signal is small, and considering the voltage drop of diode D1 ,
In the horizontal synchronization signal part, the first transistor TR 1
This results in the disadvantage that a pulse cannot be obtained at the collector of the sensor, and the original horizontal synchronization signal cannot be detected. still,
Although there are few cases where the screen is black and uniform in real life, appropriate consideration should be given to such rare cases. Even when a grid pattern is projected during an adjustment process at a factory, the screen is perceived as being black and uniform.

このため、例えばダイオードD1を削除して水
平同期信号の検出レベルを下げることが考えられ
るが、同時にノイズも検出してしまいノイズによ
る誤動作が発生してしまう。
For this reason, it is conceivable to lower the detection level of the horizontal synchronizing signal by removing the diode D1 , for example, but noise will also be detected at the same time, resulting in malfunctions due to noise.

本発明は上述の如き欠点が生じないようになす
と共にノイズをほとんど検出しないように工夫し
た水平同期信号検出回路を提案するものである。
The present invention proposes a horizontal synchronizing signal detection circuit that is designed to avoid the above-mentioned drawbacks and to detect almost no noise.

本発明を実施した第4図において、第1図と同
一部分については同一の記号を示してあるが、こ
の第4図の回路が第1図の回路と相違する点は第
1トランジスタTR1のエミツタとコンデンサC1
の間のダイオードD1が取り去られている点と、
第1トランジスタTR1のコレクタ出力を逆耐防止
用ダイオーードD3を介して第1差動対トランジ
スタTR3のベースに印加し、第2トランジスタ
TR2のコレクタ出力を第2差動対トランジスタ
TR4のベースに印加し、第1差動対トランジスタ
TR3のコレクタを抵抗R8を介してアースに接続す
ることにより該第1差動対トランジスタTR3のコ
レクタに得られる出力を水平同期信号検出出力と
し端子3に得るようにしている点である。
In FIG. 4, in which the present invention is implemented, the same parts as in FIG. 1 are indicated by the same symbols, but the difference between the circuit in FIG. 4 and the circuit in FIG. The diode D 1 between the emitter and the capacitor C 1 is removed, and
The collector output of the first transistor TR 1 is applied to the base of the first differential pair transistor TR 3 via the reverse protection prevention diode D 3, and the collector output of the first transistor TR 1 is applied to the base of the first differential pair transistor TR 3 .
The collector output of TR 2 is connected to the second differential pair transistor.
Applied to the base of TR 4 , the first differential pair transistor
By connecting the collector of TR 3 to the ground via resistor R 8 , the output obtained at the collector of the first differential pair transistor TR 3 is used as a horizontal synchronization signal detection output and is obtained at terminal 3. .

このように本発明では第1トランジスタTR1
エミツタに抵抗R1とコンデンサC1よりなる大時
定数の積分回路の出力を直接印加しダイオード
D1を省略しているので入力される信号が第1ト
ランジスタTR1のコレクタに導出され易くなり、
従つて画面が黒く均一な場合であつても水平同期
信号部分で出力が得られないことはなくなる。そ
して、このように信号が得られ易くなつた結果、
ノイズも第1トランジスタTR1のコレクタ出力に
ついて第5図に示す如く導出され易くなるという
不都合が生じるが、これはこの出力〔第5図〕
が、該出力をフライバツクパルスにより第2トラ
ンジスタTR2でゲートして得られる出力〔第6
図〕とにより差動増幅器において、組合せら
れ、その特別の場合、即ち第1差動対トランジス
タTR3のベース力の方が第2差動対トランジスタ
TR4のベース入力より小さい場合にのみ出力端子
3にパルスが得られるようにすることにより、ノ
イズのかなりのものが抑圧され、出力として現わ
れるノイズはわずかとなるので、これを積分して
もわずかな直流電圧となるだけで本来の水平同期
信号に同期するパルスを積分して直流化した場合
との差は顕著になるからノイズによる誤動作は生
じない。尚、出力端子3側に導出されるノイズは
第6図のノイズのうち、正極性で且つ第1差動対
トランジスタTR3のベースに入力されるノイズが
負極性の場合であるが、前記第1トランジスタ
TR1のコレクタ出力が第1差動対トランジスタ
TR3のベースに印加される径路と前記出力が第2
差動対トランジスタTR4のベースに印加される径
路とを比較すると後者の径路には第2トランジス
タTR2が挿入されているため、信号の遅れが発生
し、この遅れにより一方の高周波ノイズの位相が
ずれることにより、前述の様な場合が発生する確
率は大巾に減少する。よつて、出力端子3側に導
出されるノイズは極めて少なくなる。一方、テレ
ビジヨン信号受信の場合には水平同期信号を検出
するに当つて前記伝達系路の差異による時間の遅
れは無視することができ第7図に示すようにTR1
の出力EがTR2の出力Fより小さい部分で第8図
に示すように水平同期信号に同期したパルスが得
られる。
In this way, in the present invention, the output of the integrating circuit with a large time constant consisting of the resistor R1 and the capacitor C1 is directly applied to the emitter of the first transistor TR1 , and the diode
Since D1 is omitted, the input signal is easily led to the collector of the first transistor TR1 ,
Therefore, even if the screen is black and uniform, there is no possibility that no output will be obtained in the horizontal synchronizing signal portion. And as a result of it becoming easier to obtain signals in this way,
The problem arises that noise is also easily derived from the collector output of the first transistor TR1 as shown in FIG. 5;
However, the output obtained by gating this output with the second transistor TR2 by a flyback pulse [6th]
In the special case, that is, the base power of the first differential pair transistor TR3 is higher than that of the second differential pair transistor TR3 .
By ensuring that a pulse is obtained at output terminal 3 only when it is smaller than the base input of TR 4 , a considerable amount of noise is suppressed, and the noise that appears as an output is small, so even if this is integrated, it is only a small amount. Since the difference from the case where pulses synchronized with the original horizontal synchronizing signal are integrated and converted to DC voltage is significant, malfunctions due to noise will not occur. Incidentally, among the noises shown in FIG. 6, the noise derived to the output terminal 3 side is of positive polarity and the noise input to the base of the first differential pair transistor TR3 is of negative polarity. 1 transistor
The collector output of TR 1 is the first differential pair transistor
The path applied to the base of TR 3 and the output
Comparing the path applied to the base of the differential pair transistor TR 4 , since the second transistor TR 2 is inserted in the latter path, a signal delay occurs, and this delay causes the phase of high-frequency noise on one side to change. By shifting, the probability that the above-mentioned situation will occur will be greatly reduced. Therefore, the noise led to the output terminal 3 side is extremely reduced. On the other hand, in the case of television signal reception, the time delay due to the difference in the transmission path can be ignored when detecting the horizontal synchronizing signal, and as shown in FIG.
In the portion where the output E of TR 2 is smaller than the output F of TR 2, a pulse synchronized with the horizontal synchronizing signal is obtained as shown in FIG.

以上の通り、本発明はトランジスタの第1電極
に複合映像信号を加えると共に、水平同期より充
分大きな時定数の積分回路に前記複合映像信号を
加えることにより生じる出力が第2電極にかかる
ように接続し、前記トランジスタの第3電極に生
じる出力と、、この出力をフライバツクパルスで
ゲートして生じる出力とも逆位相関係になし、両
者を差動対トランジスタの各第1電極に印加する
ことにより、両者の伝達系路の差異による時間の
ずれによつて高周波のノイズ成分は大巾減少され
ると共に水平同期信号の検出は確実に行なえるの
でノイズによる誤動作を回避できると共に、いか
なる画面のときにも水平同期信号を確実に検出で
きるという効果があり、自動探局機能を有するテ
レビジヨン受像機において探局停止信号を与える
回路として極めて有用である。
As described above, the present invention applies a composite video signal to the first electrode of a transistor, and connects the transistor so that the output generated by applying the composite video signal to an integrating circuit with a time constant sufficiently larger than that of horizontal synchronization is applied to the second electrode. However, by making the output generated at the third electrode of the transistor and the output generated by gating this output with a flyback pulse in an opposite phase relationship, and applying both to each first electrode of the differential pair transistor, Due to the time difference caused by the difference in the transmission paths between the two, high-frequency noise components are greatly reduced, and the horizontal synchronization signal can be detected reliably, making it possible to avoid malfunctions due to noise, and to ensure that no noise is displayed on any screen. This circuit has the effect of reliably detecting the horizontal synchronization signal, and is extremely useful as a circuit for providing a search stop signal in a television receiver having an automatic station search function.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は先行技術を示す回路図であり、第2図
及び第3図はその説明図である。第4図は本発明
を実施した水平同期信号検出回路を示す回路図で
あり、第5図、第6図、第7図及び第8図はその
説明図である。 TR1…第1トランジスタ、C1,R1…積分回路
を形成するコンデンサ及び抵抗、…差動増幅
器。
FIG. 1 is a circuit diagram showing the prior art, and FIGS. 2 and 3 are explanatory diagrams thereof. FIG. 4 is a circuit diagram showing a horizontal synchronizing signal detection circuit embodying the present invention, and FIGS. 5, 6, 7, and 8 are explanatory diagrams thereof. TR 1 ...first transistor, C1 , R1 ...capacitor and resistor forming an integrating circuit, 4 ...differential amplifier.

Claims (1)

【特許請求の範囲】[Claims] 1 第1トランジスタの第1電極に複合映像信号
を加えると共に、水平周期より充分大きな時定数
の積分回路に前記複合映像信号を加えることによ
り生じる出力が第2電極にかかるように接続し、
前記第1トランジスタの第3電極に生じる出力
と、この出力を2トランジスタの第1電極に印加
すると共に第2電極にフライバツクパルスを印加
することにより第3電極に生じるフライバツクパ
ルス期間ゲートされ且つ位相反転された出力とを
夫々、差動対トランジスタの各第1電極に印加
し、該差動対トランジスタの一方のトランジスタ
の第3電極に生じる出力を水平同期信号検出出力
とすることを特徴とする水平同期信号検出回路。
1. A composite video signal is applied to the first electrode of the first transistor, and the output generated by applying the composite video signal to an integrating circuit with a time constant sufficiently larger than the horizontal period is connected to the second electrode,
an output produced at the third electrode of the first transistor and a period of a flyback pulse produced at the third electrode by applying this output to the first electrode of the two transistors and a flyback pulse to the second electrode; The phase-inverted outputs are respectively applied to the first electrodes of the differential pair transistors, and the output generated at the third electrode of one of the differential pair transistors is used as the horizontal synchronization signal detection output. Horizontal sync signal detection circuit.
JP11750979A 1979-09-12 1979-09-12 Horizontal synchronizing signal detecting circuit Granted JPS5640368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11750979A JPS5640368A (en) 1979-09-12 1979-09-12 Horizontal synchronizing signal detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11750979A JPS5640368A (en) 1979-09-12 1979-09-12 Horizontal synchronizing signal detecting circuit

Publications (2)

Publication Number Publication Date
JPS5640368A JPS5640368A (en) 1981-04-16
JPS6129583B2 true JPS6129583B2 (en) 1986-07-08

Family

ID=14713510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11750979A Granted JPS5640368A (en) 1979-09-12 1979-09-12 Horizontal synchronizing signal detecting circuit

Country Status (1)

Country Link
JP (1) JPS5640368A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11112163B2 (en) 2019-01-18 2021-09-07 Whirlpool Corporation Ice-making compartment for an appliance

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4918419A (en) * 1972-06-12 1974-02-18
JPS4946325A (en) * 1972-09-05 1974-05-02

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423217Y2 (en) * 1973-10-01 1979-08-10

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4918419A (en) * 1972-06-12 1974-02-18
JPS4946325A (en) * 1972-09-05 1974-05-02

Also Published As

Publication number Publication date
JPS5640368A (en) 1981-04-16

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