JPS5936062Y2 - Synchronous signal separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal separation circuit for a television receiver, and particularly to a circuit improved so as to be able to perform synchronization separation without any trouble even in the case of a special received electric field such as a ghost.

When the received electric field is normal, the input signal of the synchronization signal separation circuit of the television receiver, that is, the composite video signal derived by video detection, has a constant synchronization signal tip level as shown in Figure 1a, but due to disturbances, In the case of a special received electric field such as a ghost, there is a possibility that the tip level of the vertical synchronizing signal will undulate as shown in FIG. 1, making it impossible to separate the vertical synchronizing signal.

Therefore, it has been considered to configure a synchronization signal separation circuit as shown in FIG. 2 so that reliable synchronization separation can be achieved even if the above-mentioned undulations occur in the composite video signal.

That is, the composite synchronization signal (see Figure 3) obtained by separating the composite video signal input (see Figure 3C) by the first separation circuit 11 for composite synchronization signal amplitude separation is branched, and one of the signals is separated from the horizontal AF.
C circuit, and the other is led to the synchronous inverting amplifier circuit 12.

On the other hand, the composite video signal input is guided to the integrating circuit 13 to remove the horizontal synchronizing signal component and integrate the vertical synchronizing signal component (Fig. 3C
) and the second separation circuit 1 for vertical synchronization signal amplitude separation.
4, and the vertical synchronization signal obtained by separating here (Fig. 3C)
reference) is led to the synchronous inverting amplifier circuit 12, where it is superimposed on the output signal (composite synchronous signal) of the first separation circuit 11, synthesized, and inverted and amplified.

This amplified output (see FIG. 3C) is then guided to a vertical synchronization signal frequency separation (integration) circuit 15 to separate the vertical synchronization signal, and this output is supplied to the vertical oscillation circuit.

According to the synchronization signal separation circuit as described above, even if the vertical synchronization signal period of the composite video signal input is undulated as shown in FIG. The amplitude is reliably separated by the separating circuit 14 of 2, but due to the integration operation and phase shift by the integrating circuit 13, the separated vertical synchronizing signal (Fig. 3 d) has its trailing edge slightly widened and the signal within the signal is Cutting pulse is missing.

However, this signal is synthesized with the output signal of the first separation circuit 11, in which the vertical synchronization signal component may be omitted due to the influence of ghosts, etc., and then frequency-separated to ensure that the vertical synchronization signal is separated. It becomes like this.

In addition, as mentioned above, the vertical synchronizing signal (Fig. 3 d) whose signal width is wider than the normal width 5 and the notch pulse in the signal is missing is not supplied to the horizontal AFC circuit, and the horizontal AFC circuit is supplied with the first signal. Since only the output signal of the separation circuit 11 is supplied, the operation of the horizontal AFC circuit is not hindered.

If the vertical synchronization signal with the widened signal width as described above is supplied to the horizontal AFC circuit, the phase detection circuit output of the horizontal AFC circuit, that is, the AFC Ripples occur in the voltage, causing problems such as unstable synchronization.

By the way, with respect to the vertical synchronization signal included in the output composite synchronization signal of the first separation circuit 11, the output vertical synchronization signal of the second separation circuit 14 is delayed in phase due to the phase shift of the integration circuit 13. If the signals were simply superimposed and synthesized,
There is a level difference between the overlapping portion and the non-overlapping portion within the vertical synchronization signal period (see Fig. 3e).

This causes the phase of the frequency-separated vertical synchronization signal to become unstable, and there is a risk that the synchronization performance will deteriorate, such as deterioration of interlace on the image receiving screen.

The present invention was developed to eliminate the above-mentioned drawbacks, and in a synchronous inverting amplifier circuit, when the composite synchronous signal is below a certain level and when the amplitude separated vertical synchronous signal is input, the inverting amplifying transistor is cut off. It is an object of the present invention to provide a synchronization signal separation circuit that can improve synchronization performance without causing a level difference in the superimposed output of a synchronization signal and the vertical synchronization signal, and without interfering with other performances.

An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 4, 40 is an input terminal to which a composite video signal is applied, 41 is a first separating circuit for separating composite synchronizing signal amplitude, 42 is an integrating circuit, and 43 is a second separating circuit for separating vertical synchronizing signal amplitude. A circuit 44 is a synchronous inversion amplifier circuit, the output signal of this synchronous inversion amplifier circuit 44 is supplied to a vertical synchronization signal frequency separation circuit 45, and the output signal of the first separation circuit 41 is supplied to a horizontal AFC circuit. .

That is, the block configuration of FIG. 4 is the same as the block configuration of FIG. 2 described above.

In the first separation circuit 41, a time constant circuit 50 consisting of a resistor 51 and a capacitor 52 is inserted in series with the signal input line, and the discharge resistor 5 is connected to the output end of the time constant circuit 50.
Power supply V through 3.

It is connected to the base of the amplitude separating transistor 54.

The emitter of this transistor 54 is grounded, and the collector is connected to a power source VC via a collector load resistor 56 after connecting one diode 55 in the opposite direction.

On the other hand, the synchronous inverting amplifier circuit 44 has a current mirror circuit 60 as shown in the input stage.

That is, the input quadrant transistor 1 at the first stage is connected as an emitter follower, and its collector is connected to the power supply V.

The emitter is grounded through an emitter circuit including a resistor 62, a forward diode 63, and a resistor 64 connected in this order.

The connection point between the resistor 62 and the diode 63 is connected to the base of an inverting amplification transistor 65 at the next stage.

The emitter of this transistor 65 is grounded via a resistor 66, and the collector is connected to the power supply V via a resistor 67.

connected to. On the other hand, the integrating circuit 42 is made up of a resistor 71 and a capacitor 72, and the second separating circuit 43 is connected to the output end of the input capacitor 81 via the discharging resistor 82 to the power supply o, and also connects the amplitude separating transistor 83. The emitter of this transistor 83 is grounded, and the collector is connected to the base of the inverting amplification transistor 65 of the current mirror circuit 60.

Next, the operation of the synchronizing signal separation circuit having the above configuration will be explained.

The overall operation is the same as the operation in Fig. 2 described above with reference to Fig. 3, and the vertical synchronization signal can be reliably separated, and synchronization can be stabilized without disturbing the horizontal AFC circuit. can be converted into

On the other hand, the detailed operation is as follows.

First, as is well known, in the amplitude separation operation of the composite synchronization signal in the first separation circuit 41, when the synchronization signal is input manually, the capacitor 52 is charged and the transistor 54 is turned on.
When the synchronization signal is not input, the accumulated charge of the capacitor 52 is discharged along the path of the resistor 53 → capacitor 52 → resistor 51, and the transistor 54 is in an off state.

Similarly, in the second separation circuit 43, the transistor 8
Since the base current necessary for the ON operation of 3 flows, if the emitter follower connection transistor 61 of the current mirror circuit 60 inserted between the collector of the transistor 83 and the power supply VC is in the ON state at this time, the above transistor 83 is also turned on.

The vertical synchronizing signal obtained by amplitude separation from the output of the integrating circuit 42 is one in which the notch pulse in the signal is missing and the signal width is widened (see FIG. 3d), and the vertical synchronizing signal period is The transistor 83 of the second separation circuit 43 is in the on state, and at this time the current mirror 60
The base potential of the inverting amplifying transistor 65 becomes approximately zero, and the inverting amplifying transistor 65 is turned off.

Therefore, at this time, the collector voltage of the transistor 65, that is, the output signal level is the power supply V.

becomes the potential of

Further, the emitter follower connection transistor 61 of the current mirror circuit 60 is controlled on and off by its base potential.

That is, when the transistor 59 of the first separation circuit 41 is in the off state (when the synchronization signal is not output), the power supply ■.

Since the voltage is supplied to the base of the transistor 61 through the resistor 56, the transistor 61 is turned on.

At this time, when a part of the emitter current of the transistor 61 flows to the base of the inverting amplification transistor 65 and this transistor 65 is turned on, the collector voltage of this transistor 65 becomes the power supply V.

The voltage decreases by the voltage drop of the resistor 67 compared to the voltage of the resistor 67.

Next, when the transistor 54 of the first separation circuit 41 is on (when the synchronization signal is output), the collector-emitter saturation voltage of this transistor 54 is ■.

A voltage (VCE (SAT+VF)), which is the sum of E(SAT) and the forward voltage VF of the diode 55, is applied to the base of the inverting amplification transistor 61.

However, this base voltage is equal to the emitter-to-emitter voltage 8E of the transistor 61 and the forward voltage VF of the diode 63.
Since the voltage is smaller than the sum voltage (VBE + VF), that is, VCE (SAT+VF<VBE+VF), the transistor 61 is turned off, and therefore the inverting amplification transistor 65 is turned off because forward bias is no longer applied to its base. , and its collector voltage is the power supply V.

voltage. Furthermore, as mentioned above, the current mirror 60
The threshold level of the first stage transistor 61 (VB
Due to the pulse shaping of the composite synchronization signal input determined by E + VF), the maximum amplitude value of this synchronization signal becomes slightly smaller,
This degree hardly poses a problem in terms of synchronization performance.

Thus, in the current mirror circuit 60, the inverting amplification transistor 65 is turned off when the composite synchronization signal from the first separation circuit 41 is input and when the vertical synchronization signal from the second separation circuit 43 is input. Even if there is a slight phase difference between the two powers, the superimposed inverted synchronization signal that appears will be at the potential of the power supply (c), and no level difference will occur in the superimposed portion.

Further, in a portion of the composite synchronization signal output waveform of the first separation circuit 41 that is below a predetermined level, the input quadrant transistor 1 in the synchronous inversion amplifier circuit 44 is turned off and does not perform amplification operation.
At this time, the composite synchronization signal output waveform is slightly lower than the above-mentioned predetermined level (collector-emitter saturation voltage V of the transistor 54).

Since the input transistor transistor 1 performs amplifying operation at the moment when the difference between E(SA□) and the pace-emitter voltage vBE of the transistor 61 changes, problems such as waveform delay due to synchronous inversion amplification do not occur.

As described above, the present invention provides a synchronization signal separation circuit that can improve synchronization performance without causing any level difference in the superimposed output of amplitude-separated composite synchronization signals and vertical synchronization signals, and without interfering with other performances. can do.

[Brief explanation of the drawing]

Figures 1a and 1) are waveform diagrams showing the normal state and undulating state of the synchronous signal separation circuit human input signal, Figure 2 is a block diagram showing the conventionally considered synchronous signal separation circuit, and Figure 3 is the FIG. 4 is a signal waveform diagram shown to explain the operation shown in FIG. 4, and FIG. 4 is a circuit diagram showing an embodiment of the synchronization signal separation circuit according to the present invention. 41...First separation circuit, 42...Integrator circuit, 43...Second separation circuit, 44...
...Synchronous inverting amplifier circuit, 45...Frequency separation circuit, 54.61.65.83...Transistor, 55°63...Diode, 62°64° 66°67... Resistor, 60... Current mirror circuit.

Claims (1)

[Claims for Utility Model Registration] An input terminal to which a composite synchronization signal is applied; a signal separation level setting means connected to the input terminal on the input end side and setting a reference DC level for the composite synchronization signal; A signal extracted from the composite synchronization signal at a level set by the separation level setting means is input to the base side, a first transistor has a load, a load voltage of the first transistor is input to the base side, and an emitter is input to the base side. a second transistor having a resistor circuit on its side; a third transistor that switches according to the current flowing through the resistor circuit on the emitter side of the second transistor; and horizontal and vertical an output terminal for outputting a synchronization signal, an integration circuit connected to the input terminal, and a vertical synchronization signal extraction level setting means for setting a reference DC level for extracting a vertical synchronization signal according to the output of the integration circuit; at least a switching transistor that switches in response to the output of the vertical synchronization signal extraction level setting means to substantially short-circuit a resistor circuit on the emitter side of the second transistor and cut off the second transistor; 1. A synchronization signal separation circuit characterized in that a horizontal synchronization signal and a vertical synchronization signal train are properly extracted from a composite synchronization signal regardless of fluctuations in the DC level of the composite synchronization signal.