KR820002376B1 - Line sampling circuit for television system - Google Patents

Abstract

A composite synchronizing signal during a vertical blanking interval includes horizontal sync pulses, equalizing pulses and vertical sync pulses. A line sampling circuit includes a vertical pulse gate which detects and filters an even number of vertical sync pulses, a flyback pulse gate which filters the flyback pulses sequentially after the vertical pulse gate has filtered the even number of vertical sync pulses, and a 5-bit binary counter which counts the even number of vertical sync pulses and the flyback pulses.

Description

Line Extraction Generation Circuit

1 is a signal waveform diagram obtained from a television receiver and a line extraction generating circuit of the present invention.

2 is a graph of the components of a VIR signal included as part of a television signal.

FIG. 3 is a waveform diagram obtained from a conventional lie extraction generating circuit. FIG.

4 is a block diagram of a line extraction generating circuit of the present invention.

FIG. 5 is a circuit diagram of one embodiment of the line extraction generating circuit shown in FIG.

FIG. 6 is a waveform diagram for explaining the line extraction generating circuit shown in FIG.

7 is a waveform diagram obtained from a differential circuit used in the vertical pulse gate circuit of the re-extraction generation circuit of the present invention.

8 is a waveform diagram obtained from each flip-flop circuit used in a 5-bit binary counter of the line extraction generating circuit of the present invention.

9 is a circuit diagram in which a part of the vertical pulse gate circuit is modified.

10 is a waveform diagram obtained from FIG.

11 is a circuit diagram in which the flip-flop circuit used for the 5-bit counter is changed.

12 is a circuit diagram in which a part of the reset decoder is changed.

The present invention is an improvement on the circuitry of a television receiver, and more particularly relates to a circuit arrangement for extracting specific lines included in certain unusual vertical blanking periods.

As shown in FIG. 1A, the composite synchronization signal includes a horizontal synchronization pulse P1, an equalization pulse P2, and a vertical synchronization pulse P3. These pulses have the same amplitude but different frequencies and pulse widths.

Several lines included in the vertical retrace period and defined by neighboring horizontal synchronization pulses P1 are used to carry various kinds of signals. For example, one type of signal is a reference signal, commonly referred to as a vertical period reference VIR signal.

This VIR signal, shown schematically in FIG. 1A, is carried on the 19th line of the received image, which may be included on any other line or multiple lie.

The line of vertical blanking carries a complex speech signal or any other signal such as a video signal.

In the following description, the 19th line carries a VIR signal.

The VIR signal shown enlarged in FIG. 2 is used for automatic hue and saturation adjustment in a color television receiver.

This VIR signal includes a color burst component, a chroma reference component, a luminance weight component and a black reference component.

In order to use the VIR signal, it is necessary to detect and extract a specific line, that is, the 19th line carrying the VIR signal, at which time the VIR signal is detected in comparison with the video signal.

In the step of extracting a specific line that carries a VIR signal, it is usually counted from a particular distinction to a specific pulse that occurs before the particular line. According to the conventional method, the reference line is represented by using an integrated circuit having a constant time compared with an equalizing pulse or a horizontal synchronizing pulse regardless of the vertical pulse width.

Such an integrated circuit uses an RC integrated circuit, in which a pulse voltage is charged to the capacitor from the start of each even and odd region to separate the waveform necessary for vertical synchronization.

Voltages charged to this capacitor are shown in the even and odd regions in FIGS. 3b and 3d, respectively.

When horizontal or equalizing pulses are applied to the RC integrating circuit, they do not charge the capacitor to any suitable voltage because of a short pulsation period or a long period between adjacent pulses.

However, when the vertical sync pulses are adjacent, the voltage across the capacitor rises above the value required to trigger a reference circuit for detecting the reference pulse or a circuit such as a vertical deflection oscillator.

Since there is a half line difference between the odd and even regions (see FIGS. 3a and 3b), the time interval between the first equalizing pulse (P ₁ ') and the last horizontal synchronizing pulse (P ₂ ') is greater than that of the even region. Odd area is short.

Therefore, the capacitor reaches the trigger voltage more rapidly in the odd region than in the even region.

As such, the trigger instants in the even and odd regions do not coincide with each other. As a result, the reference line detected by the RC integrating circuit will change with respect to the area difference.

In other words, a specific line accompanying the VIR signal is detected and extracted only in one region of the even region or the odd region.

Moreover, because the voltage charged in the capacitor becomes serrated, the trigger moment is easily missed and the function malfunctions.

Furthermore, there is a drawback that the RC integrating circuit requires precise adjustment to obtain a predetermined time.

Prior art color television receivers that handle television information with a VIR signal as described above are described, for example, in US Pat. 4. Patent No. 3,950,780 dated 13 may be cited.

It is therefore a primary object of the present invention to provide an improved circuit arrangement for extracting specific lines involved in any suitable vertical blanking period.

It is a second object of the present invention to provide a circuit arrangement as described above for detecting and extracting a specific scan cool.

A third object of the present invention is to provide the above circuit arrangement which can stabilize the operation.

It is a fourth object of the present invention to provide the above circuit arrangement which is simple in structure and which can be easily manufactured at low cost.

According to an embodiment of the present invention, the line extraction circuit includes a vertical pulse gate circuit, a gate circuit, a flyback pulse gate circuit, a vertical pulse gate decoder, a 5-bit binary counter, a reset decoder and a line decoder. It is designed to generate a pulse indicating the presence of a specific line from the pulse decoder.

Since the line extracting circuit of the present invention is directly connected to a system which extracts a line carrying a VIR signal in particular, the line decoder is designed to detect a scan line accompanying a VIR signal.

Therefore, in order to better understand the present invention, a line decoder that detects a line carrying a VIR signal will hereinafter be referred to as a VIR pulse decoder.

However, this pulse decoder includes a circuit for generating a pulse indicating the presence of a specific line accompanying a complex audio signal or a video signal. The 5-bit binary counter counts the pulse train generated from the vertical pulse gate circuit and the flyback gate circuit, where the first two pulses are generated from the vertical pulse gate circuit, while the remaining pulses are generated from the flyback gate circuit. .

The first two pulses from the vertical pulse gate circuit coincide with the first two vertical sync pulses contained in the composite sync pulse.

Such first two vertical synchronization pulses are detected by a differential amplifier included in the vertical pulse gate circuit, where each pulse of the composite ceramic pulse is converted into a sawtooth pulse having a different amplitude for a different pulse duration of each composite ceramic pulse. .

Since this vertical synchronization pulse has the longest pulse period for another pulse, the sawtooth pulse converted from the vertical synchronization pulse has the largest amplitude.

The sawtooth pulse with the largest amplitude is detected by the differential amplifier.

The present invention will now be described in detail with reference to the accompanying drawings in connection with the foregoing embodiments.

Prior to the description of the present invention, like parts of the accompanying drawings are denoted by the same symbols.

4 shows a block diagram of the line extraction circuit (LSC) of the present invention. The line extraction circuit LSC includes a vertical synchronous pulse gate circuit VP, a gate circuit GC, a flyback pulse gate circuit FP, a vertical synchronous pulse gate decoder GD, and a 5-bit binary counter. BC), reset tree coder RD, and VIR pulse decoder PD.

The vertical pulse gate circuit VP receives a compound equalized pulse (waveform shown in Fig. 1b) calculated from the synchronous separator SS, and has a 5-bit binary counter BC, a reset tree coder RD, and a VIR pulse. And a decoder PD.

This vertical pulse gate circuit VP receives a composite synchronous pulse (waveform of FIG. 1b) calculated from the synchronous separator SS, and the 5-bit counter BC detects only the vertical synchronous pulse to be supplied.

The vertical pulse gate decoder GD connected to the 5-bit counter BC calculates an appropriate signal such as two vertical sync pulses after the 5-bit counter BC counts an even number of vertical sync pulses.

Upon receiving the appropriate signal from the vertical pulse gate decoder GD, the gate circuit GC controls the vertical pulse gate VP so that the vertical sync pulse is no longer supplied to the 5-bit counter BC. At the same time, the flyback pulse gate FP is activated.

Under the operation of the flyback pulse gate FP, a horizontal flyback pulse (waveform shown in Fig. 1 (e)) generated from the flyback circuit FC is applied to the 5-bit counter BC.

This flyback pulse can be replaced by any other type of pulse that occurs every horizontal time. Such pulse type is generally called horizontal frequency pulse.

Accordingly, the 5-bit counter BC receives two vertical synchronization pulses (first wave (d) waveform) from the vertical pulse gate VP, and then receives the flyback pulse train from the flyback pulse gate FD. Receive.

As a result, the 5-bit counter BC receives the pulse train shown in FIG. 1 g, and the VIR pulse decoder PD connected to the 5-bit counter BC is the 17-bit pulse of the 5-bit counter BC. After counting, the pulsation signal S (first wave (O) waveform) is calculated.

The pulse period of the pulsation signal S calculated from the VIR pulse decoder PD is equal to 1 line horizontal syringe interval, i.e., 1H, so that the pulsation signal S covers the 19th line carrying the VIR signal. do.

The decoder RD connected to the 5-bit counter BC calculates the reset signal (first h waveform) after the 5-bit counter BC counts the 21st pulse.

Such a reset signal is applied to the 5-bit counter BC and the gate circuit GC to reset the line extraction circuit LSC to the initial state, in which the vertical pulse gate VP is in a continuous region. Prepare to count the vertical sync pulses.

In FIG. 5, a circuit diagram of the line extraction circuit LSC described above is shown.

The vertical pulse gate VP includes an emitter grounded transistor T ₃ , the base of which is connected to the first terminal A ₁ through a resistor R ₂ and a zener diode ZD and sequentially. It is connected to the synchronous separator (SS).

This resistor (R ₂ ) and zener diode (ZD) are for removing noise. Since the composite synchronous pulse (first b wave form) applied to the base of the transistor T ₃ is a negative pulse, the transistor T ₃ is a horizontal synchronous pulse P ₁ , an equalizing pulse P ₂ and a vertical synchronous pulse ( It is turned off while any of P ₃ ) is present.

The pair of transistors T ₁ and T ₂ forming the differential amplifier are connected between the power supply line L ₁ and ground through an appropriate resistor. In particular, the collector of transistor T ₁ is connected to power line L ₁ through a resistor R ₃ , and the collector of transistor T ₂ is connected to power line L ₁ through a resistor R ₄ . do.

The emitters of these transistors T ₁ , T ₂ are connected to each other and grounded through a resistor R ₅ . The base of the transistor T ₂ is supplied with a predetermined voltage Ex obtained from the junction between the resistors R ₆ and R ₇ connected in series between the power supply line L ₁ and ground.

Such a predetermined voltage Ex is expressed as follows.

Ex = R ₆ / (R ₆ + R ₇ )

Where R ₆ and R ₇ are resistors designed with the same characteristics.

Meanwhile, the base of the transistor T _{1 is} connected to the terminal A ₃ and the collector of the transistor T ₃ .

Terminal A ₃ is connected to ground via condenser C ₁ and also to wire L ₁ via resistor R ₁ .

When transistor T ₃ is turned on, current flows from power line L ₁ to ground through resistor R ₁ , and at the same time, the voltage charged in capacitor C ₁ is discharged through transistor T ₁ . do.

Therefore, the base of transistor T ₁ does not receive the bias voltage.

On the other hand, when the transistor T ₃ is turned off, the voltage Vcc appearing on the power supply line L ₁ appears in the capacitor C ₁ .

Therefore, the capacitor C ₁ reaches the voltage for the time constant determined by the resistor R ₁ and the capacitor C ₁ .

Such a voltage charged across the capacitor C ₁ is applied to the base of the transistor T ₁ .

FIG. 1 shows the voltage charged in the capacitor C ₁ . As shown in FIG. 1 waveform C, the capacitor C ₁ is charged to the highest voltage when the vertical synchronization pulse P ₃ is applied to the transistor T ₃ .

On the other hand, the capacitor C ₁ is charged to the lowest voltage E ₂ when the equalizing pulse P ₂ is applied to the transistor T ₃ .

When the horizontal synchronous pulse P ₁ is applied to the transistor T ₃ , the capacitor C ₁ is charged to a voltage level E _{1 which} is slightly higher than the voltage level E ₂ .

When the predetermined voltage Ex satisfies the following equation, that is, when E ₂ < Ex < E ₃ , a constant pulse string coinciding with the vertical synchronization pulse appears in the collector of the transistor T ₂ .

Such a positive pulse train is connected in series to produce a negative pulse train from the collector of transistor T ₅ and is connected between ground and power line L ₁ via resistors R ₉ and R ₁₀ . ₅ ) is applied to the base. This negative expansion column is extracted from the junction J ₁ between the resistors R ₆ and R ₁₀ and supplied to the 5-bit counter BC.

This vertical pulse gate VP comprises a transistor T _{6 which is} connected between the collector of transistor T ₂ and ground via a resistor R ₃ , and the base of transistor T ₆ also has a resistor R _S ′. )

The functions of these transistors T ₆ , resistors R _S , and R _S ′ will be described later together with the description of the gate circuit GC.

The 5-bit counter BC is connected in series, and each of the five flip-flop circuits F ₁ , F ₂ , F ₃ , F ₄ , and F ₅ , each forming a so-called T-network. Include.

Since five sets of T-type flip-flops are exactly the same arrangement with each other, only one flip-flop circuit F ₁ is described in detail and the other is omitted.

The flip-flop circuit F ₁ includes a pair of transistors T ₁₁ , T ₁₂ and another pair of emitter ground transistors T ₉ , T ₁₀ .

The base of the transistor T ₁₁ is connected to the collector of the transistor T ₁₂ via a resistor R ₁₂ and in turn to the power supply line L ₁ through a resistor R ₁₅ . In the same way, the base of the transistor T ₁₂ is connected to the collector of the transistor T ₁₁ via a resistor R ₁₁ , which in turn is connected to the power supply line L ₁ via a resistor R ₁₄ .

To the base of the emitter of the transistor (T ₁₀₎ of the transistor (T _11), the collector of the transistor (T _9), is also connected to a power supply line (L ₁₎ via a resistor (R _13). In the same way, the emitter of transistor T ₁₂ is connected to the base of transistor T ₉ and to the collector of transistor T ₁₀ and to the power supply line L ₁ via a resistor R ₁₆ .

₁)로 부터 출력신호가 산출되도록 설계되었다.The above-described flip-flop circuit F ₁ has terminals S ₁ and (

_It is designed to calculate the output signal from ₁ ).

₁)로 부터 산출된 신호는 2진 형태의 신호이며, 이것은 고레벨 2진 신호 또는 저레벨 2진 신호이다. 출력단자(S₁)로 부터 산출된 신호는 다른 출력단자(

₁)로 부터 산출된 신호와 반대위상이다.Such output terminals S ₁ and (

The signal calculated from ₁ ) is a binary signal, which is a high level binary signal or a low level binary signal. The signal calculated from the output terminal S ₁ is converted to another output terminal (

_It is out of phase with the signal calculated from ₁ ).

This flip-flop circuit F ₁ is initially designed such that a low level signal is output to the output terminal S ₁ and its output under the reception of a vertical synchronization pulse or a flyback pulse through transistors T ₇ and T ₈ . Change the signal level. The bases of transistors T ₇ and T ₈ are connected to the junction J ₁ of the vertical pulse gate VP via a suitable resistor.

The base of transistor T ₈ is grounded and its collector is connected to the emitter of transistor T ₇ and the collector of transistor T ₉ .

₁)가 고레벨인 플립플롭회로(F₁)의 초기상태에서, 트랜지스터(T₁₁)는 오프되고, 트랜지스터(T₁₂)는 온 된다.The collector of transistor T _{7 is} connected to the collector of transistor T ₁₀ . The output terminal S ₁ is low level and the output terminal S

_In the initial state of the flip-flop circuit F ₁ where ₁ ) is high level, the transistor T ₁₁ is turned off and the transistor T ₁₂ is turned on.

The emitter current of transistor T ₁₂ therefore flows to ground through transistors T ₇ and T ₈ .

Junction is a polarity pulse portions to the base from the (J ₁₎ the transistor _{(T 7), (T 8} ) goemyeon, the emitter of the transistors _{(T 7), (T 8} ) is turned off and the transistor (T ₁₂₎ Current to ground.

Thus, the transistor (T ₁₂₎ the emitter current is turned on to flow a base transistor (T ₉₎ of the transistor (T _9), and as a result generating a bias voltage across the emitter and base of the transistor (T _11).

Thus, the flip-flop circuit F ₁ changes to another state where the transistor T ₁₁ is turned off and the transistor T ₁₂ is turned on.

In this flip-flop circuit F ₁ , it is necessary to generate two negative pulses to complete one cycle operation, that is, to change the circuit into two states. The output signal waveforms of the terminals S ₁ , S ₂ , S ₃ , S ₄ , and S ₅ of the respective flip-flop circuits are shown in FIG. .

The vertical pulse gate decoder GD includes a multi-emitter transistor or decoder transistor T ₁₉ whose base is grounded through transistor T ₂₀ .

₁), (S₂), (

₃),(

₄),(

₅)에 연결된 5개의 에미터 세트와 연결된다.The base of transistor T ₂₀ is connected to terminal A ₂ through resistor R ₂₁ . Transistor T ₁₉ is the output terminal of each flip-flop (

₁ ), (S ₂ ), (

₃ ), (

₄ ), (

₅ emitter sets connected to ₅ ).

₁), (S₂), (

₃), (

₄), (

₅)는 모두 고출력 레벨을 나타낸다.When the 5-bit counter BC counts two negative pulses received from the vertical pulse gate VP, the output terminal (

₁ ), (S ₂ ), (

₃ ), (

₄ ), (

₅ ) all indicate high power levels.

Thus, the emitter voltage of the multi-emitter transistor T ₁₉ exhibits a voltage approximately equal to the bias voltage applied to the base of the transistor T ₁₉ through the resistor R ₂₀ , and the collector-emi of the transistor T ₁₉ . Prevent intercurrent flow.

Therefore, the bias voltage present on the base of the transistor (T ₁₉₎ is applied to the base through the collector of the transistor (T ₁₉₎ the transistor (T _17).

₂)에 연결되고, 그 콜렉터는 트랜지스터(T₁₇)의 베이스에 연결된다. 게이트회로(GC)는 트랜지스터(T₁₇)와, 한 쌍의 에미터 접지형 트랜지스터(T₁₅), (T₁₆)를 내포하는 플립플롭회로(F₆)를 구성한다. 이 트랜지스터(T₁₅)의 베이스는 저항(R₂₄)을 통해 트랜지스터(T₁₆)의 콜렉터에 연결된다. 마찬가지로 트랜지스터(T₁₆)의 베이스는 저항(R₂₅)을 통해 트랜지스터(T₁₅)의 콜렉터에 연결된다.The vertical pulse gate geocoder GD further includes a transistor T ₁₈ with an emitter grounded, the base of which is connected to an output terminal (R ₂₂ ) via a resistor R ₂₂ .

₂ ), the collector of which is connected to the base of transistor T ₁₇ . The gate circuit GC constitutes a transistor T ₁₇ and a flip-flop circuit F ₆ containing a pair of emitter ground type transistors T ₁₅ and T ₁₆ . The base of this transistor T ₁₅ is connected to the collector of transistor T ₁₆ via a resistor R ₂₄ . Similarly, the base of transistor T ₁₆ is connected to the collector of transistor T ₁₅ via a resistor R ₂₅ .

The collectors of transistors T ₁₅ and T ₁₆ are connected to power supply line L ₁ via resistors R ₂₇ and R ₂₆ , respectively.

When the transistor T ₁₇ is turned on by the trigger pulse calculated from the multi-emitter transistor T ₁₉ , the base of the transistor T ₁₆ is grounded off through the resistor R ₂₅ . At the same time transistor T ₁₅ is turned on.

At this time, the high voltage level appearing at the collector of the transistor T ₁₆ is applied to the base of the transistor T ₆ used for the vertical pulse gate VP to ground the collector of the transistor T ₂ .

Therefore, two positive pulse trains calculated from the corrector of the transistor T ₂ are applied to the base of the transistor T ₅ so that two negative polarities (first waveguide) appear at the junction J ₁ .

On the other hand, the low voltage level appearing at the collector of transistor T ₁₅ is applied to transistor T ₁₃ through flyback pulse gate FD.

This flyback pulse gate FD comprises transistors T ₁₃ and T ₁₄ with an emitter grounded, where the collector of transistor T ₁₃ is connected to the base of transistor T ₁₄ .

The base of transistor T ₁₄ is connected to terminal A ₂ via a resistor R ₂₉ to receive a flyback pulse.

The collector of transistor T ₁₄ is connected to the bases of transistors T ₇ and T ₈ through suitable resistors, so that the vertical pulse gate supplies negative polarity to the 5-bit counter BC after supplying two negative pulses. Supply flyback pulses. In addition, the flyback pulse gate FD includes a reverse biased diode D ₁ connected between terminal A ₂ and ground.

When the low voltage level signal is received from the collector of the transistor T ₁₅ , the transistor T ₁₃ is turned off to apply the pulsating voltage of the flyback pulse to the base of the transistor T ₁₄ .

The transistor T ₁₄ thus generates a negative flyback pulse from its collector and supplies it to the junction J ₁ . Thus, the 5-bit counter receives the negative pulse train as shown in the first g wave form.

In the 1g wave form, the first two negative pulses are obtained from the vertical pulse gate VP and the remaining pulses are obtained from the flyback pulse gate FD.

The number of pulses supplied to the 5-bit counter from the vertical pulse gate (VP) is not limited to two, and perhaps more than two will be even, such as four or six. FIG. 6 shows a malfunction waveform in which only a negative pulse (waveforms 6b and 6f) received by the 5-bit counter BC is received if the number of pulses becomes odd, such as 1. FIG.

In the even-numbered region, one negative pulse filtered through the vertical pulse gate VP will coincide with one flyback pulse. On the other hand, in the case of the odd region, one negative pulse from the vertical pulse gate VP will deviate from the flyback pulse. Therefore, if the negative pulse filtered through the vertical pulse gate VP and the negative pulse filtered through the flyback pulse gate FD are visible, the number of pulse trains obtained during the series of odd regions (Fig. 6h waveform) It will be larger than the number of pulse trains (Fig. 6d waveform) obtained during the even region.

In order to detect one particular line by counting such pulse trains, it is necessary to calculate the same number of pulses within the same time period. Thus, the difference in such pulse trains between even and odd regions will be the difference of the detected lines. At this point, the pulse filtered through the vertical pulse gate VP corresponds to an even number of pulses. According to the above embodiment, the number of pulses filtered through the vertical pulse gate is two because of the following. As in the vertical pulse gate VP, in a circuit that handles a small amount of voltage and electric field, the pulse gain calculated from the collector of the transistor T ₂ tends to decrease in amplitude as shown in FIG. Therefore, in order to ensure the operation of the vertical pulse gate, in particular the transistor T ₅ , it is preferable to use the two negative pulses shown on the left side of FIG.

₂), (

₃), (

₄), (S₅)에 연결된 5개의 에미터 세트와 연결된다.This VIR pulse decoder PD comprises a multi emitter transistor T ₃₃ , which base is connected to an emitter grounded transistor T ₃₄ . The base of transistor T ₃₄ is connected to terminal A ₂ through resistor R ₃₁ . The multi-emitter transistor T ₃₃ has the output terminals S ₁ and () of each flip-flop circuit.

₂ ), (

₃ ), (

₄ ), connected to 5 emitter sets connected to (S ₅ ).

₂), (

₃), (

₄), (S₅)는 모두 고출력 레벨이된다. 이리하여 멀티 에미터 트랜지스터(T₃₃)의 에미터 전압은 저항(R₃₀)을 통해 트랜지스터(T₃₃)의 베이스에 인가된 바이어스 전압과 대략동일 전압으로 되어, 트랜지스터(T₃₃)의 콜렉터-에미터 간전류의 흐름을 차단한다.When the 5-bit counter BC counts 17 pulses received from the vertical pulse gate VP, the output terminals S ₁ , (

₂ ), (

₃ ), (

₄ ), (S ₅ ) are both high power levels. Thus, the emitter voltage of the multi-emitter transistor T ₃₃ becomes approximately the same voltage as the bias voltage applied to the base of the transistor T ₃₃ through the resistor R ₃₀ , so that the collector-emi of the transistor T ₃₃ is Shut off the flow of inter-current.

In other words, the multimeter emitter transistor T ₃₃ is turned off. Therefore, the bias voltage applied to the base of the transistor (T ₃₃₎ is applied to the base of the transistor (T ₃₃₎ of the transistor (T ₃₅₎ the emitter is grounded through the collector of the. The collector of the transistor T ₃₅ is connected to the power supply line L ₁ and the base of the transistor T ₃₆ . The collector of transistor T ₃₆ is connected to power supply line L ₁ , and its emitter is grounded through resistor R ₃₃ . At the junction J ₂ between the emitter of the transistor T ₃₆ and the resistor R ₃₃ , the negative pulsation signal S (first waveguide) having a pulse period at which the nineteenth line is dedicated to the VIR signal and the pulse period is etched. Is calculated. The pulse decoder RD further comprises a meter grounded transistor T ₃₇ , the base of which is connected to the emitter of the transistor T ₃₆ via a resistor R ₃₂ . The collector of the transistor T ₃₇ is connected to the power supply line L ₁ through a resistor R ₃₄ and to the base of the transistor T ₃₈ .

Transistor T ₃₈ is a collector connected to power line L ₁ , and its emitter is grounded via resistor R ₃₅ .

At the junction J ₃ between the emitter of the transistor T ₃₈ and the resistor R ₃₅ , a positive pulsation pulse exactly opposite to the negative pulsation pulse S described above is calculated.

The output signal calculated from junctions J ₂ and J _{3 is} provided to the next stage circuit (not shown) designed to separate the VIR signal from the composite synchronous pulse, or to the VIR signal or to another circuit. The VIR pulse decoder PD described to calculate two output signals having opposite wefts may produce only one output signal depending on the circuit type connected to the next stage.

Transistor transistor coupled to the base of (T ₃₃₎ (T ₃₄₎ is a flyback since on for a pulse presence trafficking register (T ₃₃₎ and a Trafficking register for base ply existence period of the back-pulse (T ₃₅₎ (T ₃₄₎ Grounded through. In other words, the transistor T ₃₅ is controlled only in the absence of the flyback pulse. Therefore, the pulse calculated from the collector of transistor T ₃₅ has exactly the same pulse period as one line period 1H excluding the flyback pulse period. The reason why the transistor T ₃₄ is used to exclude the transistor T ₃₃ is described below.

In general, a counter using a logic circuit such as an AND circuit feeds back to the input of the counter to synchronize its output. However, counters that do not feedback the output, i.e. counters that do not require synchronization, do not require a feedback system, but are complex structures. In this regard, the counter of the present invention shown in FIG. 5 has a simple structure and does not use a feedback system.

Since the counter used in the line extraction circuit (LSC) of the present invention is not fed back to the input of the counter, the signal calculated from each flip-flop circuit is likely to be delayed, and in particular, the flip-flop circuit includes a first flip. It is delayed further than the flop circuit F ₁ .

Eighth also shown in the output of the first flip-flop circuit (F ₁₎ the flip-flop circuit (F ₁₎ when receiving the 16th to the flyback pulse (F _5). The solid waveform is the ideal waveform and the dashed waveform is the actual waveform calculated from each flip-flop circuit.

As shown in the waveform of FIG. 8, the response of each flip-flop circuit is delayed in time. Such a delay results in a breakaway pulse that turns off the multi-actor transistor T ₃₃ at an unexpected moment. In order to prevent such an operation, the transistor (T ₃₃₎ for flyback in the absence of the pulse, that is, the flyback transistor (T ₃₅₎ by the switching operation of the transistor (T ₃₄₎ connected to the base during the pulse period, transistor (T ₃₃₎ To control.

Thus, the multi-emitter transistor T ₃₃ will only respond during the pulsation period given by the solid line in FIG.

With such a structure, the time delay incurred from each flip-flop circuit prevents malfunction in the 5-bit counter. Moreover, the time period between neighboring flymac pulses, in particular between flyback pulses 17 and 18 indicated in the first g wave form, is long enough to include the time of the VIR signal. For the same purpose, the switching transistor T ₂₀ provided in the vertical pulse gate decoder GD controls the multi-emitter transistor T ₁₉ with the above-described banburb. Furthermore, the multi-emitter transistor T ₃₁ is controlled in the same manner to the switching transistor T ₃₂ provided in the reset decoder RD described below. In FIG. 5 again, the reset decoder RD includes a multi emitter transistor T ₃₁ , the base of which is connected to an emitter ground type transistor T ₃₂ , and thus of the multi emitter transistor T ₃₁ . Control the operation. The base of the transistor T ₃₂ is connected to the terminal A ₂ through the resistor R ₃₇ so that the flyback pulse is applied by the transistor T ₃₂ .

₂), (S₃), (

₄), (S₅)에 연결된 5개의 에미터 세트를 가진다. 5비트 계수기(BC)가 수직펄스 게이트(VP)와 플라이백펄스 게이트(FD)로 부터 수신된 21개의 부극성 펄스를 계수할 때, 출력단자(S₁), (

₂), (S₃), (

₄),(S₅)는 모두 고출력 레벨로 나타나 트랜지스터(T₃₁)를 스위칭 오프시킨다. 그러므로 전원선(L₁)으로 부터 저항(R₃₆)을 통해 고전압을 수신하는 멀티 에미터 트랜지스터(T₃₁)는 그의 콜렉터로 부터 트리거신호를 발생시켜, 이는 순차로 에미터 접지된 트랜지스터(T₃₀)의 베이스에 인가된다.The multi-emitter transistor T ₃₁ has the output terminals S ₁ , (

₂ ), (S ₃ ), (

₄ ), it has five emitter sets connected to (S ₅ ). When the 5-bit counter BC counts 21 negative pulses received from the vertical pulse gate VP and the flyback pulse gate FD, the output terminals S ₁ and (

₂ ), (S ₃ ), (

₄ ), (S ₅ ) are all at a high output level to switch off the transistor T ₃₁ . Therefore, the multi-emitter transistor T ₃₁ , which receives a high voltage from the power supply line L ₁ through the resistor R ₃₆ , generates a trigger signal from its collector, which in turn emits an emitter grounded transistor T _30. Is applied to the base.

The collector of transistor T _{30 is} connected via a resistor R ₃₈ to the power supply line L ₁ and to the base of the emitter grounded transistor T ₂₉ . The collector of transistor T ₂₉ is connected to power line L ₁ via a resistor R ₃₉ . Upon receiving a trigger signal from the multi-emitter transistor T ₃₁ , transistors T ₃₀ and T ₂₉ are turned on and off, respectively, successively. In other words, when the positive trigger pulse signal is received from the multi-emitter transistor T ₃₁ , the transistor T ₂₉ generates an amplified positive pulse signal to the reset pulse generator.

The reset pulse generator comprises a transistor T ₂₈ whose base is connected to the collector of transistor T ₂₉ , a capacitor C ₃ connected between the emitter of transistor T ₂₈ and ground, and an emitter of transistor T ₂₇ . Resistor R ₄₆ connected between grounds.

The collectors of transistors T ₂₇ and T ₂₈ are connected to a power supply line L ₁ . When the amplified positive trigger pulse signal is received, the transistor T ₂₈ is turned on to charge the capacitor C ₃ . The voltage charged in the capacitor C ₃ is applied to the base of the transistor T ₂₇ to generate a reset pulse (waveform of FIG. 1h) from the collector of the transistor T27.

Such reset pulses are emitter grounded transistors T ₂₁ , (R ₄₄ ) through appropriate resistors R ₂₃ , R ₄₀ , R ₄₁ , R ₄₂ , R ₄₃ , and R ₄₄ , respectively. T ₂₂ ), (T ₂₃ ), (T ₂₄ ), (T ₂₅ ), and (T ₂₆ ). The transistor T ₂₁ is connected to the collector of the transistor T ₁₆ provided in the gate circuit GC. When a reset pulse from the transistor T ₂₇ is received, the transistor T ₂₁ is turned on to turn on the transistor T ₁₆ and simultaneously turn off the transistor T ₁₅ .

Thus flip-flop F ₆ changes state. Here, the transistor T ₁₃ is turned off and the transistor T ₁₄ is turned on to prevent the flyback pulse from being applied to the 5-bit counter BC. The control signal calculated from the collector of transistor T ₁₅ is a negative pulse (FIG. 1i waveform) with a fairly long time pulse, while the control signal calculated from the collector of transistor T ₁₆ is the negative signal mentioned above. It is a positive pulse having exactly the opposite phase to the polar pulse.

The collectors of transistors T ₂₂ , T ₂₃ , T ₂₄ , T ₂₅ , and T ₂₆ are flip-flop circuit terminals S ₂ , S ₁ , S ₃ , and S _4. ) And (S ₅ ). A reset pulse is received from transistor T ₂₇ , transistor T ₂₂ and transistor T ₂₆ are all turned on, and transistor T ₂₂ produces a low level signal on each collector of transistor T ₂ . . Therefore, the terminals S ₁ , S ₂ , S ₃ , S ₄ , and S ₅ generate a level signal, and reset the flip-flop circuits to their initial states.

The capacitor C ₃ installed in the reset pulse generator is provided to form a pulse to be applied to the base of the transistor T ₂ ⁸ .

When the pulse applied to the base of the transistor T ₂₈ has a small pulse period, the flip-flop circuit does not reset to the initial state. However, when the capacitor C ₃ is inserted between the transistor T ₂₈ and the branch, the pulse voltage generated from the transistor T ₂₈ is temporarily charged in the capacitor C ₃ .

Since the voltage charged in the capacitor C ₃ is discharged through the base-emitter of the transistor T ₂₇ having a relatively high impedance, the impedance between the base-emitter of the transistor T ₂₇ and the capacitor C ₃ The time constant determined by the capacity of is relatively long. Therefore, the time required for discharging the capacitor C ₃ is relatively long in the pulse period of the pulse applied to the transistor T ₂₈ . In this respect, the capacitor C ₃ has a relatively small capacity and a time constant for triggering the flip-flop circuit will be large enough.

For example, according to the embodiment described above, the capacity of the capacitor C ₃ is as small as 5PF. Therefore, the capacitor C ₃ having such a small capacity can be simply installed without requiring a large space.

As fully described above, the line extraction circuit of the present invention extracts specific scan lines with high reliability for even and odd regions because the vertical pulse gate VP provides exactly even pulses corresponding to the vertical synchronization pulses.

9 illustrates a circuit in which a part of the vertical pulse gate VP is modified.

The circuit of this embodiment includes an emitter grounded transistor T ₄ , whose collector extends to the base of line L ₂ and transistor T ₁ , the base of which is connected via a resistor R ₂ to a terminal ( A ₂ ). During the presence of the flyback pulse, transistor T ₄ is switched on to ground line L ₂ . The use and advantages of this transistor T ₄ are based on the following reasons.

According to the conventional television receiver set, the composite synchronization signal is calculated from the synchronization separator as shown on the left side of FIG. This synchronous separator SS includes transistors T ₄₀ , T ₄₁ and a capacitor C ₄ . A synchronous separator (SS) that deals with weak electric fields includes transistors (T ₄₀ ), (T ₄₁ ) and capacitor (C ₄ ). In a synchronous separator (SS) that deals with weak electric fields, the peak of the composite synchronous signal is subject to change due to the influence of the electric field. The DC current level calculated in this way is changed. In this respect, the pulse (Fig. 10i waveform) applied to the base of the transistor T ₄₁ D is somewhat adjusted by the capacitor C ₄ .

Thus, the threshold of the pulse that appears in the 9-degree junction (J ₄₎ (claim 10ii waveguide type) are for the initial pulse, that is, traffic register (T ₄₁₎ the pulse period of the applied pulse to the base of a transistor (T ₄₀₎ This results in widening at the level (K). As a result, the pulse (10th waveguide waveform) applied to the base of the transistor T ₃ becomes a pulse longer than the initial pulse to which the transistor T ₄₁ is applied.

If the fundamental pulse is an equalization pulse, this wide pulse will not be as wide as the vertical sync pulse width. However, if the basic pulse is a horizontal synchronous pulse, this wide pulse applied to the base of transistor T ₃ will be approximately equal to the vertical synchronous pulse period.

Thus, the capacitor C ₁ charged during the presence of such a wide pulse will be a high voltage, possibly exceeding the voltage level Ex described above. As a result, the differential amplifier generates a false signal from the collector of transistor T ₂ . However, if transistor T ₄ is used as shown in Fig. 9, line L ₂ is connected to ground through this transistor T ₄ during the presence of the flyback pulse.

This time is because the flyback pulse (10 iv wave form) partially coincides with this broad waveform (Fig. 10 iii wave form), so that the flyback pulse period from the wide pulse period while the capacitor C ₁ is charged It is for the rest of the time you delete it. Such remaining period corresponds to the pulse period shown in the 10v waveform, which is shorter than the vertical synchronization pulse period. Thus, there is no possibility of calculating a false signal from transistor T ₂ during the presence of the horizontal synchronizing pulse.

FIG. 11 illustrates another embodiment of the flip-flop circuit described above with reference to FIG.

This flip-flop circuit includes transistors T ₄₃ , T ₄₄ , T ₄₅ , and T ₄₆ , where transistors T ₄₃ , T ₄₄ are the main flip-flop and transistor T ₄₅ ), T ₄₆ constitutes an auxiliary flip-flop. When these flip-flop low level pulses are applied to the input terminal An, and the transistors T ₄₃ and T ₄₄ are in the conductive and non-conductive states, the driving transistors T ₄₇ and T ₄₈ are applied to the low level input pulses. It is switched off to turn off for a sufficient amount of time.

During this period, since the transistors T ₄₇ and T ₄₈ maintain linear operation, the transistors T ₄₃ and T ₄₄ constituting the main flip-flop are in the conductive and non-conducting states, respectively. However, the emitter potential of transistor T ₄₃ is substantially equal to the sum of base-emitter voltage vf and saturation collector-emitter voltage VcEsat of transistor T ₄₃ , so that a relatively small amount of base current It is supplied to (T ₄₄₎ . Therefore, the transistor T ₄₄ is brought into a conducting state with the potential decreased at the output terminal Sn, and as a result, the base current supplied to the transistor T ₄₃ decreases.

At this time, the collector potential of the transistor T ₄₃ increases with the resultant increase in the base current supplied to the transistor T ₄₄ , thereby creating a positive feedback loop that interrupts the conduction state of the transistor T ₄₃ , resulting in a transistor T ₄₄ ) to conduction state.

Resistor R ₅₉ and R ₆₀ facilitate this operation, and when the emitter potential of transistor T ₄₃ reaches voltage vf, VcEsat / R ₅ R ₅ where R ₅ is resistor R A current of a value equal to ₅ ) is supplied to the transistor T ₄₆ and accompanied by an increase in the collector current flowing through the transistor T ₄₄ , and the saturated collector-emitter voltage VcEsat of the transistor T ₄₃ is increased. The low voltage Sn of the output terminal is lowered to increase the saturated collector-emitter voltage VcEsat of the transistor T ₄₃ . However, when the low level signal is applied to the input terminal An again, the transistors T ₄₄ and T ₄₃ are switched off and switched on as described above.

The reset pulse generator of the circuit shown in Fig. 5 can be modified as either of Figs. 12A and 12B.

Variations of the reset pulse generator shown in FIGS. 12A and 12B may be used instead of the capacitor C ₃ having a relatively low capacitance, and can reduce the manufacturing volume of the reset pulse generator in the form of an integrated circuit. There is an advantage.

In FIG. 12A the reset pulse generator comprises a first transistor T ₂₈ ′ whose emitter is grounded through a capacitor C ₃ ′ and also connected to the base of the second transistor T ₂₇ ′.

"When applied to the base of the first transistor (T ₂₈ the input pulse (Pa) in this arrangement the first transistor (T ₂₈₎ ') is in the ON-state switch for the input pulse (Pa) period, the first transistor (T ₂₈ ') is charged to the capacitor (C ₃ '). A capacitor (C ₃ '), the voltage charged in the transistor (T _27' in the base of the emitter of) the transistor (T ₂₇ ') - appear over the emitter impedance. Thus, a negative voltage is present at the collector of transistor T ₂₇ ′. However, the base-emitter impedance of transistor T ₂₇ ′ is generally high, and the time required to completely discharge the voltage accumulated in capacitor C ₃ ′ is relatively long. Therefore, the negative sawtooth wave voltage Pb is generated across the resistor Pb inserted between the collector of the transistor T ₂₇ ′ and the power supply line L ₁ , and the sawtooth voltage Pb is the period of the input pulse Pa. For a longer time, it gradually reaches a voltage approximately equal to the power supply line L ₁ .

Such an arrangement as described above is used especially in the FIG. 5 circuit when the flip-flop circuit and / or other circuits are designed to be reset by a stiffness pulse. The capacitor C ₃ ′ shown and described as being connected between ground and the emitter of the transistor T ₂₈ ′ in the arrangement shown in FIG. 12a is a power supply line L ₁ and a transistor as shown in FIG. 12b. It may be inserted between collectors of (T ₂₈ ').

This arrangement produces a positive pulse from the collector of transistor T ₂₇ ′. In the arrangement shown in FIG. 12B, the transistor T ₂₇ ′ is a PNP type transistor, and the positive and negative terminals of the capacitor C ₃ ′ are connected to the collector of the power supply line L ₁ and the transistor T ₂₈ ′, respectively. Pay particular attention to what is being done.

As described above, in the modified form of the reset pulse generator shown in FIGS. 12A and 12B, the charging pressure of the capacitor C ₃ ′ is discharged using the base-emitter impedance of the transistor T ₂₇ ′, Although the capacitor C ₃ ′ is relatively low in capacity, the capacitor C ₃ ′ is designed to extend the time required to completely discharge the specified voltage to the capacitor C ₃ ′. Therefore, this modified reset pulse generator can be manufactured as an integrated circuit along with other circuit elements.

Although the present invention has been fully described by way of example with reference to the accompanying drawings, various changes and modifications will appear. Such changes and modifications are to be understood as belonging herein unless the invention departs from its true scope.

Claims (1)

A set of TV receivers comprising means for separating and generating complex synchronous pulses comprising means for generating equalization pulses, vertical synchronous pulses, horizontal synchronous pulses, and horizontal frequency pulses, the vertical horizontal collection period being calculated from adjacent horizontal The line extraction generating circuit LSC for detecting a specific line given between the projection pulses P ₁ , carrying a reference signal on the specific line, and calculating a signal indicating the existence of the specific line is a vertical synchronization pulse P _3. The first filtering means (VP) for filtering), the second filtering means (FP) for filtering the horizontal frequency pulse, the filtered vertical synchronizing pulse (P ₃ ) and the means for counting the filtered flat frequency pulse A second filtration means connected to the BC and the first and second filtration means VP and FP and for filtering the horizontal frequency pulse P ₁ when supplying an even number of vertical synchronization pulses P ₃ . (FP) is deactivated and an even number of via the first filtration means (VP) In order to filter the vertical synchronizing pulse P ₃ , it is connected to the counter BC to operate the first filtration means VP, and the vertical synchronous pulse P ₃ with the even number of the first filtration means VP is filtered. After that, the gate circuit and the counting means BC which inactivate the first filtration means VP for filtering the vertical synchronization pulse P ₃ and operate the second filtration means FP for filtering the horizontal frequency pulse. Line extracting means characterized in that it consists of a lyde coder means PD connected to the counting means for calculating the pulsating signal S having the same pulse duration as the one-line horizontal scan line period after the predetermined number of pulses are counted. Generating circuit.

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