JP3236526B2 - Multiplexer and its phase controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control device for a multiplexer for multiplexing frames to be multiplexed via an elastic store memory, and more particularly to a phase synchronization circuit for adjusting the phases of the frames to be multiplexed and the multiplexed frames. About.

[0002]

2. Description of the Related Art Hitherto, a multiplexing apparatus for multiplexing frames to be multiplexed via an elastic store memory has been known. This elastic store memory is a memory for performing bit phase synchronization and frame phase synchronization.

[0003] In such a multiplexing circuit,
As a phase synchronization circuit for controlling the phase of the multiplexed frame, for example, the multiplexing counter is reset at a timing when the frame pulses (FP) of the plurality of multiplexed frames are aligned, and the multiplexed frame is multiplexed into the multiplexed frame. . After the synchronization, the frame pulse (F
The reset of the multiplex counter is masked so that the phase does not change due to the jitter P).

FIG. 2 is a configuration diagram of a conventional multiplexer. The illustrated device includes multiplexing circuits 10 and 11, an FP generation circuit 12, and a control device 13. Multiplexing circuits 10, 1
1, data of the multiplexed frames (A) and (B) are input and output as multiplexed frames (E) and (F), respectively. In the FP generation circuit 12, the frame pulse (FP) of the multiplexed frames (A) and (B)
And a control signal (C) from the control device 13 to generate a multiplexed frame pulse and send the multiplexed FP (D) to the multiplexing circuit 10. The control device 13 is a device that sends out a control signal for controlling generation of a frame pulse from the FP generation circuit 12.

FIG. 3 is a waveform chart showing the operation of the multiplexing device. First, when the multiplexed frame B is not mounted,
The phase of the multiplex FP (D) is determined only by the multiplexed frame A (shown in a period T1). That is, the control device 13 activates the control signal (C), whereby the FP generation circuit 12
Sends out a multiple FP (D). Here, the FP generation circuit 1
2 is set in advance to transmit a multiplexed FP (D) based on the start position of the multiplexed frame (at a fixed timing from the start position).

Next, when the multiplexed frame (B) is mounted, the control device 13 activates the control signal (C) again to change a new phase from the phases of the multiplexed frames (A) and (B). (Shown in a period T2). That is, the FP generation circuit 12 generates a multiplexed FP (D) based on the logical product of the multiplexed frames (A) and (B). As a result, multiple FP
(D) is generated based on the start position of the multiplexed frame (B) (at a fixed timing from the start position).

The multiplex FP (E) can make the multiplex FP (D) transparent or multiplex the multiplexed frame (A). Similarly, multiple FP
In (F), the multiplexed FP (E) can be made transparent, and the multiplexed frame (B) can be multiplexed.

[0008]

However, in the above-mentioned conventional multiplexing apparatus, the timing of the multiplex FP is fixedly set based on the leading position of the multiplexed frame. There was a case.
For example, when the multiplexed frame (B) is not mounted, the FP generation circuit 12 outputs the multiplexed FP using only the multiplexed frame (A).
Determine the timing of (D). However, when the multiplexed frame (B) is actually implemented, the timing of the multiplexed FP (D) must be later than the frame pulse of the multiplexed frame (B). Phase will not be determined.

Further, even if the phase is determined by aligning all the inputs, the phase (for example, in the above example, the multiplexed FP based on the frame pulse of the multiplexed frame (B))
(D) is determined in advance. And
Normally, this timing is determined based on the start position of the last FP so that even if each multiplexed frame is greatly shifted, the timing does not overlap with the timing of the next frame pulse. Therefore, when the deviation of each multiplexed frame is small, the phase has an unnecessary margin, and the ideal phase control is not always performed.

In view of the above, it has been desired to realize a phase control device of a multiplexing device that can determine an optimum phase according to the configuration of the device.

[0011]

The present invention employs the following structure to solve the above-mentioned problems. <Configuration of Claim 1> In a multiplexing apparatus for multiplexing a multiplexed frame via an elastic store memory, a multiplexed frame is multiplexed from the memory.
The chromatography beam a phase control device for controlling the phase for reading the multiplex frame, mosquitoes an address indicating the phase which the multiplex frame is input to the elastic store memories
And the write address counter and outputs the count, and the read address counter to output to count the address that indicates the phase of reading the elastic store memory or al multi-weight frame, and the address of the write address counter,
Compare the address of the read address counter and determine the difference .
A phase comparator for outputting a signal for controlling the phase for reading the multiplex frame, the read address counter Niso
And a control signal generator for outputting a control signal for setting a phase difference for increasing or decreasing the count value of the control signal.

<Description of Claim 1> The write address counter is a counter that indicates the timing of writing a multiplexed frame to the elastic store memory. In addition, the read address counter, elastic store an object to be multiple frames as multiple frame
This is a counter indicating the timing of reading from the memory.
The phase comparator is for determining the phase difference between these counters.

In such a configuration, the control signal generator controls the count value of the read address counter according to the control signal. For example, the count value is set to −1 by activating the control signal once. Thereby, the difference between the count values of the write address counter and the read address counter can be set to an arbitrary value.

As a result, the phase difference signal from the phase comparator can be set to an arbitrary value, so that an optimum phase can be selected according to the state of the device.

According to a second aspect of the present invention, there is provided a multiplexer for multiplexing frames to be multiplexed through a plurality of multiplexing circuits each having an elastic store memory. The multiplexing circuit includes a control device for monitoring and outputting a phase difference control signal so as to have a predetermined phase difference, and each multiplexing circuit counts an address indicating a phase at which the multiplexed frame is input to the elastic store memory. a write address counter for outputting Te, a read address counter and outputting the counted address indicating the phase of reading the multiplexed frame to be multiplexed frame from the elastic store memory, the address of the write address counter, the address of the read address counter compared to the signal for controlling the phase of the multiplex frame the difference And outputs the count value to a read address counter based on a phase difference control signal from the control device.
And a control signal generator for outputting a control signal for setting a phase difference for increasing or decreasing the number of signals.

<Explanation of Claim 2> According to a second aspect of the present invention, the phase control signal from the phase comparator according to the first aspect of the present invention is monitored and controlled by a control device so as to obtain an optimal phase difference. It was done.
That is, the control device monitors the phase difference of each multiplexing circuit,
It is determined whether these phase differences are desirable values based on a preset reference value. If the value is not the desired value, the multiplexing circuit is instructed to change the phase difference. For example, when it is determined that the phase margin is small, control is performed to increase the phase difference. The reference value of the control device can be set to an arbitrary value.

With such a configuration, the phase difference of the multiplexing device can be set to an optimum value.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. << Specific Example 1 >><Configuration> FIG. 1 is a configuration diagram showing a specific example 1 of a phase control device of a multiplexer according to the present invention. The device shown in the figure corresponds to the configuration in the multiplexing circuit 10 or 11 described in FIG. 2, and comprises a write address counter 1, a read address counter 2, a phase comparator 3, and a control signal generator 4.

The write address counter 1 is a counter for judging the phase of inputting the multiplexed frame pulse A1 (or B1) to an elastic store memory (not shown) in correspondence with an address, and its address value (I ) Is output to the phase comparator 3. Note that the multiplexed frame pulse A1 (or B1) corresponds to the frame pulse of the multiplexed frames (A) and (B) in FIG. The read address counter 2 is a counter for inputting a multiplexed FP and determining a phase (address value) for reading out the multiplexed frames (A) and (B) from an elastic store memory (not shown). (H) is output to the phase comparator 3. Here, the input multiplex F
P is the multiple FP (D) or (E) in FIG.
Alternatively, it corresponds to (F). The phase comparator 3 is a comparator that compares the address value of the write address counter 1 with the address value of the read address counter 2 and outputs the phase difference as a phase difference signal (J) for controlling the phase of the frame. . Further, the control signal generator 4 is a controller that generates a control signal (G) for controlling the address of the read address counter 2.

<Operation> FIG. 4 is a timing chart showing the operation of the first embodiment. The write address counter 1 outputs an address value (I) in synchronization with the multiplexed FP input (A1 or B1). The read address counter 2 outputs an address value (H) in synchronization with the multiplex FP input (D, E, or F). The phase comparator 3 compares the address value (I) with the address value (H) and outputs a phase difference signal (J).

On the other hand, a control signal (G) is output from the control signal generator 4 and is input to the read address counter 2. Here, when the control signal (G) becomes active,
The read address counter 2 is configured to stop counting up by one clock. Here, an example is shown in which, when the control signal (G) is input while the read address counter 2 is counting values from 0 to 5, the address value stops at "0".

Since the control signal (G) is sampled and differentiated in the cycle of the read address counter 2, an arbitrary number of address values (eg, inactive and then active) are repeatedly activated. H) can be subtracted. For example, the count up of the address value in the read address counter 2 is set to 3
To stop the clock, this result can be obtained by activating the control signal (G) three times.

<Effect> As described above, in the first embodiment, the writing of the multiplexed frame in the elastic store memory and the
Since the phase difference between the read and can be set to any value,
An optimum phase can be selected according to the state of the device.

<< Specific Example 2 >><Configuration> FIG. 5 is a configuration diagram of Specific Example 2. The device shown comprises multiplexing circuits 50 and 51 and a control device 52. Multiplexing circuit 5
Numerals 0 and 51 include the phase locked loop circuit of the specific example 1 and, similarly to the multiplexing circuit of FIG. 2, receive the multiplexed frame (A) and the multiplexed frame (B), respectively, and output the multiplexed frame. Is what you do. The control device 52 is connected to the multiplexing circuits 50 and 51 through the interfaces (M), (N),
(O) and (P) are connected through each multiplexing circuit 50,
It has a function of monitoring the phase difference signal output from the controller 51 and outputting a phase difference control signal so as to have a predetermined phase difference.

<Operation> FIG. 6 is a waveform diagram for explaining the operation of the second embodiment. First, in the multiplexing circuit 50, the multiplexed frame (A)
Are multiplexed to output a multiplexed frame (K). In the control device 52, when the phase of the multiplexing circuit 50 is controlled by the interface (O) , the phases of the multiplex frame (K) and the multiplex frame (L) are shifted backward.

Next, the control operation of the control device 52 will be described. FIG. 7 is a flowchart of the phase synchronization process of the control device 52. First, the control device 52 has an interface
The phase difference between the multiplexing circuits 50 and 51 is monitored via (M) and (N) (step S1). For example, the phase difference of the preceding multiplexing circuit 50 is “2” and the following multiplexing circuit 51
Is "1" (period T in FIG. 6).
1). Here, in the control device 52, both multiplexing circuits 50,
Considering the variation of the multiplexing circuit 51, when the minimum phase difference is "1", it is determined that the phase margin is small, and the phase of the multiplexing circuit 50 in the preceding stage is controlled (steps S2 and S3 and T in FIG. 6).
2). This criterion is set in advance, and can be set to an arbitrary value.

Thereafter, returning to step S1, it is confirmed that the phase difference of the preceding multiplexing circuit 50 is "3" and the phase difference of the succeeding multiplexing circuit 51 is "2" (T3 in FIG. 6).
), And determine whether the phase difference is sufficient (Step S)
2) If the phase difference is not sufficient, the process shifts to step S3 to control the multiplexing circuit 50 at the preceding stage again, and ends when it is determined that the phase difference is sufficient.

It is also assumed that the frame to be multiplexed (B) is not input to the subsequent multiplexing circuit 51. Here, if it is known that the phase of the multiplexed frame (A, B) is the same as the phase shown in FIG. 6, the control device 52 controls the multiplexing circuit 50 in the preceding stage. Set the phase difference to “3”. When the phase difference is read after the multiplexed frame (B) is input in this way, the phase difference of the multiplexing circuit 51 is “2”.

<Effects> As described above, in the second embodiment, the phase difference between the multiplexing circuits 50 and 51 is controlled while monitoring the phase difference between the multiplexing circuits 50 and 51. The phase difference of the device can be set to an optimal state. Further, even if the multiplexed frames are not aligned, if the phase of the multiplexed frame can be predicted in advance, the phase can be adjusted to an optimum phase in advance by controlling the counter.
Thereby, the operability and reliability of the multiplexer can be improved.

<< Usage Mode >> In each of the above-described specific examples, the configuration in which the multiplexing circuits 50 and 51 are connected in two stages has been described as the multiplexing device. A multiplexing device configured to multiplex a plurality of frames to be multiplexed by the multiplexing circuit.

In each of the above specific examples, an example of counter subtraction has been described as control of the read address counter 2.
A configuration in which a counter is added may be used. Further, in the specific example 2, the number of subtractions is set to a fixed number of -1. However, the number of these subtractions or additions can be freely set, for example, -2 every time the control signal G is input once. can do.

In the above specific example 2, the multiplexing circuit 50,
The timing at which the phase difference is read from 51 may be any timing such as a timing based on a multiplexed frame pulse or a timing created by the control device 52. The control device 52 can be arbitrarily selected to be configured by a logic circuit or a CPU and a program. Further, the control device 52 may be a remote control, for example, via a communication line.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a phase control device of a multiplexer according to Embodiment 1 of the present invention.

FIG. 2 is a configuration diagram of a conventional multiplexer.

FIG. 3 is a waveform diagram for explaining the operation of a conventional multiplexer.

FIG. 4 is a waveform diagram for explaining an operation of the phase control device of the multiplexer according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a multiplexer according to Embodiment 2 of the present invention.

FIG. 6 is a waveform diagram for explaining an operation of the multiplexer according to the second embodiment of the present invention.

FIG. 7 is a flowchart illustrating an operation of the multiplexer according to the second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 write address counter 2 read address counter 3 phase comparator 4 control signal generator 50, 51 multiplexing circuit 52 controller

Claims (2)

(57) [Claims] 1. A multiplexing apparatus for multiplexing through the object to be multiplexed frame elastic store memory, the main
Read the multiplexed frame from the memory as a multiplexed frame.
A write address counter for counting and outputting an address indicating a phase of the multiplexed frame input to the elastic store memory; compared with the read address counter Ru <br/> be outputted by counting an address indicating the phase of reading the previous Kio heavy frame from the stick store memory, the address of the write address counter, the address of the read address counter decrease and the phase comparator, the count value to the read address counter for outputting a signal for controlling the phase for reading the pre Kio <br/> heavy frame the difference
A control signal generator for outputting a control signal for setting a phase difference for causing a phase difference to be set . 2. A multiplexing apparatus for multiplexing frames to be multiplexed via a plurality of multiplexing circuits each having an elastic store memory, wherein a phase difference signal output from each of the multiplexing circuits is monitored, A control device that outputs a phase difference control signal so as to have a determined phase difference, wherein each of the multiplexing circuits counts an address indicating a phase at which the multiplexed frame is input to the elastic store memory. A write address counter to output, and an address indicating a phase for reading the multiplexed frame from the elastic store memory as a multiplexed frame.
A read address counter for counting and outputting the address of the write address counter, the control the difference by comparing the address of said read address counter as a signal for controlling the pre Kio <br/> phase heavy frame a phase comparator for outputting the device, based on the phase difference control signal from said control unit, to increase or decrease the count value to the read address counter
A control signal generator for outputting a control signal for setting a phase difference .