JPH11112456A - Bit buffer device for clock replacement - Google Patents

Abstract

PROBLEM TO BE SOLVED: To replace a clock signal without production of missing bits even when fluctuation takes place in a write clock or a read clock. SOLUTION: While write, read clocks WCK, RCK are still unstable, serial input data DIN are written in a buffer memory 10 based on a write address from a counter 20. In the case that data are read from the memory 10 based on a read address from a counter 30, a phase comparator circuit 40 quickly detects that a phase difference margin between the write and read addresses is insufficient and, e.g. a counter 30 is initialized to have a desired count.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method in which serial input data is sequentially written on a buffer memory in bit units by a write address, while data is sequentially read in bit units from the buffer memory by a read address. Related to the clock transfer bit buffer device, especially after turning on the power to the device and the PLL.
A clock transfer bit suitable for preventing bit loss due to fluctuations of either the write clock or the read clock immediately after the clock phase of either the write or the read becomes stable, such as after completion of phase synchronization pull-in. The present invention relates to a buffer device.

[0002]

2. Description of the Related Art Heretofore, a bit buffer device for clock transfer according to the prior art is disclosed in, for example,
FIG. 3 shows an example of its block configuration, and FIG. 4 shows an example of its operation. In these cases shown in FIGS. 3 and 4, the write clock WCK is counted up from the N (in this example, it is assumed that N = 8) binary write address counter 20, and the count value is written to the write address WAi. Are generated sequentially and sequentially. As described above, each time the write address WAi is generated from the N-ary write address counter 20, the serial write data DIN is temporarily written in the buffer memory 10 in bit units, so that the multiplexing circuit For 50, the parallel outputs REG1-REG8 are output.

On the other hand, an N-ary write address counter 20
In parallel with the generation of the write address WAi, the N-ary read address counter 30 counts up the read clock RCK, so that the count value is generated as the read address RAi to the multiplexing circuit 50. Has become. As a result, in parallel with the sequential writing of the serial write data DIN in the buffer memory 10 in bit units, the read address RAi from the N-ary read address counter 30 causes the multiplexing circuit 50 to sequentially select and read in bit units. Is what is being done. The multiplexed data D is output from the multiplexing circuit 50 as a selector by the sequential selective reading.
OUT is obtained.

[0006] In parallel with the above sequential writing and sequential selective reading, the phase comparison circuit 40 uses an address value ( In this example, the address phase difference between the specific write address WAi and the read address RAi whose “0” is assumed to be the same is always detected. Each time the address phase difference is detected as being less than the set value, the initial read address of the N-ary read address counter 30 is reset to “N / 2” by the initialization control signal RST from the phase comparison circuit 40. It is a thing.

[0005]

By the way, in the above-mentioned prior art, the write clock WCK and the read clock RC are set after a sufficient time has elapsed since the power-on.
K, even if the respective clock phases are in a stable state, the write address WAi and the read address RAi
In some cases, there may not be a phase difference margin greater than or equal to the set value. Therefore, if fluctuations (jitter) occur in any clock in such a state, for example, the read address RAi An abrupt change from “0” to “N / 2”, that is, as a result of temporarily not generating “1” to “N / 2-1” as the read address RAi, bit loss in the multiplexed data DOUT The occurrence is undeniable.

The above situation will be described in more detail. As shown in FIG. 5, in this example, the write addresses WAi,
It is assumed that the address phase difference between the read addresses RAi is always detected by focusing on the address value “0”. In addition, the write clock WCK and the read clock RCK change at the same timing, and the address phase difference when the phases of the clocks WCK and RCK are stable is 1 bit of the set value, and the write address WAi is “1”. 7 "and the read address RAi being" 0 ", assuming that no fluctuation occurs in any clock, the write address WAi and the read address RAi are respectively" It should be updated to "0" and "1". However, at this time, for example, if a phase delay fluctuation corresponding to the time Δt occurs in the read clock RCK, the write address WA may be instantaneous.
i and the read address RAi are both "0", which is the result of the determination from the phase comparison circuit 40 that the address phase difference is smaller than the set value. / 2 ".

SUMMARY OF THE INVENTION An object of the present invention is to generate a bit loss after the clock phases of a write clock and a read clock are in a stable state, even if any of the clocks fluctuates. It is an object of the present invention to provide a clock transfer bit buffer device having a configuration capable of performing clock transfer without any change.

[0008]

It is an object of the present invention to provide at least an N-ary write address counter which generates a count value as a write address by counting a write clock, and a read clock which follows the write clock. An N-ary read address counter that generates a count value as a read address by counting the data, and a buffer memory in which serial input data is sequentially written in bit units by the write address, while data is sequentially read in bit units by the read address. Before the preset time elapses from the time of power-on, a combination of a specific write address as one write address and a specific read address as each of a plurality of continuous read addresses, or a plurality of With the combination of the specific write address as each write address and the specific read address as one read address, after the elapse of the preset time, the specific write address as one write address and the specific read address as one read address In the state where the phase comparison of the write address and the read address is performed by each combination, the address phase difference between the N-ary write address counter and the N-ary read address counter becomes N each time the comparison result related to the phase match is obtained. This is achieved by providing a phase comparison circuit for initializing at least one of the N-ary write address counter and the N-ary read address counter so as to be reset to / 2.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described with reference to FIG. FIG. 1 shows a block configuration of an example of a clock transfer bit buffer device according to the present invention, and FIG. 2 shows an operation of an example on the device. As shown in FIG. What is shown in FIG. 3 is
A difference is found between the phase comparison circuit 40 and the circuit configuration in the vicinity thereof. That is, in the phase comparison circuit 40 of this example, before the lapse of the preset time from the power-on time, the combination of the specific write address as one write address and the specific read address as each of three consecutive read addresses Further, after the elapse of the preset time, writing is performed using a combination of the specific write address as one write address and the specific read address as one read address, and the phase comparison of the read addresses is performed. It is detected whether or not the phase difference margin between the write address and the read address is sufficient.

Here, the circuit configuration of the phase comparison circuit 40 and its vicinity and its operation will be described as follows. That is, when the power is turned on, the timer 60 starts counting the measurement clock TC which is independent of the write clock WCK and the read clock RCK.
Although K is counted, the time at which the timer 60 times out can be set as desired by an external expiration condition setting signal (time-up time setting count value). Before the timer 60 expires, it is considered that each of the write clock WCK and the read clock RCK is not yet in a stable state. However, before the timeout, as the specific read address passed through the selector 41, While the phase comparison is performed between each of the three consecutive read addresses and the one write address as the specific write address,
After the time-up, the time-up signal acts on the selector 41 as the switching signal OVER, so that 1 as the specific read address passed through the selector 41 is output.
The phase comparison is performed between the read address and the one write address as the specific write address.

Here, assuming that N = 8 and the address value of the specific write address is “0”, referring to FIG.
More specifically, before the timer 60 times out, the address values of the three consecutive read addresses are set as “7”, “0”, and “1”, respectively. 7 "," 0 ", and" 1 "are obtained from the selector 41 as a 3-bit width window, and are separated from the 1-bit width existence period of the address value" 0 "of the specific write address. The presence or absence of temporal overlap is detected. If even a slight temporal overlap is detected, it is determined that there is not enough phase difference margin between the write address WAi and the read address RAi, and the read address counter 30 sets the read address “ 4 "is forcibly initialized. On the other hand, timer 6
After the time-out of 0, the address value of the 1-read address is set as “0”. The existence section of this address value “0” is obtained from the selector 41 as a 1-bit width window, and then specified. The presence / absence of temporal overlap between the write address and the 1-bit width existing section of the address value “0” is detected.

Therefore, as can be seen from the above description, the write address WAi and the read address RAi
When there is no sufficient phase difference margin between them, this is immediately detected before the timer 60 times out, and the read address counter 30 is forcibly initialized to the read address “4”. The phase difference margin after the initialization can be secured sufficiently large irrespective of the fluctuation of each of the write clock WCK and the read clock RCK. It can be prevented.

In the above description, the phase of the read address RAi with respect to the write address WAi is controlled by initializing the read address counter 30 as necessary. Since the phase between WAi may be relatively controlled, the write address W
It is also possible to control the phase of Ai with respect to the read address RAi. That is, the write address counter 20 may be initialized and set as needed. However, instead of initializing one of them, both may be simultaneously initialized as desired.

[0014]

As described above, according to the first aspect, even after the clock phases of the write clock and the read clock are in a stable state, even if any one of the clocks fluctuates. Even if it occurs, clock transfer can be performed without causing bit loss.

[Brief description of the drawings]

FIG. 1 is a diagram showing a block configuration of an example of a clock transfer bit buffer device according to the present invention;

FIG. 2 is a diagram showing an operation in an example on the device;

FIG. 3 is a diagram showing a block configuration of an example of a clock transfer bit buffer device according to the related art;

FIG. 4 is a diagram showing an operation of an example on the device;

FIG. 5 is a diagram for explaining a defect on the device.

[Explanation of symbols]

10: buffer memory, 20: N-ary write address counter, 30 ... N-ary read address counter, 40 ...
Phase comparison circuit, 50 multiplexing circuit, 60 timer, 41
…selector

Claims (1)

[Claims] 1. A clock transfer bit wherein serial input data is sequentially written into a buffer memory in a bit unit by a write address, while data is sequentially read in a bit unit from the buffer memory by a read address. A buffer device,
An N-ary write address counter that generates a count value as a write address by counting a write clock, an N-ary read address counter that generates a count value as a read address by count of a read clock that follows the write clock, While the input data is sequentially written in bit units by the write address, a buffer memory in which data is sequentially read in bit units by the read address, and one write operation before the preset time elapses from the power-on time. A combination of a specific write address as an address and a specific read address as each of a plurality of continuous read addresses, or a specific write address and a read address as each of a plurality of continuous write addresses With a combination of a specific read address and, in the after the preset time, 1
Each time a comparison is made between a specific write address as a write address and a specific read address as one read address, and the phase comparison of the read addresses is performed, each time a comparison result related to phase matching is obtained, N-ary The N-ary write address counter is set so that the address phase difference between the write address counter and the N-ary read address counter is reset to N / 2.
And a phase comparison circuit for initializing at least one of the N-ary read address counters.