JP4285440B2 - Optical data link - Google Patents

Description

  The present invention relates to an optical data link for reproducing data from an optical signal in optical communication.

  An optical data link used as a receiving circuit in optical communication converts a received optical signal into an electrical signal, amplifies and identifies the electrical signal, removes fluctuations in voltage, and then converts the electrical signal to a clock. Some extract (retiming) a signal and perform data regeneration (regeneration) using the extracted clock signal to remove fluctuations in time. In the latter optical data link, the output signal is reproduced in this manner in this way, and jitter caused by transmission lines and devices is also removed.

  In general, many high-speed optical data links are provided with a synchronous reproduction circuit that performs retiming processing and regeneration processing. The characteristics required for this synchronized recovery circuit include high-speed synchronization pull-in in the phase-locked loop (PLL), ability to cope with variations in characteristics between devices, and low-frequency fluctuations such as delay time and frequency response on the transmission line. It is possible to cope with a signal with a wide mark ratio, a burst signal, a signal including a low frequency component, and the like.

  Among these, the response to the low-frequency fluctuation on the transmission line is particularly important for preventing data errors in optical communication in which a signal constantly flows. In order to cope with low-frequency fluctuations, it is necessary to widen the frequency synchronization range in the PLL and to reduce the jitter in the output from the synchronous reproduction circuit. However, when the frequency synchronization range is widened, it is difficult to reduce the jitter at the output because low frequency jitter cannot be distinguished from the original signal. Therefore, in general, it is difficult to achieve both widening the frequency synchronization range and reducing jitter at the output.

As conventional techniques for dealing with such low-frequency fluctuations, for example, PLL circuits described in Patent Documents 1 and 2 below are known. This PLL circuit includes a frequency difference detection circuit or a second PLL as means for correcting the clock signal extracted by the first PLL in order to widen the frequency synchronization range. Patent Document 3 below discloses a retiming circuit having a determination control circuit that optimizes the phase of a clock signal. Further, Patent Document 4 below discloses a PLL circuit that detects a change point density of an input signal and adjusts an output of a phase comparator according to the change point density. Patent Document 5 below discloses a data receiving circuit in which two PLL circuits having different frequency synchronization ranges are connected in series.
JP-A-11-55112 JP 11-55113 A JP 2003-318872 A Special republication WO01 / 041351 JP-A-5-327683

  In the PLL circuits described in Patent Documents 1 to 4, even if the input signal includes low frequency jitter, the low frequency jitter cannot be removed, and the output signal has low frequency jitter. It will be output in a state of being included. On the other hand, in the data receiving circuit described in Patent Document 5, since the frequency synchronization range of the second PLL circuit is narrower than that of the first PLL circuit, low frequency jitter in the output signal can be suppressed. . As a result, the data receiving circuit widens the frequency synchronization range and simultaneously suppresses low frequency jitter in the output signal.

  However, in the data receiving circuit, the phase difference between the clock signal extracted by the first PLL circuit and the clock signal extracted by the second PLL circuit is input due to the difference in response time of the PLL circuit. There is a drawback that a data error due to clock slip occurs when the signal has reached a half pulse width or more. For example, the response time of the first PLL circuit is 100 nsec, the response time of the second PLL circuit is 100 μsec, and a pulse signal having a pulse width of 0.9999 nsec and a pulse signal having a pulse width of 1.0001 nsec are input signals. Consider a signal sequence that appears alternately every 10,000. In this case, the first PLL circuit responds when 100 nsec elapses after the pulse width is switched from 0.9999 nsec to 1.0001 nsec, but the second PLL circuit is not responding at that time. Therefore, the interval of the clock signal extracted in the second PLL circuit is different from the interval in the second PLL circuit by 0.0002 nsec. When 2,500 pulses have elapsed in this state, the phase difference between the two circuits reaches 0.5 nsec, that is, more than ½ pulse width of the input signal, causing an error. In order to prevent such a clock slip, it is conceivable to shorten the response time of the second PLL circuit. However, in general, the same type of circuit has a trade-off relationship between the response time of the PLL circuit and the synchronization frequency width. Therefore, in order to reduce the low frequency jitter of the output signal, there is a limit to shortening the response time. is there.

  Therefore, the present invention has been made in view of such problems, and provides an optical data link that can reduce low-frequency jitter in an output signal and at the same time effectively prevent data errors due to clock slip. For the purpose.

In order to solve the above problems, an optical data link of the present invention converts an optical signal including a clock signal and a data signal into an electric signal, extracts the clock signal from the electric signal, and uses the clock signal to extract the clock signal. In the optical data link for reproducing the data signal, a first phase-locked loop (PLL) circuit that extracts the first clock signal from the electrical signal, and the first from the electrical signal in synchronization with the first clock signal A first data identification circuit that generates an output signal; a data holding unit that holds the first output signal in synchronization with the first clock signal; and a frequency synchronization range that is narrower than that of the first PLL circuit. And a second PLL circuit that extracts the second clock signal from the first clock signal or the electric signal, and the first output signal is output from the data holding unit in synchronization with the second clock signal. Is Desa see, characterized in that it comprises a second data identification circuit for generating a second output signal in synchronization with the second clock signal based on the first output signal read from the data holding unit further .

In this optical data link, after the first clock signal is extracted by the first PLL circuit having a wide frequency synchronization range based on the electrical signal converted from the optical signal, the electrical signal or the first Based on the clock signal, the second clock signal is extracted by the second PLL circuit having a narrow frequency synchronization range, and the data signal is reproduced from the electrical signal in synchronization with the second clock signal. Therefore, the frequency synchronization range is widened by the first PLL circuit, and at the same time, low frequency jitter in the output signal is reduced by the second PLL circuit. Further, in the data holding unit, the first output signal generated based on the first clock signal by the first data identification circuit is held in synchronization with the first clock signal and held in the first data signal. The output signal is read in synchronization with the second clock signal. As a result, even if the phase difference between the clock signals increases due to the difference in response time between the two PLL circuits, the output signal from the previous PLL circuit is output in synchronization with the second clock signal. Clock slip can be prevented. In general, in reading from the data holding unit, the delay time of the signal changes slightly depending on the read address, and this may cause the occurrence of jitter. If provided, the occurrence of jitter in the output circuit can be suppressed without being influenced by the characteristics of the data holding unit.

  The first PLL circuit also preferably receives the reference clock signal from the second PLL circuit. In this way, even if the first PLL circuit is a PLL circuit that requires a reference clock, the reference clock source in the first PLL circuit is not required, so the circuit scale of the first PLL circuit is reduced. Can be small.

  The data holding unit divides and holds the first output signal and the first output signal in one of the plurality of buffer units in synchronization with the first clock signal. It is also preferable to have a data writing circuit for inputting in a predetermined order and a data reading circuit for outputting in a predetermined order from one of the plurality of buffer units in synchronization with the second clock signal. With such a configuration, after each data string of data output from the first data identification circuit is divided and input to the buffer unit, each data unit is synchronized with the second clock signal from each buffer unit. By outputting the data string, an output signal synchronized with the second clock signal can be obtained.

  The data holding unit outputs a first counter that counts the first clock signal, a second counter that counts the second clock signal, and a difference between the outputs of the first counter and the second counter. And an address setting unit that receives the first output signal, shifts the input first output signal in synchronization with the first clock signal, and synchronizes with the second clock signal by the address setting unit. It is preferable to have a shift register that outputs the selected bit.

  In this case, each data string of the first output signal output from the first data identification circuit is sequentially stored in the shift register, and the data string is read from the shift register in synchronization with the second clock signal. Generate an output signal. At this time, by selecting the data string to be read according to the difference between the count numbers of the first and second clock signals, occurrence of clock slip at the time of reading can be prevented.

  In addition, it is preferable to further include a monitoring circuit that outputs an alarm signal when the difference between the outputs of the first counter and the second counter exceeds a predetermined range. By providing such a monitoring circuit, a notification is given in advance when the data holding unit catches up with reading or when the writing process is earlier than the reading process and data is lost. Can do.

  It is also preferable that the second PLL circuit brings the frequency of the second clock signal close to the frequency of the first clock signal when an alarm signal is output. In this way, loss of data in the data buffer and occurrence of clock slip can be prevented in advance.

  It is also preferable that the data holding unit reads the first output signal in synchronization with the first clock signal when the alarm signal is output. In this case, since the positional relationship between the writing position and the reading position in the data holding unit is held, loss of data in the data buffer can be reliably prevented.

  According to the optical data link of the present invention, low frequency jitter in the output signal can be reduced, and at the same time, data error due to clock slip can be effectively prevented.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of an optical data link according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted.

[First Embodiment]
FIG. 1 is a diagram showing a configuration of an optical data link according to the first embodiment of the present invention. The optical data link 1 shown in the figure converts an optical signal input from the transmission line side into an electrical signal, extracts a clock signal from the electrical signal, and uses the extracted clock signal to generate a data signal from the electrical signal. It is a module that performs playback.

The optical data link 1 includes a light receiving element such as a photodiode and a current-voltage conversion circuit, and includes an optical receiving unit 2 that converts the optical signal O _in into an electric signal S _in corresponding to the intensity thereof, and a synchronous reproduction circuit 3. ing. The synchronous reproduction circuit 3 includes a first phase-locked loop (PLL) circuit 4 that extracts the clock signal CL ₁ from the electric signal S _in including the clock signal and the data signal, and the electric signal S _in synchronization with the clock signal CL _1. a first data identification circuit 5 that generates an output signals _{S 1} from the _in, and the second PLL circuit 6 further for extracting a clock signal CL ₂ from the clock signal CL _1, the output signals _{S 1,} the clock signal CL ₂ a FIFO data buffer (data holding section) 7 for outputting as the output signal _{S 2} of synchronized, the second data identification circuit 8 for reproducing the data signal in synchronization with the clock signal CL ₂ based on the output signal _{S 2,} FIFO The address monitoring circuit 9 monitors the state of the data buffer 7 and an AND circuit 10. Hereinafter, each component of the synchronous reproduction circuit 3 will be described in detail.

The first and second PLL circuits 4 and 6 extract a clock signal that defines the timing for identifying (reproducing data) the pulse signal included in the electric signal from the input electric signal. The first PLL circuit 4 includes a phase detection circuit 11 that generates a voltage signal corresponding to the phase difference between the electrical signal S _in and the clock signal CL ₁ , a filter circuit 12 that removes a high-frequency component of the voltage signal, and a filter circuit 12 includes a VCO (Voltage Controlled Oscillator) circuit 13 that changes the transmission frequency in accordance with a voltage signal from 12 (see FIG. 2). The configuration of the second PLL circuit 6 will be described later.

Specifically, the first PLL circuit 4 extracts the clock signal CL ₁ from the electric signal _{S in} output from the light receiving element 2, the second PLL circuit 6, a clock signal CL ₂ from the clock signal CL ₁ Extract further. In this case, the first PLL circuit 4 is utilized by receiving the clock signal CL ₂ from the second PLL circuit 6, the frequency spectrum is a sharp clock signal CL _2, as a reference clock source for the clock extraction To do. Here, the frequency synchronization range of the second PLL circuit 6 is set narrower than that of the first PLL circuit 4, and as a result, the response time of the clock extraction processing of the second PLL circuit 6 is the first It is longer than the response time of the PLL circuit 4. Therefore, even if the clock signal CL ₁ contains low frequency jitter, the clock signal CL ₂ will be output in the state where the low-frequency jitter has been removed.

The first data identification circuit 5 generates the output signal S ₁ by reproducing the data signal of the electric signal S _in based on the clock signal CL ₁ . That is, the first data identification circuit 5 identifies the data bit by comparing the level of the electric signal S _in with a predetermined threshold _in accordance with the timing of the clock signal CL ₁ and at the same time, the pulse corresponding to the data bit. Play the signal. The first data identification circuit 5 outputs the output signal S ₁ synchronized with the clock signal CL ₁ by continuously reproducing the data signal in this way.

FIFO data buffer 7, the output signals _{S 1,} and holds in synchronization with the clock signal CL _1, and outputs synchronization with the output signals _{S 1} held in the clock signal CL ₂ as an output signal _{S 2.} As shown in FIG. 3, the FIFO data buffer 7 includes a data writing circuit 15, a data holding circuit 16, and a data reading circuit 17. The data holding circuit 16 is a memory element that holds a data bit represented by the output signal S ₁ by a predetermined bit length. When receiving the output signal S ₁ , the data writing circuit 15 identifies the data bit from the output signal S ₁ in synchronization with the clock signal CL ₁ , and then writes the identified data bit in the data holding circuit 16. Data read circuit 17, the data bits written to the data holding circuit 16, read out in synchronism with the clock signal CL ₂ in a first-in first-out (FIFO) method. With such a configuration, the FIFO data buffer 7 generates an output signal S ₂ that is a continuation of a pulse signal synchronized with the clock signal CL ₂ .

  FIG. 4 is a diagram showing the configuration of the FIFO data buffer 7 in more detail. As shown in the figure, the data writing circuit 15 and the data reading circuit 17 are each composed of an input side switch unit 18 and an output side switch unit 20, and the data holding circuit 16 includes a plurality of 1-bit buffer units. 19.

Input switch unit 18 has an input terminal 21 to the output signal S ₁ is input, and a plurality of output terminals 22 connected in 1-bit buffer 19 and the one-to-one. Input switch unit 18 is configured to receive at all times a clock signal CL _1, by in synchronism with timing of the clock signal CL ₁ switches the connection between the input terminal 21 and output terminal 22, a plurality of 1-bit buffer The output signal S ₁ is input to one of 19 in a predetermined order. The order for inputting the output signals S ₁ is appropriately set, for example, it is set as input in order from above for 1-bit buffer section 19 shown in FIG.

The output-side switch unit 20 includes a plurality of input terminals 23 connected to the 1-bit buffer 19 in a one-to-one, and an output terminal 24 to the output signal S ₂ is outputted. The output-side switch unit 20 is configured to receive at all times a clock signal CL _2, by switching the connection between the input terminal 23 and output terminal 24 in synchronization with the clock signal CL _2, a plurality of 1-bit buffer 19 Data is sequentially read from one of them in accordance with the input order by the input side switch unit 18.

As shown in FIG. 5, the 1-bit buffer unit 19 includes a first D flip-flop (DFF) circuit 27 and a second DFF circuit 28 connected in series to the first DFF circuit 27. Yes. When the output signal S ₁ is input to the first DFF circuit 27 from the input side switch unit 18, the clock signal CL ₁ is simultaneously pulled in, and when the clock signal CL ₂ is pulled into the second DFF circuit 28. At the same time, the output side switch unit 20 is connected. In the first DFF circuit 27, the output signal S ₁ is given as “D input”, the clock signal CL ₁ is given as “CLOCK input”, and “Q output” is sent to the second DFF circuit 28. . In the second DFF circuit 28, the output of the first DFF circuit 27 is given as “D input”, the clock signal CL ₂ is given as “CLOCK input”, and “Q output” is given to the output side switch unit 20. It has been sent out.

With this configuration, 1 bit buffer unit 19 holds by dividing one bit of data bits in the input signals S ₁ at generation timing of the clock signal CL _1, holding at the timing of generation of the clock signal CL ₂ Output data bits as pulse signals. Further, by the cooperation of the input-side switch unit 18, the output-side switch unit 20, and the 1-bit buffer unit 19, the data bits divided and held in each 1-bit buffer unit 19 are stored in the clock signal CL _2. It is combined into an output signal S ₂ synchronized with. At this time, the data bits held in the plurality of 1-bit buffer units 19 are synthesized by the output side switch unit 20 in the order of input from the input side switch unit 18.

Returning to FIG. 1, the second data identification circuit 8 generates the output signal (second output signal) S _out by reproducing the data signal of the output signal S ₂ in synchronization with the clock signal CL ₂ . That is, the second data identification circuit 8, in accordance with the timing of the clock signal CL _2, and at the same time identify the data bit by comparing the level of the output signal S ₂ with a predetermined threshold value, corresponding to the data bit pulse Play the signal. When the low frequency jitter in the output signal S ₂ from the FIFO data buffer 7 is sufficiently small and the level of the output signal S ₂ is sufficiently large, the output signal S ₂ is used as the final output signal of the optical data link 1. Therefore, the second data identification circuit 8 may be omitted.

The address monitoring circuit 9 monitors the write destination address and the read destination address of the data holding circuit 16, and outputs an alarm signal to the outside when the positional deviation between both addresses exceeds a predetermined range. For example, the data holding circuit 16 includes N (N is an integer of 2 or more) 1-bit buffer units 19, and K ₁ , K _{2 ,.} (K ₁ , K ₂ ,..., K _N are assumed to be integers satisfying K ₁ <K ₂ <... <K _N ). The input-side switch 18, in descending or ascending order of address, it is assumed to input the output signals S ₁ to 1 bit buffer unit 19. In this case, the address monitoring circuit 9 monitors a write destination address K _W at the current input switching unit 18, the read address K _R in the current output-side switching unit 20. The address monitoring circuit 9, the deviation of the position of the write destination address K _W and the read address K _R is calculated by taking the difference between the two addresses, the deviation of the calculated position exceeds a preset value In this case, the alarm signal ALM is output to the outside in the ON state.

AND circuit 10 receives the alarm signal ALM output from the address monitoring circuit 9, receives the permission signal _{U in} from the outside. The permission signal U _in is input by a user from an external input device or the like, and is a signal that can distinguish between an on state and an off state based on a voltage level. Further, AND circuit 10, after identifying the state of the alarm signal ALM and state of enabling signal _{U in,} performs an AND operation on their state, to the second PLL circuit 6 an operation result as an automatic correction signal _{S a} Send it out. For example, the alarm signal ALM is "on", permission signal _{U in} the case of "on", "on" automatic correction signal _{S a} state is sent.

As shown in FIG. 6, the second PLL circuit 6 includes a frequency detection circuit 34, a voltage conversion circuit, a phase detection circuit 31, a filter circuit 32, and a VCO circuit 33, which are the same components as the first PLL circuit 4. A device 35 and a switch 36 are further provided. The frequency detection circuit 34 receives the clock signal CL ₁ from the first PLL circuit 4 and also receives the clock signal CL ₂ from the VCO circuit 33. The frequency detection circuit 34 outputs the level of the voltage signal corresponding to the frequency difference between the clock signal CL ₁ and the clock signal CL _2. The voltage converter 35 converts the level of the voltage signal output from the frequency detection circuit 34 to k times. The voltage converter 35 may add an offset voltage to the voltage signal output from the frequency detection circuit 34. The voltage signal output from the voltage converter 35 in this way is added to the voltage signal output from the filter circuit 32 via the switch 36, whereby the VCO circuit 33 is used as a voltage signal for controlling the oscillation frequency. Is input. In this case, the switch 36, when the automatic correction signal _{S a} from the AND circuit 10 is "ON" state, and transmits signals from the voltage converter 35 to the VCO circuit 33. With the configuration of the second PLL circuit 6 as described above, when the automatic correction signal _Sa is in the “on” state, the frequency of the clock signal CL ₂ that is the oscillation frequency of the VCO circuit 33 is the frequency of the clock signal CL ₁ . It is controlled to approach. Here, the output of the frequency detection circuit 34 can be output both at the top and bottom with a specific voltage as the center. When there is no frequency difference between the first PLL circuit 4 and the second PLL circuit 6, the frequency detection circuit 34 outputs this specific voltage, and a voltage higher than this specific voltage according to the sign of the frequency difference. Alternatively, a low voltage is output.

  The second PLL circuit 6 includes the frequency detection circuit 34. However, when the first PLL circuit 4 includes a function equivalent to the frequency detection circuit 34, the second PLL circuit 6 is provided. The frequency detection circuit 34 in FIG.

  The operational effects of the optical data link 1 described above will be described.

In the optical data link 1, based on the converted electric signal S _in the optical signal O _in, after the first clock signal CL ₁ is extracted by the wide first PLL circuit 4 frequency synchronization range, the The second clock signal CL ₂ is extracted by the second PLL circuit 6 having a narrow frequency synchronization range based on the _one clock signal CL ₁ , and the data signal S _in the electric signal S _in is synchronized with the clock signal CL _{2. out} is played back. Therefore, at the same time frequency synchronization range is wider by a first PLL circuit 4, the low-frequency jitter can be reduced in the output signal S _out by the second PLL circuit 6. Further, in the data writing circuit 15, the first output signal S ₁ generated based on the clock signal CL ₁ by the first data identification circuit 5 is sent to the data holding circuit 16 as the first clock signal CL ₁ . The data is written in synchronism, and the data read circuit 17 reads the data in the data holding circuit 16 in synchronism with the _second clock signal CL2. Specifically, in the FIFO data buffer 7, each data string of the output signal S ₁ output from the first data identification circuit 5 is divided and input to the 1-bit buffer unit 19. to output the respective data strings in synchronization with the bit buffer 19 to the clock signal CL _2. As a result, even if the phase difference between the clock signals CL ₁ and CL ₂ is increased due to the response times of the PLL circuits 4 and 6 being different, the output signal from the PLL circuit 4 in the previous stage is output to the second in the FIFO data buffer 7. of than is output in synchronization with the clock signal CL _2, it is possible to prevent the clock slips of data reproduction.

In general, in reading from the data holding circuit 16, the signal delay time slightly changes depending on the read address, and this may cause the occurrence of jitter. Therefore, the occurrence of jitter in the output signal S _out can be suppressed without being influenced by the characteristics of the data holding circuit 16 in the FIFO data buffer 7.

Further, the optical data link 1 includes the address monitoring circuit 9 so that the data holding circuit 16 can catch up with the read destination address or the write process is earlier than the read process and data is lost. In such a case, the user can be notified in advance. Further, the second PLL circuit 6, when the alarm signal from the address monitoring circuit 9 is outputted, since the operation of the second frequency of the clock signal CL ₂ so as to approach to the first frequency of the clock signal CL ₁ The loss of data in the FIFO data buffer 7 and the occurrence of clock slip during data reproduction can be prevented in advance.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 7 is a diagram showing a configuration of an optical data link 51 according to the second embodiment of the present invention. In the optical data link 51 according to the present embodiment, the configuration of the FIFO data buffer is different from that of the first embodiment.

FIG. 8 shows the configuration of the FIFO data buffer 57 of FIG. 7 in detail. As shown in the drawing, FIFO data buffer 57 is composed of a register unit 61a for holding a data string in the output signal S _1, the shift register control circuit 61b for shifting the data string is held in the register unit 61a The shift register 61 includes a switch unit 63 that selectively outputs a data string held in the shift register 61, and an output control unit 64 that controls the output of the data string in the switch unit 63.

Register unit 61a, which memory unit 68 for storing data of one bit is formed by a plurality of rows arranged, it is for storing a data sequence represented by the output signals S ₁ by one bit. Shift register control circuit 61b is configured to receive the clock signal CL _1, after identifying the data bits of the output signals S ₁ in accordance with the timing of the clock signal CL _1, the data bits, the most significant (Figure of the register unit 61a 8 is controlled so as to be written in the memory unit 68 on the input side. At this time, the shift register control circuit 61 b shifts the respective data strings held in all the memory units 68 of the register unit 61 a toward the adjacent memory units 68 in the input direction. In this case, the shift register control circuit 61b is a data bit of the output signals S ₁ may be written into the least significant register unit 61a.

Switch unit 63 has an output terminal 70 for outputting a plurality of input terminals 69 which are connected to each of the memory unit 68 of the register unit 61a output signal S _2, the control of the output control section 64, a clock signal in synchronization with the CL ₂ switches connection between the input terminal 69 and output terminal 70 in a one-to-one. In this way, the switch unit 63 selectively outputs a specific column in the data column of the register unit 61a.

The output control unit 64 includes two clock counters 65 and 66 and an address setting unit 67. The clock counter 65 receives the clock signal CL _1, counts the count Ct ₁ of the clock signal CL ₁ to the current from a predetermined timing. The clock counter 66 receives a clock signal CL _2, counts the count Ct ₂ clock signal CL ₂ to the current from the one time with the clock counter 65.

The address setting unit 67 calculates a difference between the count number Ct ₁ output from the clock counter 65 and the count number Ct ₂ output from the clock counter 66 in synchronization with the clock signal CL ₂ and outputs the difference to the switch unit 63. To do. As a result, the address setting unit 67 performs control so as to switch the input terminal 69 connected to the output terminal 70 according to the calculated difference. As a result, the data string read from the register unit 61a is moved toward the upper column or the lower column. More specifically, the address setting unit 67 connects the switch unit 63 when the count number Ct ₁ is larger than the count number Ct ₂ and the data string writing speed needs to be higher than the reading speed. Then, the shift register 61 is moved in the reading direction (right direction in FIG. 8). On the other hand, when the count number Ct ₁ is smaller than the count number Ct _{2 and} it is necessary to make the data string writing speed slower than the reading speed, the connection of the switch unit 63 is reverse to the reading direction of the shift register 61. (Move leftward in FIG. 8). At this time, the address setting unit 67 increases or decreases the amount of movement from the default position of the connection position of the input terminal 69 according to the absolute value of the difference between the count number Ct ₁ and the count number Ct ₂ .

The address monitoring circuit 59 monitors the difference between the count number Ct ₁ and the count number Ct ₂ in the address setting unit 67 and outputs an alarm signal ALM to the outside when the difference exceeds a predetermined range.

According to the optical data link 51 described above, each data string in the output signal S ₁ outputted from the first data identification circuit 5, in synchronism with sequentially stored in the shift register 61, the clock signal CL ₂ shift It generates an output signal S ₂ by reading the data string from the register 61. At this time, the data sequence read by the shift register 61 is selected in accordance with the difference between the count numbers Ct ₁ and Ct ₂ of the first and second clock signals CL ₁ and CL ₂ , thereby reducing the clock slip at the time of reading. Occurrence can be prevented.

Hereinafter, the effect of preventing clock slip in the optical data link 51 will be described more specifically. When the data capacity of the shift register 61 in the FIFO data buffer 57 is N bits and the data interval in the output signal S ₁ is T ₀ , theoretically, the accumulation of low frequency jitter, that is, the clock signal CL ₁ and the clock signal if the phase difference between CL ₂ is smaller than MT _0/2, it is possible to prevent the occurrence of clock slips. In contrast, in the conventional optical data link without a FIFO data buffer 57, clock slip when accumulation of low-frequency jitter is greater than T _0/2 occurs. This means that the optical data link 51 can withstand the influence of low-frequency jitter having a frequency 1 / M times the same amplitude as an optical data link that does not include the FIFO data buffer 57.

Actually, the rise time and fall time of the electrical signal processed by the optical data link 51 are not zero, and the settling time of the D flip-flop built in the data identification circuits 5 and 8 is not zero. Therefore, in the optical data link without a FIFO data buffer _{57, T 0/2-T} a (T a _{is, 0 <T a <T 0} /2 a is a positive number) withstand the low frequency jitter to size When used, the optical data link 51, so that the withstand low frequency jitter magnitude of up to MT _{0/2-T a.} As a result, in reality, the optical data link 51 can withstand the influence of low-frequency jitter having a frequency equal to or less than 1 / M times the same amplitude as an optical data link that does not include the FIFO data buffer 57. .

In addition, this invention is not limited to embodiment mentioned above. For example, the clock signal CL ₁ generated by the first PLL circuit 4 is input to the second PLL circuit 6, but the electric signal S _in is input to the second PLL circuit 6. Also good. However, the clock signal CL ₁ are the narrowband than the electrical signal S _in, better to perform clock extraction using the clock signal CL ₁ is more efficient. In addition, when 0 or 1 continues _in the data of the input signal S _in , it is advantageous to perform clock extraction using the clock signal CL ₁ because the second PLL circuit 6 can operate stably. .

The optical data links ₁ and 51 operate so as to read out the data string from the FIFO data buffers 7 and 57 in synchronization with the clock signal CL ₁ when the alarm signal ALM is output from the address monitoring circuits 9 and 59. May be.

9, when the output of the alarm signal ALM, is a diagram illustrating a configuration of an optical data link 81 in the case of a read operation of the FIFO data buffer 57 to perform on the basis of the clock signal CL _1. Similar to the first PLL circuit 4, the second PLL circuit 86 includes a phase detection circuit, a filter circuit, and a VCO circuit. The clock signal CL ₂ output from the second PLL circuit 86 is sent to the data reading circuit 17 (see FIG. 3) of the FIFO data buffer 57 via the switch unit 87. Switch unit 87 is configured to receive an alarm signal ALM from the address monitoring circuit 59, the clock signal CL from the clock signal CL ₁ and the second PLL circuit 86 from the first PLL circuit 4 according to the state of the alarm signal ALM ₂ is selectively sent to the data reading circuit 17. That is, the switch unit 87, if the alarm signal ALM is "ON" state, and sends the clock signal CL ₁ to the data read circuit 17, when the alarm signal ALM is "off" state, the data clock signal CL ₂ The data is sent to the reading circuit 17. The address setting unit 67 of the FIFO data buffer 57 uses the read address when the alarm signal ALM transits from the “on” state to the “off” state, and the address when the alarm signal ALM transits to the “on” state immediately before. If the read address is changed to an address close to the default position, it is more preferable because data reading is performed stably.

Thus, data read circuit 17, when the alarm signal ALM is "ON" state, operates to synchronously from the data holding circuit 16 with the clock signal CL ₁ reads data. As a result, the positional relationship between the write destination address and the read destination address in the data holding circuit 16 is held, so that loss of data in the FIFO data buffer 7 can be reliably prevented.

It is a figure which shows the structure of the optical data link which is 1st Embodiment of this invention. It is a figure which shows the structure of the 1st PLL circuit of FIG. It is a figure which shows the structure of the FIFO data buffer of FIG. FIG. 4 is a diagram showing the configuration of the FIFO data buffer of FIG. 3 in more detail. FIG. 5 is a diagram illustrating a configuration of a 1-bit buffer unit in FIG. 4. FIG. 2 is a diagram illustrating a configuration of a second PLL circuit in FIG. 1. It is a figure which shows the structure of the optical data link which is 2nd Embodiment of this invention. It is a figure which shows the structure of the FIFO data buffer of FIG. It is a figure which shows the structure of the optical data link which is a modification of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,51,81 ... Optical data link, 2 ... Light receiving element, 3 ... Synchronous reproduction circuit, 4 ... 1st PLL circuit, 5 ... 1st data identification circuit, 6,86 ... 2nd PLL circuit, 7, 57 ... FIFO data buffer (data holding unit), 8 ... second data identification circuit, 9, 59 ... address monitoring circuit, 15 ... data writing circuit, 16 ... data holding circuit, 17 ... data reading circuit, 18 ... input Side switch section (data writing circuit), 19... 1-bit buffer section, 20... Output side switch section (data reading circuit), 61... Shift register, 65 ... clock counter (first counter), 66. (Second counter), 67 ... address setting unit, ALM ... alarm signal, CL ₁ ... first clock signal, CL ₂ ... second clock signal, O _in ... optical signal, S _in ... electrical signal, S ₁ ... first output signal, S _out ... second output signal.

Claims (7)

In an optical data link that converts an optical signal including a clock signal and a data signal into an electrical signal, extracts the clock signal from the electrical signal, and regenerates the data signal from the electrical signal using the clock signal ,
A first phase-locked loop (PLL) circuit that extracts a first clock signal from the electrical signal;
A first data identification circuit for generating a first output signal from the electrical signal in synchronization with the first clock signal;
A data holding unit for holding the first output signal in synchronization with the first clock signal;
A frequency synchronization range set to be narrower than that of the first PLL circuit, and a second PLL circuit that extracts a second clock signal from the first clock signal or the electrical signal,
The first output signal is read from the data holding unit in synchronization with the second clock signal ,
A second data identification circuit that generates a second output signal in synchronization with the second clock signal based on the first output signal read from the data holding unit;
An optical data link characterized by that. The first PLL circuit receives a reference clock signal from the second PLL circuit;
The optical data link according to claim 1 . A plurality of buffer units for dividing and holding the first output signal;
A data writing circuit for inputting the first output signal to one of the plurality of buffer units in a predetermined order in synchronization with the first clock signal;
A data read circuit for outputting the data from one of the plurality of buffer units in the predetermined order in synchronization with the second clock signal;
The optical data link of claim 1 or 2, characterized in that. The data holding unit
A first counter for counting the first clock signal;
A second counter for counting the second clock signal;
An address setting unit for outputting a difference between outputs of the first counter and the second counter;
The first output signal is input, the input first output signal is shifted in synchronization with the first clock signal, and is selected by the address setting unit in synchronization with the second clock signal. A shift register that outputs the selected bits,
The optical data link according to claim 1 or 2 , characterized by comprising: A monitoring circuit that outputs an alarm signal when a difference between outputs of the first counter and the second counter exceeds a predetermined range;
5. The optical data link according to claim 4, wherein: The second PLL circuit brings the frequency of the second clock signal close to the frequency of the first clock signal when the alarm signal is output.
6. The optical data link according to claim 5, wherein: The data holding unit reads the first output signal in synchronization with the first clock signal when the alarm signal is output.
6. The optical data link according to claim 5, wherein:

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