CN111817726A - Serial system - Google Patents

Abstract

A serial system includes a logical physical layer and an electrical physical layer. The logical physical layer provides a first clock and parallel data. The electrical physical layer provides a second clock, and comprises a clock phase tracking circuit and a transmitting end. The clock phase tracking circuit includes a shift register, a phase detection circuit, and a selection circuit. The shift register samples the parallel data according to a first clock to generate first sample data, second sample data and third sample data. The phase detection circuit generates a detection signal according to the phase difference between the first clock and the second clock. The selection circuit selects one set from the first sample data, the second sample data, and the third sample data as output data in accordance with the detection signal. The transmitting end serializes the output data to generate serial data.

Description

Serial system

Technical Field

The present invention relates to a serial system.

Background

Generally, a serial system includes a logical Physical Layer (LPHY) and an Electrical Physical Layer (EPHY). When the operation clocks of the logical physical layer and the electrical physical layer are not synchronized, the electrical physical layer cannot recognize the data output by the logical physical layer.

Disclosure of Invention

The invention provides a serial system, which comprises a logical physical layer and an electrical physical layer. The logical physical layer provides a first clock and parallel data. The electrical physical layer provides a second clock, and comprises a clock phase tracking circuit and a transmitting end. The clock phase tracking circuit includes a shift register, a phase detection circuit, and a selection circuit. The shift register samples the parallel data according to a first clock to generate first sample data, second sample data and third sample data. The phase detection circuit generates a detection signal according to a phase difference between the first clock and the second clock. The selection circuit selects one set from the first sample data, the second sample data, and the third sample data as output data in accordance with the detection signal. The transmitting end serializes the output data to generate serial data.

Drawings

FIG. 1 is a schematic diagram of a serial system of the present invention.

FIG. 2 is a schematic diagram of the interior of a channel of the electro-physical layer of the present invention.

FIG. 3A is a block diagram of a shift register according to an embodiment of the present invention.

FIG. 3B is a diagram of another exemplary embodiment of a shift register unit.

FIG. 4A is a schematic diagram of a selection circuit according to an embodiment of the present invention.

FIG. 4B is a schematic diagram of a selection circuit according to an embodiment of the present invention.

Fig. 5A is a schematic diagram of a phase detection circuit according to an embodiment of the invention.

Fig. 5B is a schematic diagram of another exemplary embodiment of a phase detection circuit.

Fig. 6A is a schematic diagram of a phase frequency detector according to an embodiment of the invention.

Fig. 6B is a schematic operation diagram of the phase frequency detector of fig. 6A.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The arrangement of the components in the embodiments is for illustration and not for limiting the invention. In the embodiments, the reference numerals are partially repeated to simplify the description, and do not indicate the relationship between the different embodiments.

FIG. 1 is a diagram of a serial system 100 according to the present invention. As shown, the serial system 100 includes a logical Physical L (logical Physical L)an eye; LPHY)110 and an Electrical Physical Layer (Electrical Physical Layer; EPHY) 120. The logical physical layer 110 comprises a controller 111 and a plurality of channels LL₁～LL_n. Controller 111 passes through channel LL₁～LL_nIn communication with the electrophysical layer 120. Among other things, the serial system shown in fig. 1 may be used in a Serializer/Deserializer (SerDes) system to perform serial operations in the Serializer/Deserializer system.

By channel LL₁For example, channel LL₁Output clock LP₁CLK and parallel data LP₁_TCAD<19:0>To the electrophysical layer 120. In one possible embodiment, the clock LP₁CLK and parallel data LP₁_TCAD<19:0>Is generated by the controller 111. In addition, channel LL₁Also receives a clock EP from the Electrical physical layer 120₁CLK and parallel data EP₁_RCAD<19:0>. In one possible embodiment, the controller 111 is based on the clock EP₁CLK and parallel data EP₁_RCAD<19:0>And (6) acting.

In the present embodiment, the EPL 120 includes a Phase-Locked Loop (PLL) 121 and a plurality of channels EL₁～EL_n. The phase-locked loop 121 is used to generate the clock PLL _ CLK to the channel EL₁～EL_n。

Channel EL₁～EL_nReceiving clock LP₁_CLK～LP_nCLK and parallel data LP₁_TCAD<19:0>～LP_n_TCAD<19:0>. In the present embodiment, the channel EL₁～EL_nFurther providing a clock EP₁_CLK～EP_nCLK and parallel data EP₁_RCAD<19:0>～EP_n_RCAD<19:0>Channel LL to logical physical layer 110₁～LL_n。

In the present embodiment, the channel EL₁～EL_nEach of which comprises a frequency divider, a clock phase tracking circuit, a transmitting end and a receiving end. By channel EL₁For example, channel EL₁Including a divider 125, a clock phase tracking circuit 122, a transmit terminal 123, and a receive terminal 124. Frequency divider 125Dividing the clock PLL _ CLK to generate the clock TPLL₁CLK. Clock phase tracking circuit 122 based on clock TPLL₁CLK, sample parallel data LP₁_TCAD<19:0>To generate a plurality of sampling data, and according to a clock TPLL₁CLK and LP clocks₁The CLK phase difference, selects appropriate sample data and outputs the selected sample data to the transmitting terminal 123.

According to an embodiment of the invention, the clock TPLL depends on the architecture of the serializing circuit in the initiator 123₁CLK and LP clocks₁CLK is different in most serial systems, but clock TPLL₁Frequency of CLK and clock LP₁The frequency of CLK is the same. When i1 channels use the same communication protocol, the clock LP₁_CLK～LP_i1CLK is the same, clock TPLL₁_CLK～TPLL_i1CLK is the same, clock LP₁_CLK～LP_i1CLK and clock TPLL₁_CLK～TPLL_i1The frequency of CLK is the same. When (i2-i1) of the remaining lanes employ another communication protocol, the clock LP_i1_CLK～LP_i2CLK is the same as the clock LP₁_CLK～LP_i1Different from CLK, clock TPLL_i1_CLK～TPLL_i2CLK is the same as the clock TPLL₁_CLK～TPLL_i1Different from CLK, clock LP_i1_CLK～LP_i2CLK and clock TPLL_i1_CLK～TPLL_i2CLK has the same frequency as the clock LP₁_CLK～LP_iThe frequency of CLK is different, wherein 1<＝i1<＝i2<＝n。

The transmitter 123 serializes the sampled data output from the clock phase tracking circuit 122 according to the clock PLL _ CLK to generate and output serial data SO₁And _DTto external circuitry (not shown). In one possible embodiment, the serial data SO₁DT is a differential signal. The present invention does not limit the circuit architecture of the transmitting terminal 123. Any circuit that can serialize parallel data into serial data can be used as the transmitting terminal 123.

The receiving end 124 receives the serial data SI₁And (4) DT. Serial data SI₁DT may be a differential signal. In one possible embodiment, the receiver 124 processesSerial data SI₁DT for slave serial data SI₁Recover clock and data from _ DT. In this example, the receiving end 124 provides parallel data EP₁_RCAD<19:0>And a clock EP₁CLK to channel LL₁. The present invention does not limit the circuit architecture of the receiver 124. Any circuit that can convert serial data into parallel data can be used as the receiving end 124.

FIG. 2 is a schematic diagram of the interior of a channel of the electro-physical layer of the present invention. Channel EL due to the Electrical physical layer 120₁～EL_nThe same structure, so FIG. 2 only shows the channel EL₁The internal architecture of (1). As shown, channel EL₁Including a divider 125, a clock phase tracking circuit 122, a transmit terminal 123, and a receive terminal 124.

The clock phase tracking circuit 122 includes a shift register 211, a phase detection circuit 212, and a selection circuit 213. The shift register 211 is based on the clock LP₁CLK sample parallel data LP₁_TCAD<19:0>For generating sampling data SP₁<19:0>～SP₃<19:0>. The phase detection circuit 212 is based on the clock LP₁CLK and clock TPLL₁The phase difference of CLK generates the detection signal SD. The selection circuit 213 selects the sampling data SP based on the detection signal SD₁<19:0>～SP₃<19:0>As output data OT<19:0>。

For example, when the clock LP₁CLK and clock TPLL₁When the phase difference of CLK is within a predetermined range, the phase detecting circuit 212 instructs the selecting circuit 213 to select the sampling data SP according to the detection signal SD₂<19:0>. Therefore, the selection circuit 213 samples the data SP₂<19:0>As output data OT<19:0>. However, when the clock LP₁CLK leads clock TPLL₁CLK, and clock LP₁CLK and clock TPLL₁When the phase difference between CLK is not within the predetermined range, the phase detecting circuit 212 instructs the selecting circuit 213 to select the sampling data SP based on the detection signal SD₃<19:0>As output data OT<19:0>. In other embodiments, the clock LP₁CLK hysteresisIn clock TPLL₁CLK, and clock LP₁CLK and clock TPLL₁When the phase difference between CLK is not within a predetermined range, the phase detecting circuit 212 instructs the selecting circuit 213 to select the sampling data SP based on the detection signal SD₁<19:0>As output data OT<19:0>。

Since the phase detection circuit 212 is based on the clock LP₁CLK and clock TPLL₁The CLK phase difference instructs the selection circuit 213 to select the proper sampling data, so that the data output by the phy 120 can be ensured to be synchronized with the clock PLL CLK. Furthermore, the clock phase tracking circuit 122 is open-circuited, so that the stability is high and the circuit design is simple. In addition, the clock phase tracking circuit 122 has the advantages of low power consumption and small area.

The present invention does not limit the number of sets of sample data. In the present embodiment, the number of groups of sample data is odd. The present invention is not limited to the structure of the phase detection circuit 212. Any circuit that can generate an appropriate detection signal SD and select appropriate sample data from a plurality of sets of sample data by the selection circuit 213 may be used as the phase detection circuit 212.

For example, when the shift register 211 generates three sets of sampling data, such as SP₁<19:0>～SP₃<19:0>The detection signal SD generated by the phase detection circuit 212 includes at least two detection signals UP and DN, so that the selection circuit 213 selects the sample data SP from the two detection signals UP and DN of the detection signal SD₁<19:0>～SP₃<19:0>One group of which is selected as the output data OT<19:0>. In another embodiment, when the shift register 211 may generate five sets of sampling data (e.g., SP)₁<19:0>～SP₅<19:0>). In this case, the phase detection circuit 212 needs to generate at least four detection signals UP₁、UP₂、DN₁、DN₂The detection signal SD of (1). In this example, the selection circuit 213 selects four detection signals UP according to the detection signal SD₁、UP₂、DN₁、DN₂From sampled data SP₁<19:0>～SP₅<19:0>Selection inSelect a set as output data OT<19:0>. Wherein, the detection signal SD includes (k-1) detection signals, k is the number of groups of sampling data generated by the shift register 211, and the (k-1) detection signals include UP₁～UP_(k-1)/2And DN₁～DN_(k-1)/2。

The transmit terminal 123 includes a serializing circuit 221 and a driver 222. The serializing circuit 221 serializes the parallel data LP according to the clock PLL _ CLK₁_TCAD<19:0>For generating serial data SO₁And (4) DT. The present invention does not limit the architecture of the serializing circuit 221. In one embodiment, the serializing circuit 221 includes at least one data receiving unit (not shown). In this case, the data receiving unit may be a buffer (buffer), a D flip-flop, a register (register), or a latch (latch).

In this example, the driver 222 is used for outputting the serial data SO according to the clock PLL _ CLK₁And (4) DT is provided for an external circuit. In addition, in other embodiments, driver 222 modulates the signal to meet the electrical specifications required by a particular protocol, such as to meet the requirements of the particular protocol for output impedance, signal amplitude, slew rate, equalization granularity, equalization amplitude, ESD specifications, short circuit current, and so forth.

The receiving end 124 includes a receiver 231 and a Clock Data Recovery (CDR) circuit 232. The receiver 231 receives the serial data SI₁And (4) DT. Clock data recovery circuit 232 analyzes serial data SI₁DT for slave serial data SI₁And recovering the clock and the data in the _ DT. In the present embodiment, the clock data recovery circuit 232 generates the clock EP₁CLK and parallel data EP₁_RCAD<19:0>。

Fig. 3A is a shift register 211 according to an embodiment of the invention. As shown in FIG. 3A, the shift register 211 includes a shift buffer unit SR₀～SR₁₉. The number of shift register units is not limited in the present invention. In the present embodiment, LP is performed due to parallel data₁_TCAD<19:0>Has 20 bits (bit), so the shift register 211 correspondingly includes 20 shift buffer units.

Shift buffer unit SR₀～SR₁₉According to the clock LP₁CLK sample parallel data LP₁_TCAD<19:0>. For example, the shift register unit SR₀Sampling parallel data LP₁_TCAD<19:0>Least Significant Bit (LSB) of the bit line, the next called bit data LP₁_TCAD<0>. Shift buffer unit SR₁Sampling parallel data LP₁_TCAD<19:0>Is adjacent to the least significant bit, the lower nominal bit data LP₁_TCAD<1>. Shift buffer unit SR₁₈Sampling parallel data LP₁_TCAD<19:0>Adjacent bit of Most Significant Bit (MSB), referred to as bit data LP₁_TCAD<18>. Shift buffer unit SR₁₉Sampling parallel data LP₁_TCAD<19:0>Is most significant bit of, the next called bit data LP₁_TCAD<19>。

Due to the shift of the buffer unit SR₀～SR₁₉The circuit structures of the shift register units are the same, so that only the shift register unit SR is described below₀The circuit architecture of (1). In the embodiment, the shift buffer unit SR₀ Including sampling circuits 310, 320, and 330. The invention is not limited to the shift buffer unit SR₀The number of middle sampling circuits. When the number of the sampling circuits is larger, the shift buffer unit SR₀The more sampled data may be provided. In one embodiment, the number of sampling circuits of each shift buffer unit is an odd number.

The sampling circuit 310 is based on the clock LP₁First falling edge of CLK, sample bit data LP₁_TCAD<0>For generating the first data Q1. In the present embodiment, the first data Q1 is used as the sampling data SP₁<19:0>Is the least significant bit SP of₁<0>. The present invention is not limited to the architecture of the sampling circuit 310. In the present embodiment, the sampling circuit 310 includes a D flip-flop 311. In this example, data input terminal D of D flip-flop 311 receives bit data LP₁_TCAD<0>The clock input Clk of the D flip-flop 311 receives the clock LP₁CLK, the output terminal Q of the D flip-flop 311 outputs the first data Q1.

The sampling circuit 320 is based on the clock LP₁The first rising edge of CLK samples the first data Q1 to generate the second data Q2, which isThe first rising edge is the first rising edge after the first falling edge. In the present embodiment, the second data Q2 is used as the sampling data SP₂<19:0>Is the least significant bit SP of₂<0>. The present invention is not limited to the architecture of the sampling circuit 320. In the present embodiment, the sampling circuit 320 includes a D flip-flop 321. In this example, the data input terminal D of the D flip-flop 321 receives the first data Q1, and the clock input terminal Clk of the D flip-flop 321 receives the clock LP₁CLK, the output terminal Q of the D flip-flop 321 outputs the second data Q2. In other embodiments, sampling circuit 320 includes a latch 321.

The sampling circuit 330 is based on the clock LP₁The second data Q2 is sampled at a second falling edge of CLK to generate third data Q3, wherein the second falling edge is the first falling edge after the first rising edge. In the present embodiment, the third data Q3 is used as the sampling data SP₃<19:0>Is the least significant bit SP of₃<0>. The present invention is not limited to the architecture of the sampling circuit 330. In the present embodiment, the sampling circuit 330 includes a D flip-flop 331. In this example, the data input terminal D of the D flip-flop 331 receives the second data Q2, and the clock input terminal Clk of the D flip-flop 331 receives the clock LP₁CLK, the output terminal Q of the D flip-flop 331 outputs the third data Q3. In other embodiments, sampling circuit 320 includes a latch 331.

In the embodiment, the shift buffer unit SR₀～SR₁₉The respectively generated first data Q1 constitute sample data SP₁<19:0>And the second data Q2 constitute the sample data SP₂<19:0>And the third data Q3 constitute the sample data SP₃<19:0>. In other embodiments, the reset terminal R of the D flip- flops 311, 321, and 331 receives the reset signal RST. In this example, when the reset signal RST is enabled, the output terminals Q of the D flip- flops 311, 321, and 331 return to a predetermined level, for example, a low level.

FIG. 3B is a diagram of a shift register unit according to another embodiment of the present invention. Due to the shift of the buffer unit SR₀～SR₁₉The structures are the same, so FIG. 3B only shows the shift register unit SR₀. In this embodimentIn, shift buffer unit SR₀Sampling circuits 340 and 350 are also included.

The sampling circuit 340 is based on the clock LP₁The third data Q3 is sampled at a second rising edge of CLK to generate a fourth data Q4, wherein the second rising edge is the first rising edge after the second falling edge. In the present embodiment, the fourth data Q4 is the sample data SP₄<19:0>Is the least significant bit SP of₄<0>. The present invention is not limited to the architecture of the sampling circuit 324. In the present embodiment, the sampling circuit 340 includes a D flip-flop 341. In this example, the data input terminal D of the D flip-flop 341 receives the third data Q3, and the clock input terminal Clk of the D flip-flop 341 receives the clock LP₁CLK, output Q of D flip-flop 341 provides fourth data Q4. In other embodiments, sampling circuit 340 includes latch 341.

The sampling circuit 350 operates according to the clock LP₁The fourth data Q4 is sampled at a third falling edge of CLK to generate fifth data Q5, wherein the third falling edge is the first falling edge after the second rising edge. In the present embodiment, the fifth data Q5 is the sampling data SP₅<19:0>Is the least significant bit SP of₅<0>. The present invention is not limited to the architecture of the sampling circuit 350. In the present embodiment, the sampling circuit 350 includes a D flip-flop 351. In this example, the data input terminal D of the D flip-flop 351 receives the fourth data Q4, and the clock input terminal Clk of the D flip-flop 351 receives the clock LP₁CLK, the output Q of the D flip-flop 351 provides the fifth data Q5. In other embodiments, sampling circuit 350 includes latch 351.

Fig. 4A is a schematic diagram of a selection circuit 213A according to an embodiment of the invention. As shown in FIG. 4A, the selection circuit 213A includes a decoder 410A and a selector SA₀～SA₁₉. The decoder 410A decodes the detection signal SD to generate the switching signal SWA. In the present embodiment, the detection signal SD includes detection signals UP and DN.

Selector SA₀～SA₁₉Selecting the sampling data SP according to the switching signal SWA₁<19:0>～SP₃<19:0>As output data OT<19:0>. The invention is not limited to the selector SA₀～SA₁₉The kind of (2). In the present embodiment, the selector SA₀～SA₁₉Is a multiplexer. The number of selectors is not limited in the present invention. In one possible embodiment, the number of selectors and the parallel data LP₁_TCAD<19:0>The number of bits is the same.

The invention is not limited to the selector SA₀～SA₁₉How to select the sample data SP according to the switching signal SWA₁<19:0>～SP₃<19:0>One group of (1). In one possible embodiment, when the detection signals UP and DN are both at the first level, e.g. both low levels, it indicates that the clock LP₁CLK and clock TPLL₁The phase difference between CLK is within a predetermined range. Thus, decoder 410A commands selector SA by switching signal SWA₀～SA₁₉Selecting sample data SP₂<19:0>As output data OT<19:0>. When the UP signal is at the second level, e.g., high level, and the DN signal is at the first level, e.g., low level, it indicates the LP clock₁CLK lags behind clock TPLL₁CLK and clock LP₁CLK and clock TPLL₁The phase difference between CLK is not within a preset range. Accordingly, the decoder 410A commands the selector SA according to the switching signal SWA₀～SA₁₉Selecting sample data SP₁<19:0>As output data OT<19:0>. When the UP signal is at a first level, e.g., low level, and the DN signal is at a second level, e.g., high level, it indicates the LP clock₁CLK may lead clock TPLL₁CLK and clock LP₁CLK and clock TPLL₁The phase difference between CLK is not within a preset range. Accordingly, the decoder 410A commands the selector SA according to the switching signal SWA₀～SA₁₉Selecting sample data SP₃<19:0>As output data OT<19:0>。

Fig. 4B is a schematic diagram of another possible embodiment 213B of the selection circuit 213 of the present invention. As shown in FIG. 4B, the selection circuit 213A includes a decoder 410B and a selector SB₀～SB₁₉. In the present embodiment, it is preferred that,the detection signal SD includes a detection signal UP₁、UP₂、DN₁And DN₂. In this example, decoder 410B is responsive to detection signal UP₁、UP₂、DN₁And DN₂Adjusts the switching signal SWB to select the sampling data SP₁<19:0>～SP₅<19:0>As output data OT<19:0>. Specifically, when the signal UP is detected₁、UP₂、DN₁、DN₂All at a first level, e.g., low level, decoder 410B commands selector SB in response to switching signal SWB₀～SB₁₉Selecting sample data SP₃<19:0>As output data OT<19:0>. When detecting signal UP₁、UP₂、DN₁、DN₂Middle detection signal UP₁When the decoder 410B is at the second level, e.g. high, and the rest are at the first level, e.g. low, the selector SB is commanded according to the switching signal SWB₀～SB₁₉Selecting sample data SP₂<19:0>As output data OT<19:0>. When detecting signal UP₁、UP₂、DN₁、DN₂Middle detection signal UP₁、UP₂When the decoder 410B is at the second level, e.g. high, and the rest are at the first level, e.g. low, the selector SB is commanded according to the switching signal SWB₀～SB₁₉Selecting sample data SP₁<19:0>As output data OT<19:0>. When detecting signal UP₁、UP₂、DN₁、DN₂Middle detection signal DN₁When the decoder 410B is at the second level, e.g. high, and the rest are at the first level, e.g. low, the selector SB is commanded according to the switching signal SWB₀～SB₁₉Selecting sample data SP₄<19:0>As output data OT<19:0>. When detecting signal UP₁、UP₂、DN₁、DN₂Middle detection signal DN₁、DN₂When the decoder 410B is at the second level, e.g. high, and the rest are at the first level, e.g. low, the selector SB is commanded according to the switching signal SWB₀～SB₁₉Selecting sample data SP₅<19:0>As output data OT<19:0>。

Fig. 5A is a schematic diagram of a phase detection circuit 212 according to an embodiment 212A of the invention. In the present embodiment, the phase detection circuit 212A includes a Phase Frequency Detector (PFD) 510A, a Low Pass Filter (LPF) 520A, a comparison circuit 530A, and a synchronization circuit 540A.

Phase frequency detector 510A detects clock LP₁CLK and clock TPLL₁A phase difference of CLK, and according to clock LP₁CLK and clock TPLL₁A phase difference of CLK to generate a pulse signal PS₁And PS₂. In one possible embodiment, the clock LP₁CLK and clock TPLL₁When the phase difference of CLK exceeds the linear range of phase frequency detector 510A, the pulse signal PS₁And PS₂Cannot reflect the clock TPLL₁CLK and LP clocks₁-the actual phase difference between CLK. In this case, a phase frequency detector with a higher linear range can be used, or the clock LP can be used₁CLK and clock TPLL₁And (4) dividing CLK frequency and detecting.

The present invention does not limit the kind of the phase frequency detector 510A. In one possible embodiment, the type of phase frequency detector 510A is related to the number of samples. For example, when the shift register 211 provides 3 sets of sample data, the linear range of the phase frequency detector 510A must be between-pi and + pi. When the shift register 211 provides 5 sets of sample data, the linear range of the phase frequency detector 510A must be between-2 pi and +2 pi. Wherein, when the number of the sampling data groups is k, the linear range of the phase frequency detector 510A must be between- (k-1) pi/2 to + (k-1) pi/2, and the linear range is such that the DC signal (hereinafter, the filtered signal FT) in the output signal of the phase frequency detector 510A₁And FT₂) Clock LP whose voltage can maintain continuous linearity₁CLK and clock TPLL₁Range of phase difference between CLK.

The low pass filter 520A filters the pulse signal PS₁And PS₂For generating a direct current filtered signal FT₁And FT₂. In this embodiment, the dc signal after filtering the high frequency signal, i.e. the filtered signal FT₁And FT₂And the pulse signal PS₁And PS₂Is proportional to the pulse width of (c), and also represents the clock LP₁CLK and clock TPLL₁The magnitude of the phase difference CLK.

The comparison circuit 530A will filter the signal FT₁Comparing with reference signal VREF to generate comparison result CP₁And the filtered signal FT is₂Comparing with reference signal VREF to generate comparison result CP₂. In the present embodiment, the comparing circuit 530A includes comparators 531 and 532. As shown in FIG. 5A, the inverting input of the comparator 531 receives the reference signal VREF, and the non-inverting input of the comparator 531 receives the filtered signal FT₁. The inverting input terminal of the comparator 532 receives the reference signal VREF, and the non-inverting input terminal of the comparator 532 receives the filtered signal FT₂。

Synchronization circuit 540A is based on clock TPLL₁CLK, synchronous comparison result CP₁And CP₂For generating a detection signal SD. In the present embodiment, the detection signal SD includes detection signals UP and DN. In this example, the detection signals UP and DN are used to represent the clock LP₁CLK and clock TPLL₁-phase difference between CLK. The present invention is not limited to the architecture of the synchronization circuit 540A. In one embodiment, the synchronization circuit 540A includes D flip- flops 541 and 542. In this example, D flip-flop 541 is based on clock TPLL₁CLK, sample comparison result CP₁For generating the detecting signal UP. D flip-flop 542 is based on clock TPLL₁CLK, sample comparison result CP₂For generating a detection signal DN.

In other embodiments, phase detection circuit 212A also includes voltage generation circuit 550A. The voltage generating circuit 550A is used for generating a reference signal VREF. In one possible embodiment, the reference signal VREF is approximately VDD of 1/4, where VDD is the operating voltage of phase frequency detector 510A.

Fig. 5B is a schematic diagram of another possible embodiment 212B of the phase detection circuit 212 according to the present invention. In the present embodiment, the detection signal SD generated by the phase detection circuit 212B has the detection signal UP₁、UP₂、DN₁And DN₂For selecting one of the five sets of sample data. As shown in fig. 5B, phase detection circuit 212B includes a phase frequency detector 510B, a low pass filter 520B, a comparison circuit 530B, and a synchronization circuit 540B. Since the characteristics of the phase frequency detector 510B and the low pass filter 520B are similar to those of the phase frequency detector 510A and the low pass filter 520A in fig. 5A, further description is omitted.

In the present embodiment, the comparison circuit 530B includes comparators 533 to 536. The inverting input terminal of the comparator 533 receives the reference signal VREF₁The non-inverting input of the comparator 533 receives the filtered signal FT₁The output terminal of the comparator 533 provides the comparison result CP₃. The inverting input of the comparator 534 receives the reference signal VREF₁The non-inverting input terminal of the comparator 534 receives the filtered signal FT₂The output of the comparator 534 provides the comparison result CP₄. The inverting input of the comparator 535 receives the reference signal VREF₂The non-inverting input of the comparator 535 receives the filtered signal FT₁The output of the comparator 535 provides the comparison result CP₅. The inverting input of comparator 536 receives the reference signal VREF₂The non-inverting input of comparator 536 receives the filtered signal FT₂The output of the comparator 536 provides the comparison result CP₆。

Synchronization circuit 540B is based on clock TPLL₁CLK, synchronous comparison result CP₃～CP₆For generating a detection signal SD. In the present embodiment, the detection signal SD includes the detection signal UP₁、UP₂、DN₁And DN₂. The present invention is not limited to the architecture of the synchronization circuit 540B. In one embodiment, the synchronization circuit 540B includes D flip-flops 543-546.

D flip-flop 543 according to clock TPLL₁CLK, sample comparison result CP₃For generating a detecting signal UP₁. D flip-flop 544 according to clock TPLL₁CLK, sample comparison result CP₄For generating a detection signal DN₁. D flip-flop 545 based on clock TPLL₁CLK, sample comparison result CP₅For generating a detection signalUP₂. D flip-flop 546 is based on clock TPLL₁CLK, sample comparison result CP₆For generating a detection signal DN₂。

In the present embodiment, the phase detection circuit 212B further includes a voltage generation circuit 550B. The voltage generating circuit 550B is used for generating a reference signal VREF₁And VREF₂. In one embodiment, the reference signal VREF₁VDD of about 1/4, and reference signal VREF₂And VDD of about 3/4, where VDD is the operating voltage of phase frequency detector 510B.

In other embodiments, the detection signal SD comprises more detection signals for selecting the appropriate sample data from more sample data. For example, when each shift buffer unit has 7 sampling circuits, the detection signal SD includes 6 detection signals. In this example, the voltage generation circuit provides 3 reference signals, where the first reference signal is VDD of 1/6, the second reference signal is 3/6, i.e., VDD of 1/2, and the third reference signal is VDD of 5/6. In another embodiment, when each shift buffer unit has 9 sampling circuits, the detection signal SD has 8 detection signals. In this example, the voltage generation circuit provides 4 reference signals, where the first reference signal is VDD of 1/8, the second reference signal is VDD of 3/8, the third reference signal is VDD of 5/8, and the fourth reference signal is VDD of 7/8. When the number of the sampling circuits is k, the shift buffer unit may generate k groups of sampling signals, where the detection signal SD includes (k-1) detection signals, and the voltage generation circuit is required to provide (k-1)/2 reference signals, where the reference signals VREF are sequentially taken as VDD of m/(k-1), where VDD is the operating voltage of the phase frequency detector 510B, and m is each odd number in the interval [1, k), which may also be expressed as m being 1, 3 … k-4, and k-2.

Fig. 6A is a schematic diagram of a phase frequency detector according to an embodiment of the invention. As shown, the phase frequency detector 600 includes a D flip-flop 610, a D flip-flop 620, and a logic gate 630. The data input terminal D of the D flip-flop 610 receives the operating voltage VDD, and the clock input terminal Clk of the D flip-flop 610 receives the clock LP₁CLK, output Q of D flip-flop 610 outputs pulse signal PS₁The reset terminal R of the D flip-flop 610 is coupled to a logicAn output of the edit gate 630. The data input terminal D of the D flip-flop 620 receives the operating voltage VDD, and the clock input terminal Clk of the D flip-flop 620 receives the clock TPLL₁CLK, output Q of D flip-flop 620 outputs pulse signal PS₂The reset terminal R of the D flip-flop 620 is coupled to the output terminal of the logic gate 630. The logic gate 630 receives the pulse signal PS₁And PS₂. In the present embodiment, the logic gate 630 is an AND gate (AND gate).

Fig. 6B is a waveform diagram of the phase frequency detector 600 of fig. 6A. When the clock LP₁When CLK rises from low to high, the pulse signal PS₁And goes high. When clock TPLL₁When CLK rises from low to high, the pulse signal PS₂And goes high. When the pulse signal PS₁And PS₂When high, the logic gate 630 resets the D flip- flops 610 and 620, so that the pulse signal PS is asserted₁And PS₂From high to low.

FIG. 6B shows clock TPLL₁CLK _ CLK is formed by LP₁LP in case of CLK _ Flip₁CLK leads clock TPLL₁CLK state. Pulse signal PS₁And a pulse signal PS₂The pulse width difference of (a) represents the clock LP₁CLK and clock TPLL₁-phase difference between CLK. For example, when the clock LP₁CLK and clock TPLL₁The larger the phase difference between CLK becomes, the pulse signal PS₁And a pulse signal PS₂The larger the difference in pulse width.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

While the invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented in hardware, software, or a combination of hardware and software. Therefore, the scope of the present invention is defined by the appended claims.

Claims (10)

1. A serial system, comprising:

a logical physical layer providing a first clock and parallel data; and

an electrical physical layer providing a second clock, comprising:

a clock phase tracking circuit comprising:

a shift register for sampling the parallel data according to the first clock to generate first, second and third sampling data;

a phase detection circuit for generating a detection signal according to a phase difference between the first clock and the second clock; and

a selection circuit for selecting one of the first sample data, the second sample data and the third sample data as output data according to the detection signal; and

the transmitting end serializes the output data to generate serial data.

2. The serial system of claim 1, wherein the selection circuit selects the second sampled data as the output data when the phase difference is within a preset range; when the first clock leads the second clock and the phase difference is not within the preset range, the selection circuit selects the third sampling data as the output data; when the first clock lags behind the second clock and the phase difference is not within the preset range, the selection circuit selects the first sampling data as the output data.

3. The serial system as recited in claim 1, wherein the shift register comprises a plurality of shift buffer units, each of the shift buffer units comprising a plurality of sampling circuits, the number of the plurality of sampling circuits being odd.

4. The serial system as recited in claim 3, wherein each of said shift register units comprises:

a first sampling circuit for sampling a bit of the parallel data according to a first falling edge of the first clock to generate first data;

a second sampling circuit for sampling the first data according to a first rising edge of the first clock to generate second data; and

a third sampling circuit for sampling the second data according to a second falling edge of the first clock to generate third data,

the first sample data includes a plurality of first data generated by the plurality of shift buffer units, the second sample data includes a plurality of second data generated by the plurality of shift buffer units, and the third sample data includes a plurality of third data generated by the plurality of shift buffer units.

5. The serial system of claim 4, wherein the first sampling circuit, the second sampling circuit, the third sampling circuit comprise flip-flops.

6. The serial system of claim 4, wherein the first sampling circuit comprises a flip-flop, and the second sampling circuit and the third sampling circuit comprise latches.

7. The serial system of claim 1, wherein the phase detection circuit comprises:

the phase frequency detector generates a first pulse signal and a second pulse signal according to the phase difference of the first clock and the second clock;

a low-pass filter for processing the first pulse signal and the second pulse signal to generate a first filtered signal and a second filtered signal;

a comparison circuit for comparing the first filtered signal with a reference signal to generate a first comparison result, and for comparing the second filtered signal with the reference signal to generate a second comparison result; and

and a synchronization circuit for synchronizing the first and second comparison results according to the second clock to generate the detection signal.

8. The serial system of claim 7, wherein the synchronization circuit comprises:

a first flip-flop, sampling the first comparison result according to the second clock, for generating a first detection signal; and

a second flip-flop for sampling the second comparison result according to the second clock to generate a second detection signal,

the detection signal includes the first detection signal and the second detection signal.

9. The serial system of claim 8, wherein the selection circuit comprises:

a decoder for decoding the detection signal to generate a switching signal; and

and the selector selects one group of the first sampling data, the second sampling data and the third sampling data as the output data according to the switching signal.

10. The serial system of claim 1, wherein the transmitting end comprises:

a serializing circuit for serializing the output data to generate the serial data; and

the driver is used for outputting the serial data.

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