JP3214544B2 - Planar optical waveguide - Google Patents

Planar optical waveguide

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Publication number
JP3214544B2
JP3214544B2 JP20505596A JP20505596A JP3214544B2 JP 3214544 B2 JP3214544 B2 JP 3214544B2 JP 20505596 A JP20505596 A JP 20505596A JP 20505596 A JP20505596 A JP 20505596A JP 3214544 B2 JP3214544 B2 JP 3214544B2
Authority
JP
Japan
Prior art keywords
core
substrate
optical waveguide
glass
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP20505596A
Other languages
Japanese (ja)
Other versions
JPH1048460A (en
Inventor
善典 日比野
靖之 井上
文明 塙
泰文 山田
元速 石井
雅弘 柳沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
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Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP20505596A priority Critical patent/JP3214544B2/en
Publication of JPH1048460A publication Critical patent/JPH1048460A/en
Application granted granted Critical
Publication of JP3214544B2 publication Critical patent/JP3214544B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、光ファイバもしく
は他の平面型光導波路と信頼性の高い接続を可能とする
平面型光導波路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar optical waveguide which enables a highly reliable connection with an optical fiber or another planar optical waveguide.

【0002】[0002]

【従来の技術】Siや石英等の平面基板上に石英系ガラ
ス導波路を形成し、平面型光回路(PLC)を構成する
研究開発が進んでいる。石英系ガラス導波路は屈折率の
高い矩形のコアと該コアを囲みかつ該コアよりも屈折率
がわずかに低いクラッドとからなり、石英系ガラス膜形
成技術及び反応性エッチング技術により作製される。P
LCを実際にシステムで使用するには、光信号を入出力
するために光ファイバと接続する必要がある。そして、
PLC−光ファイバ接続技術は低損失かつ高安定である
ことが要求される。
2. Description of the Related Art Research and development for forming a planar optical circuit (PLC) by forming a silica-based glass waveguide on a flat substrate such as Si or quartz are progressing. The quartz-based glass waveguide includes a rectangular core having a high refractive index and a clad surrounding the core and having a slightly lower refractive index than the core, and is manufactured by a quartz-based glass film forming technique and a reactive etching technique. P
In order to actually use an LC in a system, it is necessary to connect an optical fiber to input and output an optical signal. And
PLC-optical fiber connection technology is required to have low loss and high stability.

【0003】通常、PLCは多数の入出力ポートを有す
るため、多芯の光ファイバが接続される。このため、ガ
ラスブロックに多芯ファイバをUV接着剤で固定してフ
ァイバアレイを作製し、さらに該ファイバアレイをUV
接着剤でPLCと固定している。
Usually, a PLC has a large number of input / output ports, so that a multi-core optical fiber is connected. Therefore, a fiber array is manufactured by fixing a multi-core fiber to a glass block with a UV adhesive, and the fiber array is further UV-coated.
It is fixed to the PLC with an adhesive.

【0004】現在まで最も汎用性の高いPLC型スプリ
ッタの実用化では、PLCの両端を研磨し、同じく端面
を研磨した入出力ファイバ部品に接続していた。
Until now, the most versatile PLC type splitter has been put to practical use, in which both ends of the PLC are polished and connected to input / output fiber parts whose end faces are also polished.

【0005】図1は光ファイバを接続した従来のPLC
型スプリッタの構造を示す。図中、11はスプリッタ回
路(PLC)、12は入力用1芯ファイバ、13は出力
用8芯テープファイバ、14,15はファイバ固定用ガ
ラスブロック、16a,16b,17a,17bは接続
補強用ガラス板である。PLC本体のサイズは4×30
mm程度で、全体の長さは80mmである。
FIG. 1 shows a conventional PLC to which an optical fiber is connected.
1 shows the structure of a mold splitter. In the figure, 11 is a splitter circuit (PLC), 12 is a single-core fiber for input, 13 is an 8-core tape fiber for output, 14 and 15 are glass blocks for fixing fibers, and 16a, 16b, 17a and 17b are glass for connection reinforcement. It is a board. PLC body size is 4 × 30
mm, and the entire length is 80 mm.

【0006】具体的な接続は、前述した入力用1芯ファ
イバ12をガラスブロック14及びガラス板16aとと
もに、また、出力用8芯テープファイバ13をガラスブ
ロック15及びガラス板17aとともに、さらにまた、
PLC11をガラス板16b,17bとともに、その端
面を8度に研磨し、UV接着剤にて接続した。
More specifically, the input single-core fiber 12 is connected with the glass block 14 and the glass plate 16a, and the output 8-core tape fiber 13 is connected with the glass block 15 and the glass plate 17a.
The end face of the PLC 11, together with the glass plates 16b and 17b, was polished to 8 degrees and connected with a UV adhesive.

【0007】前述した接続法による回路では、(1)基
板切断による表面の荒れを研磨により平坦化することに
よって低損失なファイバ接続が可能、(2)研磨面の角
度を任意に設定できるので、例えば8度にすると反射減
衰量を大幅に低減することが可能、(3)平坦化により
接着強度を増加させることができ、PLC−光ファイバ
接続で高い信頼性を実現することが可能、という利点が
ある。
In the circuit by the connection method described above, (1) a low-loss fiber connection is possible by flattening the surface roughness by cutting the substrate by polishing, and (2) the angle of the polished surface can be set arbitrarily. For example, when the angle is set to 8 degrees, the return loss can be greatly reduced, (3) the bonding strength can be increased by flattening, and high reliability can be realized by PLC-optical fiber connection. There is.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、前述し
た回路では、PLC端面を研磨する際に研磨面のクラッ
ド(ガラス)層にクラックを生じるという欠点があっ
た。
However, the above-mentioned circuit has a disadvantage that cracks occur in the clad (glass) layer on the polished surface when the end face of the PLC is polished.

【0009】図2は研磨後のPLC端面を模式的に示す
ものである。図中、21はSi基板、22は下部クラッ
ド層、23は上部クラッド層、24はコアである。通
常、クラックはSi基板21に近い下部クラッド(ガラ
ス)層22に生じる。このクラックは接着材層に不均一
を生じさせ、長期信頼性を劣化させるとともに反射減衰
量等の光学特性も劣化させるという問題がある。
FIG. 2 schematically shows a PLC end face after polishing. In the figure, 21 is a Si substrate, 22 is a lower cladding layer, 23 is an upper cladding layer, and 24 is a core. Usually, cracks occur in the lower cladding (glass) layer 22 near the Si substrate 21. The cracks cause non-uniformity in the adhesive layer, deteriorating long-term reliability and deteriorating optical characteristics such as return loss.

【0010】以下、前述したクラックの原因と考えられ
るガラス層における内部応力について簡単に見積もる。
内部応力σは熱膨張係数の差で生じ、 σ∝(Tg−Tr)(αg −αSi) の関係がある。
Hereinafter, the internal stress in the glass layer which is considered to be the cause of the crack will be briefly estimated.
The internal stress σ generated in the difference in thermal expansion coefficient, a relationship of σα (Tg-Tr) (α g -α Si).

【0011】ここで、Tgはクラッド(ガラス)層のガ
ラス化温度、Trは室温、αg 及びαSiはそれぞれクラ
ッド(ガラス)層及びSi基板の熱膨張係数である。ま
た、図2に示すように、PLC断面において平面基板と
平行及び垂直な方向をそれぞれx及びy方向とすると、
応力と屈折率の関係は Δnx =C1 σx +C2 σy Δny =C1 σy +C2 σx で与えられる。
Here, Tg is the vitrification temperature of the cladding (glass) layer, Tr is room temperature, and α g and α Si are the thermal expansion coefficients of the cladding (glass) layer and the Si substrate, respectively. Further, as shown in FIG. 2, when the directions parallel and perpendicular to the plane substrate in the PLC cross section are x and y directions, respectively,
Relationship stress and refractive index is given by Δn x = C 1 σ x + C 2 σ y Δn y = C 1 σ y + C 2 σ x.

【0012】ここで、σx ,σy はそれぞれの方向の応
力、Δnx ,Δny はそれぞれの軸方向の応力による屈
折率変化、C1 及びC2 は光弾性係数であり、 C1 =−7.7×10-13 (Pa-1) C2 =−4.1×10-12 (Pa-1) の値を有する。
[0012] Here, σ x, σ y each direction of stress, Δn x, Δn y is the refractive index change due to each of the axial stresses, C 1 and C 2 are photoelastic coefficient, C 1 = −7.7 × 10 −13 (Pa −1 ) C 2 = −4.1 × 10 −12 (Pa −1 ).

【0013】また、σx とσy は、 σy =−κσx の関係(ポアソンの関係)がある。ここで、κ(=0.
17)はポアソン係数である。
Further, σ x and σ y have a relationship of σ y = −κσ x (Poisson's relationship). Here, κ (= 0.
17) is a Poisson coefficient.

【0014】前述した関係より Δny −Δnx =σx (−κC1 +C1 −C1 +κC2 ) =σx (1+κ)(C2 −C1 ) ……(1) が得られる。[0014] From the foregoing relationship Δn y -Δn x = σ x ( -κC 1 + C 1 -C 1 + κC 2) = σ x (1 + κ) (C 2 -C 1) ...... (1) is obtained.

【0015】一方、Si基板上の石英系光導波路におい
て厚さ30μm程度の下部クラッド層の場合、典型的な
複屈折率Bの値は、 B=nTM−nTE=nx −ny =4×10-4 ……(2) となる。
On the other hand, in the case of a lower clad layer having a thickness of about 30 μm in a quartz optical waveguide on a Si substrate, a typical value of the birefringence B is as follows: B = n TM −n TE = n x −n y = 4 × 10 −4 (2)

【0016】圧縮応力を一にとると、上記(1) ,(2) 式
より内部応力は、 σx =4×10-4/1.171×3.3×10-12 =1.0×108 Pa =0.1GPa となる。
If the compressive stress is taken to be unity, the internal stress is given by σ x = 4 × 10 −4 /1.171×3.3×10 −12 = 1.0 × according to the above equations (1) and (2). 10 8 Pa = 0.1 GPa.

【0017】上式より、クラッド(ガラス)層には0.
1GPa程度の圧縮応力が作用していることがわかる。
この値はクラッド層の厚さ及び組成に依存する。基本的
にはこの内部応力によりクラックが生じ、特にクラック
の形成は厚いクラッド(ガラス)層の周辺部で起き易い
ことが明らかにされている。これは周辺部で応力集中が
起き易いためと考えられる。
According to the above equation, the cladding (glass) layer has a thickness of 0.1 mm.
It can be seen that a compressive stress of about 1 GPa is acting.
This value depends on the thickness and composition of the cladding layer. It has been clarified that cracks basically occur due to this internal stress, and that crack formation is particularly likely to occur in the periphery of a thick clad (glass) layer. This is presumably because stress concentration easily occurs in the peripheral portion.

【0018】本発明の目的は、接続部でのクラック発生
を防止し、他の光導波路との信頼性の高い接続が可能な
平面型光導波路を提供することにある。
An object of the present invention is to provide a planar optical waveguide capable of preventing a crack from occurring at a connecting portion and enabling highly reliable connection with another optical waveguide.

【0019】[0019]

【課題を解決するための手段】前記課題を解決するた
め、本発明では、接続部におけるクラッド(ガラス)層
の厚さを不均一にする、具体的には、コア周辺を除いて
クラッドを薄くするか、コア周辺のみにクラッドを形成
することにより、導波構造を保ちつつコア周辺部の内部
応力を減少させる。
In order to solve the above-mentioned problems, according to the present invention, the thickness of the cladding (glass) layer at the connection portion is made non-uniform. Alternatively, by forming a clad only around the core, the internal stress around the core is reduced while maintaining the waveguide structure.

【0020】図3は本発明の平面型光導波路の基本的な
概念を示すもので、図中、31はSi基板、32は下部
クラッド層、33は上部クラッド層、34はコアであ
る。
FIG. 3 shows the basic concept of the planar optical waveguide of the present invention. In the figure, 31 is a Si substrate, 32 is a lower cladding layer, 33 is an upper cladding layer, and 34 is a core.

【0021】ここでは下部クラッド層32がコア31の
周辺のみで厚くなっているのが特徴である。応力の観点
からすると、コア下部のクラッドをなくせば、ほとんど
応力もなくなるが、導波構造もなくなってしまうので損
失が大きくなる。従って、コア周辺のクラッドをなくす
ことはできない。
Here, the characteristic is that the lower cladding layer 32 is thickened only around the core 31. From the viewpoint of stress, if there is no cladding under the core, almost no stress will be applied, but since there is no waveguide structure, loss will increase. Therefore, the cladding around the core cannot be eliminated.

【0022】そこで、本発明ではコアの断面積がPLC
全体の断面積に占める割合が小さいことを生かして、コ
ア周辺にのみクラッドを残し、その他の部分では下部ク
ラッド層をなくすか、薄くすることを特徴とする。これ
により、内部応力を大幅に減少させることができ、従っ
てクラックの発生がなくなり、長期安定性に優れたPL
C−ファイバ接続が可能になるとともに、その光学特性
も変化しない。
Therefore, in the present invention, the cross-sectional area of the core is PLC
Taking advantage of the small proportion of the entire cross-sectional area, the clad is left only around the core, and the lower clad layer is eliminated or thinned in other portions. As a result, the internal stress can be greatly reduced, so that the generation of cracks is eliminated, and the PL having excellent long-term stability is obtained.
While the C-fiber connection is possible, its optical properties do not change.

【0023】[0023]

【発明の実施の形態】図4は本発明の第1の実施の形態
を示すもので、ここでは石英系PLC1×8スプリッタ
回路の例を示す。図中、41はスプリッタ回路(PL
C)、42は導波路、43は入力側接続部、44は出力
側接続部である。
FIG. 4 shows a first embodiment of the present invention. Here, an example of a silica-based PLC 1 × 8 splitter circuit is shown. In the figure, reference numeral 41 denotes a splitter circuit (PL
C) and 42 are waveguides, 43 is an input side connection, and 44 is an output side connection.

【0024】また、図5は図4のa−a´線に沿う研磨
後の出力側接続部44の拡大端面図、図6は図4のb−
b´線に沿う拡大断面図である。図中、45はSi基
板、46は下部クラッド層、47は上部クラッド層、4
8はコアである。
FIG. 5 is an enlarged end view of the output side connection portion 44 after polishing along the line aa 'in FIG. 4, and FIG.
It is an expanded sectional view which follows a b 'line. In the figure, 45 is a Si substrate, 46 is a lower cladding layer, 47 is an upper cladding layer,
8 is a core.

【0025】図4乃至6に示す構造を作製するには、ま
ず、Si基板45にフォトリソグラフィでクラッド形状
をパターニングし、ウェットエッチングによりコア48
の下部に下部クラッド層を形成する部分を形成する。次
に、石英系ガラスからなる下部クラッド層46をFHD
法で堆積し、透明ガラス化する。この後、表面形状に凹
凸が生じるので、研磨により平坦化する。コア層を堆積
した後、マーカを用いてコア48のパターニング及びガ
ラスエッチングを行い、最後に上部クラッド層47を堆
積した。
In order to manufacture the structure shown in FIGS. 4 to 6, first, a clad shape is patterned on a Si substrate 45 by photolithography, and a core 48 is formed by wet etching.
A portion for forming a lower cladding layer is formed below the surface of the substrate. Next, the lower cladding layer 46 made of quartz glass is
It is deposited by the method and vitrified. Thereafter, the surface shape becomes uneven, so that it is flattened by polishing. After depositing the core layer, patterning and glass etching of the core 48 were performed using a marker, and finally the upper clad layer 47 was deposited.

【0026】作製した1×8スプリッタでは、出力側の
8ポートのピッチを0.25mmとし、入力側接続部4
3及び出力側接続部44の変形クラッド領域の幅を50
μm(コアを中心)、長さを2mm、コア直下のクラッ
ド層の厚さを15μmとした。作製したウェファを切断
し、研磨面には保護用にガラス板49をUV接着剤で固
定した。その後、図4のスプリッタ端面を通常の方法で
研磨した。研磨後の端面にはクラックは全く観測されな
かった。この結果より、本発明の有効性が確認された。
In the manufactured 1 × 8 splitter, the pitch of the eight ports on the output side was set to 0.25 mm, and
3 and the width of the deformed cladding region of the output side connection portion 44 is 50
μm (centered on the core), the length was 2 mm, and the thickness of the cladding layer immediately below the core was 15 μm. The produced wafer was cut, and a glass plate 49 was fixed on the polished surface with a UV adhesive for protection. Thereafter, the end face of the splitter shown in FIG. 4 was polished by an ordinary method. No crack was observed on the polished end face. From these results, the effectiveness of the present invention was confirmed.

【0027】また、本例ではスプリッタの光学特性も、
変形クラッド領域のない従来のスプリッタと同じであ
り、この点でも本発明の有効性が確認された。
In this embodiment, the optical characteristics of the splitter are
This is the same as a conventional splitter without a deformed cladding region, and the effectiveness of the present invention was also confirmed in this regard.

【0028】図7は本発明の第2の実施の形態を示すも
ので、ここでは光トランシーバ用波長多重機能付きPL
Cの例を示す。図中、51はスプリッタ回路(PL
C)、52は導波路、53は波長多重用干渉膜フィル
タ、54は入出力接続部、55は光トランシーバ用L
D,PD搭載部である。また、図8は図7のc−c´線
に沿う研磨後の入出力接続部54の拡大端面図であり、
図中、56はSi基板、57は下部クラッド層、58は
上部クラッド層、59はコアである。
FIG. 7 shows a second embodiment of the present invention, in which a PL with a wavelength multiplexing function for an optical transceiver is used.
The example of C is shown. In the figure, 51 is a splitter circuit (PL
C), 52 are waveguides, 53 is an interference film filter for wavelength multiplexing, 54 is an input / output connection portion, and 55 is an optical transceiver L.
D, PD mounting part. FIG. 8 is an enlarged end view of the input / output connection portion 54 after polishing along the line cc ′ in FIG.
In the figure, 56 is a Si substrate, 57 is a lower cladding layer, 58 is an upper cladding layer, and 59 is a core.

【0029】図7及び8に示す構造を作製するには、ま
ず、Si基板56にフォトリソグラフィでクラッド形状
をパターニングし、ウェットエッチングによりコア59
の下部に石英系ガラス下部クラッド層を形成する部分を
形成する。本例では、Si基板56のエッチング量を1
0μmと少なくしてクラッド形成後の凹凸が小さくなる
ようにした。次に、石英系ガラス下部クラッド層57を
FHD法で10μm堆積し、透明ガラス化する。
In order to fabricate the structure shown in FIGS. 7 and 8, first, a clad shape is patterned on a Si substrate 56 by photolithography, and a core 59 is formed by wet etching.
A portion for forming a quartz-based glass lower cladding layer is formed underneath. In this example, the etching amount of the Si substrate 56 is 1
The thickness was reduced to 0 μm so that unevenness after the formation of the clad was reduced. Next, a silica-based glass lower cladding layer 57 is deposited to a thickness of 10 μm by the FHD method, and is turned into a transparent glass.

【0030】この後、研磨による平坦化を行わず、Si
基板56をエッチングした部分以外の不要なクラッド層
をフォトリソグラフィによるパターニング及びガラスエ
ッチングで除去する。さらに、コア層を堆積し、コア5
9をパターニングする。コア59のパターニングでは、
凹凸が小さいので研磨による平坦化を行わずとも精密な
パターニングができた。その後、ガラスエッチングを行
い、最後に上部クラッド層58を堆積した。
Thereafter, without planarization by polishing,
Unnecessary cladding layers other than the portions where the substrate 56 is etched are removed by patterning by photolithography and glass etching. Further, a core layer is deposited, and a core 5
9 is patterned. In patterning the core 59,
Because of the small irregularities, precise patterning was possible without flattening by polishing. Thereafter, glass etching was performed, and finally, an upper clad layer 58 was deposited.

【0031】作製した光トランシーバ用波長多重機能付
きPLCでは、入出力接続部54の変形クラッド領域の
幅を50μm(コアを中心)、長さを2mmとした。作
製したウェファを切断し、研磨面には保護用にガラス板
(図示せず)をUV接着剤で固定した。その後、図7の
PLC端面を通常の方法で研磨した。研磨後の端面には
クラックは全く観測されなかつた。この結果より、本発
明の有効性が確認された。
In the manufactured PLC with the wavelength multiplexing function for the optical transceiver, the width of the deformed cladding region of the input / output connection portion 54 was set to 50 μm (centered on the core) and the length was set to 2 mm. The produced wafer was cut, and a glass plate (not shown) was fixed on the polished surface with a UV adhesive for protection. Thereafter, the end face of the PLC of FIG. 7 was polished by a usual method. No crack was observed on the end face after polishing. From these results, the effectiveness of the present invention was confirmed.

【0032】また、本例ではスプリッタの光学特性も、
変形クラッド領域のない従来のスプリッタと同じであ
り。この点でも本発明の有効性が確認された。
In this embodiment, the optical characteristics of the splitter are
Same as conventional splitter without deformed cladding region. In this respect, the effectiveness of the present invention was confirmed.

【0033】図9は本発明の第3の実施の形態を示すP
LCスプリッタの出力側接続部の端面図である。図中、
61はSi基板、62は下部クラッド層、63は上部ク
ラッド層、64はコアである。
FIG. 9 shows a third embodiment of the present invention.
It is an end elevation of the output side connection part of an LC splitter. In the figure,
61 is a Si substrate, 62 is a lower cladding layer, 63 is an upper cladding layer, and 64 is a core.

【0034】図9に示す構造を作製するには、まず、下
部クラッド層をFHD法で堆積し、透明ガラス化する。
次に、フォトリソグラフィでクラッド形状をパターニン
グし、ドライエッチングによりコア近傍に相当する下部
クラッド層62の部分のみを残す。コア層の形成後、マ
ーカを用いてコア64のパターング及びガラスエッチン
グを行い、矩形のコアを形成し、最後に上部クラッド層
63を堆積した。
In order to produce the structure shown in FIG. 9, first, a lower clad layer is deposited by the FHD method and is made vitrified.
Next, the clad shape is patterned by photolithography, and only the lower clad layer 62 corresponding to the vicinity of the core is left by dry etching. After the formation of the core layer, patterning and glass etching of the core 64 were performed using a marker to form a rectangular core, and finally the upper clad layer 63 was deposited.

【0035】なお、接続部以外の部分では下部クラッド
層が基板上の全面にあることはいうまでもない。
It is needless to say that the lower clad layer is present on the entire surface of the substrate except for the connection portion.

【0036】作製したウェファを切断し、研磨面には保
護用にガラス板(図示せず)をUV接着剤で固定した。
その後、図9のスプリッタ端面を通常の方法で研磨し
た。研磨後の端面にはクラックは全く観測されなかっ
た。本例によれば、Si基板のエッチング及び研磨が必
要ないので、簡便に変形クラッド領域を形成できる。
The produced wafer was cut, and a glass plate (not shown) was fixed on the polished surface with a UV adhesive for protection.
Thereafter, the end face of the splitter shown in FIG. 9 was polished by an ordinary method. No crack was observed on the polished end face. According to this example, since the etching and polishing of the Si substrate are not required, the deformed cladding region can be easily formed.

【0037】また、本例ではスプリッタの光学特性も、
変形クラッドのない従来のスプリッタと同じであり、こ
の点でも本発明の有効性が確認された。
In this embodiment, the optical characteristics of the splitter are
This is the same as a conventional splitter without a deformed cladding, and the effectiveness of the present invention was also confirmed in this regard.

【0038】なお、これまでの説明では基板としてSi
を用いたが、サファイア等の基板にも本発明は適用可能
である。また、各種の基板の加工にはウェットエッチン
グ以外にドライエッチングまたは機械加工が適用可能で
ある。また、変形クラッド領域のコアに沿う方向の長さ
についての制限はなく、全てのコアの下部クラッド層を
変形クラッド領域としても良いが、作製の容易さの点で
は端部のみが好ましい。また、幅については光学特性が
劣化しないところまで狭くすることが可能であり、数1
0μmのオーダになる。
It should be noted that in the above description, the substrate is Si
However, the present invention can be applied to a substrate such as sapphire. In addition, dry etching or mechanical processing other than wet etching can be applied to processing of various substrates. Further, there is no limitation on the length of the deformed cladding region in the direction along the core, and the lower cladding layer of all the cores may be the deformed cladding region. However, only the end portions are preferable from the viewpoint of ease of fabrication. Further, the width can be reduced to a point where the optical characteristics do not deteriorate.
It is on the order of 0 μm.

【0039】[0039]

【発明の効果】以上説明したように、本発明によれば、
研磨に伴う接続部でのクラック発生を防止でき、クラッ
クのない研磨面を形成できるので、信頼性の高いPLC
−ファイバ接続を実現できる。
As described above, according to the present invention,
Since cracks can be prevented from being generated at the connection part due to polishing and a polished surface without cracks can be formed, a highly reliable PLC
-A fiber connection can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来のPLC型スプリッタの構造を示す断面図FIG. 1 is a cross-sectional view showing the structure of a conventional PLC splitter.

【図2】研磨後のPLC端面を示す端面図FIG. 2 is an end view showing a PLC end face after polishing.

【図3】本発明の平面型光導波路の基本的な概念を示す
端面図
FIG. 3 is an end view showing the basic concept of the planar optical waveguide of the present invention.

【図4】本発明の平面型光導波路の第1の実施の形態を
示す平面図
FIG. 4 is a plan view showing a first embodiment of the planar optical waveguide of the present invention.

【図5】図4のa−a´線に沿う研磨後の出力側接続部
の拡大端面図
5 is an enlarged end view of the output side connection portion after polishing along the line aa ′ in FIG. 4;

【図6】図4のb−b´線に沿う拡大断面図FIG. 6 is an enlarged sectional view taken along the line bb ′ of FIG. 4;

【図7】本発明の平面型光導波路の第2の実施の形態を
示す平面図
FIG. 7 is a plan view showing a planar optical waveguide according to a second embodiment of the present invention.

【図8】図7のc−c´線に沿う研磨後の入出力接続部
の拡大端面図
FIG. 8 is an enlarged end view of the input / output connection portion after polishing along the line cc ′ in FIG. 7;

【図9】本発明の平面型光導波路の第3の実施の形態を
示す出力側接続部の端面図
FIG. 9 is an end view of an output-side connecting portion showing a third embodiment of the planar optical waveguide of the present invention.

【符号の説明】[Explanation of symbols]

31,45,56,61…Si基板、32,46,5
7,62…下部クラッド層、33,47,58,63…
上部クラッド層、34,48,59,64…コア、4
1,51…スプリッタ回路、42,52…導波路、43
…入力側接続部、44…出力側接続部、49…ガラス
板、53…波長多重用干渉膜フィルタ、54…入出力接
続部、55…光トランシーバ用LD,PD搭載部。
31, 45, 56, 61 ... Si substrate, 32, 46, 5
7, 62 ... lower cladding layer, 33, 47, 58, 63 ...
Upper cladding layer, 34, 48, 59, 64 ... core, 4
1, 51: splitter circuit, 42, 52: waveguide, 43
... input side connection part, 44 ... output side connection part, 49 ... glass plate, 53 ... interference film filter for wavelength multiplexing, 54 ... input / output connection part, 55 ... LD, PD mounting part for optical transceiver.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 山田 泰文 東京都新宿区西新宿3丁目19番2号 日 本電信電話株式会社内 (72)発明者 石井 元速 東京都新宿区西新宿3丁目19番2号 日 本電信電話株式会社内 (72)発明者 柳沢 雅弘 東京都新宿区西新宿3丁目19番2号 日 本電信電話株式会社内 (56)参考文献 特開 平8−43654(JP,A) 特開 平7−27933(JP,A) 特開 平9−166724(JP,A) 特開 平9−166723(JP,A) 特開 平8−201649(JP,A) 特表 平6−501570(JP,A) (58)調査した分野(Int.Cl.7,DB名) G02B 6/12 - 6/14 G02B 6/26 - 6/27 G02B 6/30 - 6/35 G02B 6/42 - 6/43 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yasufumi Yamada 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (72) Inventor Motohaya Ishii 3-19, Nishishinjuku, Shinjuku-ku, Tokyo No. 2 Nippon Telegraph and Telephone Corporation (72) Inventor Masahiro Yanagisawa 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-8-43654 (JP, A) JP-A-7-27933 (JP, A) JP-A-9-166724 (JP, A) JP-A-9-166723 (JP, A) JP-A-8-201649 (JP, A) -501570 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) G02B 6/12-6/14 G02B 6/26-6/27 G02B 6/30-6/35 G02B 6 / 42-6/43

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 光を導波伝搬するコアと該コアを囲みか
つ該コアよりも屈折率がわずかに低いクラッドとからな
る光導波路を基板上に形成するとともに、該基板の少な
くとも一端に前記基板上の光導波路と他の光導波路との
接続を行う接続部を設けてなる平面型光導波路におい
て、前記基板の前記接続部付近全体は、前記コアの下部を除
き、前記基板の他の部分よりも厚く形成され、 前記基板の前記接続部付近の前記コアの下部は、各コア
毎に独立に、前記基板の前記接続部付近の他の部分より
も薄く形成され、 前記クラッドは前記基板上に平坦に堆積されている こと
を特徴とする平面型光導波路。
An optical waveguide comprising a core for guiding and propagating light and a clad surrounding the core and having a refractive index slightly lower than the core is formed on a substrate, and the substrate is provided at least at one end of the substrate. In a planar optical waveguide provided with a connection portion for connecting the upper optical waveguide to another optical waveguide, the entire vicinity of the connection portion of the substrate except the lower portion of the core is provided.
And the lower part of the core near the connection part of the substrate is formed thicker than other portions of the substrate.
Independently of each other, from other portions of the substrate near the connection.
A flat optical waveguide , wherein the cladding is formed to be thin and the cladding is deposited flat on the substrate .
【請求項2】 前記基板の前記接続部付近の前記コアの
下部の断面形状であって前記接続部の端面に平行な断面
形状はコアに近い側を底辺とする台形であることを特徴
とする請求項1記載の平面型光導波路。
2. The core according to claim 1 , wherein said core is located near said connection portion of said substrate.
A cross section parallel to an end face of the connection portion, the cross section being a lower shape
2. The planar optical waveguide according to claim 1 , wherein the shape is a trapezoid whose base is on the side close to the core .
JP20505596A 1996-08-02 1996-08-02 Planar optical waveguide Expired - Lifetime JP3214544B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20505596A JP3214544B2 (en) 1996-08-02 1996-08-02 Planar optical waveguide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20505596A JP3214544B2 (en) 1996-08-02 1996-08-02 Planar optical waveguide

Publications (2)

Publication Number Publication Date
JPH1048460A JPH1048460A (en) 1998-02-20
JP3214544B2 true JP3214544B2 (en) 2001-10-02

Family

ID=16500703

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3214544B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003240990A (en) 2002-02-14 2003-08-27 Fujitsu Ltd Planar optical waveguide device
JP2005266179A (en) 2004-03-17 2005-09-29 Omron Corp Optical waveguide device, manufacturing method thereof, and intermediate body of optical waveguide device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9021944D0 (en) * 1990-10-09 1990-11-21 British Telecomm Self-aligned-v-groves and waveguides
JPH0727933A (en) * 1993-07-14 1995-01-31 Furukawa Electric Co Ltd:The Plane waveguide chip
JPH0843654A (en) * 1994-08-02 1996-02-16 Hitachi Cable Ltd Silica glass waveguide and its production
JPH09166723A (en) * 1995-12-15 1997-06-24 Furukawa Electric Co Ltd:The Optical waveguide module
JPH09166724A (en) * 1995-12-15 1997-06-24 Furukawa Electric Co Ltd:The Manufacture of optical waveguide module

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