JP3213844B2 - Method for manufacturing thin film transistor - Google Patents

Description

The present invention relates to a semiconductor device for forming a contact hole.

[Prior Art] With miniaturization and high integration of semiconductor devices, MOS transistors have been miniaturized, but there is a limit in reducing the cell area in the two-dimensional planar technology. Thus, a three-dimensional integrated circuit has been considered. This three-dimensional integrated circuit has many advantages over two-dimensional planar technology. Particularly, from the viewpoint of application to MOS memory, it is important to have high density, high integration, and low soft errors due to alpha rays. As one of the three-dimensional integrated circuits, a TFT (Thin Film Transistor) in which a source, a drain, and a channel region of a transistor are formed by a thin polysilicon layer.
r) there. A method of manufacturing the TFT will be described with reference to FIG.

First, a silicon oxide film 20 is formed on a semiconductor substrate 201 by a CVD method.
After forming 2, a polysilicon film is formed by a CVD method, and a gate electrode 203 is formed by etching using a positive resist by photolithography. (FIG. 2 (a)) Next, after the gate oxide film 204 is formed, an amorphous silicon film is formed at a low temperature by the LPCVD method, and a silicon film is crystallized by applying lamp annealing to form a polysilicon film 205. BF ₂ ⁺ which is a P-type impurity is ion-implanted using a resist as a mask to form a P + impurity layer 206. (FIG. 2 (b)) Further, after forming a pattern by etching using a positive resist by photolithography, forming a silicon oxide film 207 on the entire surface by a CVD method, forming a contact hole by a photolithography method, and performing aluminum sputtering on the entire surface. rear,
After forming a pattern using a positive resist layer by photolithography, aluminum wiring pattern 208 by etching
To form

[Problem to be Solved by the Invention] One of the major features of the SRAM is that the standby current is as low as possible for battery backup. However, it has become more difficult to keep the standby current low as the memory capacity increases. The TFT that appeared in the prior art was introduced here, but in order to further reduce the standby current, it is effective to apply heat to amorphous silicon and recrystallize the polysilicon layer that is the source, drain, and channel parts. It becomes. (SDM
1980-19 Central Rsearch Laboratory, Hitachi, L
td.,) In this TFT, too, overetching is performed when forming source / drain contacts in order to prevent contact failure due to residual etching. However, since the polysilicon layer in the source / drain / channel portion is thinned for the above reason (usually 1,000 mm or less), the contact etching causes an increase in resistance due to local thinning of the polysilicon film in the contact portion, and furthermore, a disconnection. Worry about. Therefore, the present invention is intended to explain such a problem. The purpose of the present invention is to reduce the increase in resistance due to the thinning of the polysilicon film due to the overetching of the polysilicon film and the failure due to the polysilicon disconnection during the contact etching of the source / drain. To prevent it.

[Means for Solving the Problems] In the method of manufacturing a thin film transistor according to the present invention, a step of depositing a first conductive layer above a substrate and patterning the first conductive layer to form a gate electrode and a pad portion Forming a first oxide film on the gate electrode;
Depositing a second conductive layer on the first oxide film and the pad portion; performing ion implantation on the second conductive layer to form source and drain regions of a thin film transistor; Forming a second dioxide film thereon, forming a contact hole in the second conductive layer and the second dioxide film located above the pad portion, and forming a second contact hole on the contact hole and the second dioxide film. Forming the three conductive layers in this order.

In the method of manufacturing a thin film transistor, the second conductive layer is made of polysilicon.

Further, the step of forming the polysilicon includes a step of depositing amorphous silicon on the first oxide film and the pad portion, and a step of performing lamp annealing on the amorphous silicon.

The thickness of the amorphous silicon is 300 to 700.
Angstrom.

Further, the lamp annealing temperature is 1000 to 1200 ° C.

The lamp annealing time is 20 to 60 seconds.

Further, in the step of forming the contact hole, a concave portion that becomes a part of the contact hole is formed in the pad portion.

Further, in the method for manufacturing a thin film transistor according to the present invention, the step of forming a first oxide film on the gate electrode includes:
Forming a first oxide film on the gate electrode and the pad portion, and removing the first oxide film on the pad portion to expose an upper surface of the pad portion. Features.

EXAMPLES Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a view showing an embodiment of the present invention in the order of steps. Ten
1 is a semiconductor substrate, 102, 106, 108 are silicon oxide films, 103
Is a gate electrode made of a polysilicon film, 104 is a polysilicon layer wiring portion, 105 is a PAD portion made of polysilicon, 109 is a positive resist, 107 is P-type polysilicon implanted with BF ₂ ⁺ , and 110 is an aluminum wiring layer .

First, a polysilicon oxide film 102 is formed on the entire surface of the semiconductor substrate 101 by 3000 to 5000 Å by a CVD method, and then a polysilicon film is formed at 600 to 640 ° C. in a monosilane atmosphere by an LPCVD method.
00~3000Å formed, BF ₂ ⁺ with a dose of 1 × 10 ¹⁵ is a P-type impurity on the entire surface, after the ion implantation energy 35 keV, by photolithography by forming after the anisotropic etching a pattern using a positive resist layer a As shown in the figure, a gate electrode 103, a first polysilicon wiring layer 104, and a PAD portion 105 below the second polysilicon contact are formed to form a first conductive layer. Next, a silicon oxide film to be the gate oxide film
After forming 106 to 200 ° by thermal oxidation, the contact portion between the first polysilicon wiring layer 104 and the second polysilicon layer and the second polysilicon wiring are etched by photolithography using a positive resist layer. The portion that will be the bottom of the layer contact is removed. (Figure b) Next, the amorphous silicon 3 was deposited at 520 ° C in a monosilane atmosphere by LPCVD.
Lamp annealing 1000 to 1200
After forming a polysilicon film by applying a temperature of 20 ° C. for 20 to 60 seconds and further forming a pattern by photolithography using a positive resist layer (not shown), BF ₂ ⁺ as a P-type impurity is dosed at 1 to 5 × 10 ^15. The second conductive layer is formed by ion implantation at an energy of 35 keV (FIG. 3C). Then on the whole surface
After forming silicon oxide film 108 by 3000 ~ 5000mm by CVD method,
Anisotropic etching is performed by photolithography using the positive resist layer 109 (FIG. 4D). (Figure e) then f
As shown in the figure, after aluminum is formed on the entire surface in a range of 5000 to 10,000 Å, a pattern is formed by etching, and an aluminum wiring layer is formed to form a third conductive layer.

According to this embodiment, at the time of contact etching, the polysilicon portion to be contact-etched has a PAD portion formed by the first polysilicon layer at the bottom. There is no need to worry about thinning or disconnection.

[Effects of the Invention] According to the present invention, when contact etching is performed for contacting a polysilicon layer, even if the thickness of the polysilicon in the source / drain portions is small, the polysilicon is excessively etched by the wiring layer. An increase in resistance due to thinning and a failure due to disconnection of polysilicon can be prevented.

Therefore, the present invention has an effect that a highly reliable semiconductor device can be provided.

[Brief description of the drawings]

1 (a) to 1 (f) are sectional views in the order of steps showing one embodiment of a method for manufacturing a semiconductor device of the present invention. 2 (a) to 2 (c) show a conventional method for manufacturing a semiconductor device. 101, 102 ... semiconductor substrate 102, 106, 108, 202, 204, 207 ... silicon oxide film 103, 203 ... gate electrode made of polysilicon film 104 ... polysilicon layer wiring part 105 ... PAD part made of polysilicon 109 ... positive resist layer 107, 206 ... BF ₂ ⁺ Implanted P-type polysilicon 110,208 ... Aluminum wiring layer 111 ... Polysilicon film not ion-implanted 205 ... Polysilicon layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/3205 H01L 21/336

Claims (8)

(57) [Claims] A step of depositing a first conductive layer above a substrate; a step of patterning the first conductive layer to form a gate electrode and a pad portion; and forming a first oxide film on the gate electrode. Forming, a step of depositing a second conductive layer on the first oxide film and the pad portion, and performing ion implantation on the second conductive layer to form source and drain regions of the thin film transistor; Forming a second dioxide film on the second conductive layer; forming a contact hole in the second conductive layer and the second dioxide film located above the pad portion; Forming a third conductive layer on the dioxide film in this order. 2. The method according to claim 1, wherein the second conductive layer is made of polysilicon. 3. The step of forming the polysilicon includes: a step of depositing amorphous silicon on the first oxide film and the pad portion; and a step of performing lamp annealing on the amorphous silicon. The method for manufacturing a thin film transistor according to claim 2. 4. The film thickness of said amorphous silicon is 300
4. The method according to claim 3, wherein the thickness is about 700 Å. 5. The lamp annealing temperature is 1000 to 1200.
5. The method for manufacturing a thin film transistor according to claim 3, wherein the temperature is ° C. 6. The lamp annealing time is 20 to 60 hours.
The method of manufacturing a thin film transistor according to claim 3, wherein the time is seconds. 7. The method for manufacturing a thin film transistor according to claim 1, wherein in the step of forming the contact hole, a concave portion which becomes a part of the contact hole is formed in the pad portion. . 8. The step of forming a first oxide film on the gate electrode, the step of forming a first oxide film on the gate electrode and the pad portion, and the step of forming the first oxide film on the pad portion. 8. The method of manufacturing a thin film transistor according to claim 1, further comprising: removing an upper surface of the pad portion to expose the upper surface of the pad portion. 9.