JPH04196538A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the increase of resistance occurring by excessive over- etching of a wiring layer, and failures occurring by disconnection of poly silicon, by forming a first conducting film under a third conducting film of the part which is exposed by etching a third insulating film while a third photo resist is used as a mask. CONSTITUTION:A gate electrode 103, a wiring layer 104 of a first poly silicon layer, and a PAD part 105 turning to a contact bottom part of a second poly silicon layer are formed by anisotropic etching. After a silicon oxide layer 106 turning to a gate oxide film is formed by thermal oxidation, etching is performed by photolithography using a positive resist layer, thereby eliminating a contact part between the poly silicon wiring layer 104 of the first layer and the poly silicon layer of the second layer, and a part turning to the contact bottom part of the second poly silicon wiring layer. After a silicon oxide film 108 is formed on the whole surface by a CVD method, anisotropic etching is performed by photolithography using a photo resist layer 109. After aluminum is formed on the whole surface, a pattern is formed by etching, and an aluminum wiring layer 110 is formed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device that forms contact holes.

[Prior Art] With the miniaturization and higher integration of semiconductor devices, MO8 type transistors have also been miniaturized, but there is a limit to the ability to reduce the cell area using two-dimensional brainer technology. This led to the idea of three-dimensional integrated circuits. This three-dimensional integrated circuit has many advantages over two-dimensional brainer technology. Particularly important from the viewpoint of application to MOS memory are high density, high integration, and low soft errors caused by alpha rays. One of these three-dimensional integrated circuits is a TFT (Thin Fi
lm Transistor). The method for manufacturing this TPT will be explained using FIG. 2.

First, a silicon oxide film 202 is formed on a semiconductor substrate 201 by the CVD method, a polysilicon film is formed by the CVD method, and a gate electrode 203 is formed by etching using a positive resist by photolithography. (FIG. 2(a)) Next, after forming the gate oxide film 204, LPCVD
An amorphous silicon film is formed at a low temperature using a method, and lamp annealing is applied to crystallize the silicon to form a polysilicon film 205. P-type impurity BF2'' is ion-implanted using a photoresist as a mask to form a P-type impurity layer. 206 (FIG. 2(b)) After forming a pattern by photolithography and etching using a positive resist, a silicon oxide film 207 is formed on the entire surface by CVD, and a contact hole is formed by photolithography. After aluminum sputtering on the entire surface, a pattern is formed using a positive resist layer by photolithography, and then an aluminum wiring pattern 208 is formed by etching.

[Problems to be Solved by the Invention] One of the major features of SRAM is that the standby current is low enough to allow battery backup. However, as memory capacity increases, it is becoming difficult to keep the standby current low. This is where the TPT described in the conventional technology appeared, but in order to further reduce the standby current, it is effective to thin the polysilicon layer that forms the source, drain, and channel parts by applying heat to amorphous silicon and recrystallizing it. It becomes. (
SDM 1980-19 CentralRsea
rch Laboratory, Hitachi, L.
td-j) By the way, in this TPT as well, over-etching is applied when forming source/drain contacts in order to prevent contact failure due to etching residue. However, because the polysilicon layer in the source, drain, and channel portions is made thinner (usually less than 1000%) for the reason mentioned above.
In contact etching, there is a risk of an increase in resistance due to local thinning of the polysilicon film at the contact portion, and furthermore, a risk of wire breakage. The present invention is intended to solve these problems, and its purpose is to
During drain contact etching, the purpose is to prevent an increase in resistance due to thinning of the polysilicon group due to overetching and to prevent failures due to polysilicon wire breakage.

[Means for Solving the Problems] The semiconductor device of the present invention includes a first insulating film formed on a semiconductor substrate, a first conductive film formed on the first insulating film,
A first photoresist formed in a predetermined first pattern, a pattern formed by etching using the first photoresist as a mask, and a part of a second insulating film formed on the first conductive film. the second insulating film from which has been removed, a second conductive film formed on the second insulating film and the exposed first conductive film, and a second photoresist formed in a predetermined second pattern. , a pattern formed by etching using the second photoresist as a mask; a third insulating film formed on the second conductive film and the second insulating film exposed by etching the second conductive film; a third photoresist formed in a predetermined third pattern on a third insulating film; and a semiconductor made of the third insulating film partially removed by etching using the third photoresist as a mask. The device is characterized in that the first conductive film is formed under the third conductive film in the exposed portion by etching the third insulating film using the third photoresist as a mask.

[Example] Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a diagram showing an embodiment of the present invention in the order of steps. 10
1 is a semiconductor substrate, 102.106.1°8 is a silicon oxide film, 103 is a gate electrode made of a polysilicon film, 1
04 is a polysilicon layer wiring part, 105 is a polysilicon PAD part, 109 is a positive resist, 107 is BF2
110 is an aluminum wiring layer.

First, a polysilicon oxide film 102 of 3,000 to 5,000 layers is formed on the entire surface of a semiconductor substrate 101 by the CVD method, and then a polysilicon oxide film of 600 to 5,000 layers is formed by the LPCVD method in a monosilane atmosphere.
Form a polysilicon film of 2000-3000A at 40℃,
A dose of BF2+, which is a P-type impurity, is applied to the entire surface.
- After ion implantation with an energy of 35 keV, a pattern is formed using a positive resist layer by photolithography, and then anisotropic etching is performed to form the gate electrode 1 as shown in figure a.
03. A wiring layer 104 of the first polysilicon layer and a PAD section 105 which will be the lower part of the contact of the second polysilicon layer are formed. Next, 200 to 300 silicon oxide films 106, which will become gate oxide films, are formed by thermal oxidation, and then the first polysilicon wiring layer 104 and the second polysilicon layer are etched using a positive resist layer by photolithography. The contact portion of the layer and the portion that will become the contact bottom of the second polysilicon wiring layer are removed. (Figure b) Next, 300 to 700 layers of amorphous silicon were formed using the LPCVD method at 520°C in a monosilane atmosphere, and then a polysilicon film was formed by adding Helambu annealing at 1000 to 1200°C for 20 to 60 seconds, and then photolithography. After forming a pattern using a positive resist layer 106, a P-type impurity BF2° is added at a dose of 1 to 5×1.
015, ion implantation is performed at an energy of 35 keV (Figure 0). Next, after forming a silicon oxide film 108 of 3000 to 5000 Å on the entire surface by CVD, anisotropic etching is performed using a positive resist layer 109 by photolithography (Fig. d). (Fig. e) Thereafter, as shown in Fig. f, aluminum is formed on the entire surface with a thickness of 500 to 10,000 Å, and a pattern is formed by etching to form an aluminum wiring layer.

According to this embodiment, when contact etching is performed, the polysilicon portion to be contact etched has a PAD portion formed at the bottom by the first layer of polysilicon, so that the contact portion of the second layer of polysilicon is formed during contact etching. There is no need to worry about the film becoming thin or breaking.

[Effects of the Invention] According to the present invention, when contact etching is performed on a polysilicon layer for contact contact, even if the polysilicon film thickness in the source/train portion is thin, the polysilicon layer is not etched due to excessive overetching of the wiring layer. Failures due to increased resistance due to thinner films and disconnections in polysilicon can be prevented.

Therefore, the present invention has the effect of providing a highly reliable semiconductor device.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(f) are step-by-step cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 2(a) to 2(C) show a conventional method for manufacturing a semiconductor device. 101.102...Semiconductor substrate 102.106, 108, 202, 204.207
...Silicon oxide film 103.203...Gate electrode 104 made of polysilicon film ...Polysilicon layer wiring section 105
...PAD section 109 made of polysilicon ...Positive resist layer 107.206 ...P-type polysilicon implanted with BF2'' 110.208 ...Aluminum wiring layer 205 ...Polysilicon layer and above Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Yoshizobe Ogi (and 1 other person) 'J'lLl force (α) U() + 1y, <(・) Iro'A (c) Pleasure 11 SoI (, () Pleasure 1) Concave (已) 潴1 figure (j)

Claims (1)

[Claims] a first insulating film formed on a semiconductor substrate, a first conductive film formed on the first insulating film, a first photoresist formed in a predetermined first pattern, and the first photoresist. a pattern formed by etching using a resist as a mask; a second insulating film formed on the first conductive film;
the second insulating film from which a portion has been removed; a second conductive film formed on the second insulating film and the exposed first conductive film;
a second photoresist formed in a predetermined second pattern; a pattern formed by etching using the second photoresist as a mask; and a second conductive film exposed by etching the second conductive film. A third insulating film formed on the second insulating film, a third photoresist formed in a predetermined third pattern on the third insulating film, and etching using the third photoresist as a mask. In the semiconductor device comprising the third insulating film that has been partially removed, the third insulating film is etched using the third photoresist as a mask, so that the first insulating film is etched under the exposed portion of the third conductive film. A semiconductor device characterized in that a conductive film is formed.