JP3186236B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3186236B2
JP3186236B2 JP22560492A JP22560492A JP3186236B2 JP 3186236 B2 JP3186236 B2 JP 3186236B2 JP 22560492 A JP22560492 A JP 22560492A JP 22560492 A JP22560492 A JP 22560492A JP 3186236 B2 JP3186236 B2 JP 3186236B2
Authority
JP
Japan
Prior art keywords
adhesive
conductor
semiconductor device
semiconductor
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22560492A
Other languages
Japanese (ja)
Other versions
JPH0677282A (en
Inventor
禎志 中村
喜久 ▲高▼瀬
修司 近藤
康晴 福井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP22560492A priority Critical patent/JP3186236B2/en
Publication of JPH0677282A publication Critical patent/JPH0677282A/en
Application granted granted Critical
Publication of JP3186236B2 publication Critical patent/JP3186236B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関するものであり、特にマイクロコンピュータやゲート
アレイ等の多電極、狭ピッチのＬＳＩチップの実装方法
に関するものである。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for mounting a multi-electrode, narrow-pitch LSI chip such as a microcomputer or a gate array.

【０００２】[0002]

【従来の技術】従来の半導体装置の製造方法を図３と共
に説明する。2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described with reference to FIG.

【０００３】まず、図３（ｂ）に示すようにガラスから
なる基板１上にインジウム・錫酸化物（ＩＴＯ）等の薄
膜電極２を形成し、フォトレジスト３をめっきマスクと
して金（Ａｕ）等をめっきして突起状導体４を形成す
る。次に図３（ａ）に示すＬＳＩチップ５を用意し、図
３（ｃ）のようにＬＳＩチップ５上のＡｌ電極６と突起
状導体４とを位置合わせし、約４７０℃に加熱された加
圧ツール７によってＬＳＩチップ５を加圧する。この加
圧によって、Ａｌ電極６と突起状導体４のＡｕが拡散し
て合金を形成し、図３（ｄ）に示すようにＬＳＩチップ
５に突起状導体４が転写される。First, as shown in FIG. 3 (b), a thin film electrode 2 such as indium tin oxide (ITO) is formed on a substrate 1 made of glass, and a photoresist 3 is used as a plating mask to form gold (Au) or the like. To form the protruding conductor 4. Next, an LSI chip 5 shown in FIG. 3A was prepared, and the Al electrode 6 on the LSI chip 5 and the protruding conductor 4 were aligned as shown in FIG. 3C, and heated to about 470 ° C. The LSI chip 5 is pressed by the pressing tool 7. By this pressurization, Au of the Al electrode 6 and the projecting conductor 4 diffuses to form an alloy, and the projecting conductor 4 is transferred to the LSI chip 5 as shown in FIG.

【０００４】次に、図３（ｅ）に示すようにＡｕや銀・
パラジウム（Ａｇ−Ｐｄ）、ＩＴＯ等からなる導体配線
８を形成したガラスやセラミック等からなる基板９上
に、接着剤１０を塗布する。続いて図３（ｆ）に示すよ
うに導体配線８とＬＳＩチップ５に転写された突起状導
体４とを位置合わせし、常温のままで加圧ツール７によ
ってＬＳＩチップ５を加圧する。その状態で接着剤１０
を硬化する。この硬化によってＬＳＩチップ５の突起状
導体４と導体配線８が電気的に接続される（図３
（ｇ））。[0004] Next, as shown in FIG.
An adhesive 10 is applied on a substrate 9 made of glass, ceramic, or the like, on which a conductor wiring 8 made of palladium (Ag-Pd), ITO, or the like is formed. Subsequently, as shown in FIG. 3 (f), the conductor wiring 8 is aligned with the projecting conductor 4 transferred to the LSI chip 5, and the LSI chip 5 is pressed by the pressing tool 7 at a normal temperature. In that state, the adhesive 10
To cure. By this curing, the protruding conductor 4 of the LSI chip 5 and the conductor wiring 8 are electrically connected (FIG. 3).
(G)).

【０００５】[0005]

【発明が解決しようとする課題】前述した従来の構成で
は、ＬＳＩチップ５のＡｌ電極６に突起状導体４を転写
する工程で、ＬＳＩチップ５の破損や転写不良が発生す
る。また個別でＬＳＩチップ５への突起状導体４の転写
を行い、その後もＬＳＩチップ５を個別に取り扱うた
め、少量生産では対応できるが、多量生産になるとＬＳ
Ｉチップ５の搬送が短時間では困難となり、配線基板へ
の実装時間が長くなるため生産コストが高くなるという
問題点を有していた。In the above-described conventional configuration, in the step of transferring the projecting conductor 4 to the Al electrode 6 of the LSI chip 5, breakage or poor transfer of the LSI chip 5 occurs. In addition, since the protruding conductors 4 are individually transferred to the LSI chip 5 and then the LSI chip 5 is individually handled, it is possible to cope with small-scale production.
There has been a problem that it is difficult to transport the I chip 5 in a short time, and the mounting time on the wiring board becomes longer, thereby increasing the production cost.

【０００６】本発明は上記従来の問題点を解決するもの
で、テープ状に突起状導体と接着材料を形成し、この上
にＬＳＩチップを仮固定して、突起状電極と接着剤を同
時にＬＳＩチップに転写する半導体装置の製造方法を提
供するものである。The present invention solves the above-mentioned conventional problems. A projecting conductor and an adhesive material are formed in a tape shape, an LSI chip is temporarily fixed thereon, and the projecting electrode and the adhesive are simultaneously applied to the LSI. An object of the present invention is to provide a method of manufacturing a semiconductor device to be transferred to a chip.

【０００７】[0007]

【課題を解決するための手段】この目的を達成するため
に本発明の半導体の製造方法は、フィルムベース上に半
導体素子の電極位置に合わせて穴が開くように絶縁層を
形成する工程と、前記穴に突起状導体を形成しそれを覆
うように絶縁性の接着層を形成して接着シートを形成す
る工程と、あらかじめ非酸化性の金属導体がその表面に
形成された半導体素子の電極と前記突起状導体との位置
合わせを行い前記接着層を仮硬化して仮固定する工程
と、前記半導体素子から前記絶縁層を含む前記フィルム
ベースを剥離する工程と、前記半導体素子側に仮固定さ
れた前記突起状導体と配線基板の電極との位置合わせを
行い、前記半導体素子の電極と前記突起状導体、および
前記突起状導体と前記配線基板の電極とがそれぞれの間
に存在する前記接着層を排出して電気的な接続が図られ
まで加圧するとともに、同時に前記接着層を本硬化して
前記半導体素子を前記配線基板に本固定する工程とを有
するものである。In order to achieve this object, a method for manufacturing a semiconductor according to the present invention comprises a method of forming a semiconductor on a film base.
Insulate the insulating layer so that a hole is opened according to the electrode position of the conductive element.
Forming a projecting conductor in the hole and covering it.
Form an adhesive sheet by forming an insulating adhesive layer
A non-oxidizing metal conductor on the surface in advance.
Position of the formed semiconductor element electrode and the protruding conductor
A step of temporarily curing the adhesive layer and temporarily fixing the adhesive layer
And the film including the insulating layer from the semiconductor element
Removing the base, and temporarily fixing the base to the semiconductor element side.
Alignment between the projected conductor and the electrode of the wiring board.
Perform, the electrode of the semiconductor element and the protruding conductor, and
Between the protruding conductor and the electrode of the wiring board
The adhesive layer present at the end is discharged to establish an electrical connection.
And at the same time, fully cure the adhesive layer
Permanently fixing the semiconductor element to the wiring board.
Is what you do.

【０００８】[0008]

【作用】従って本発明によれば、接着シートに半導体素
子を仮固定した後に、絶縁層を含むフィルムベースを剥
離しているので、確実に突起状導体と接着材料を半導体
素子に転写することができる。また接着シートをテープ
状に形成することにより突起状導体と接着材料が転写さ
れた半導体素子の搬送を容易にし、連続して配線基板に
実装することができる。Therefore, according to the present invention , the semiconductor element is added to the adhesive sheet.
After temporarily fixing the child, peel off the film base including the insulating layer.
Since they are separated , the projecting conductor and the adhesive material can be reliably transferred to the semiconductor element. Further, by forming the adhesive sheet in a tape shape, the semiconductor element to which the projecting conductor and the adhesive material are transferred can be easily transported, and the semiconductor element can be continuously mounted on the wiring board.

【０００９】[0009]

【実施例】本発明の一実施例を図１，図２を用いて説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS.

【００１０】図１（ａ）〜（ｅ）は本発明の実施例にお
けるフィルムベース上に形成された突起状導体と接着材
料にＬＳＩチップを仮固定し、フィルムベースをテープ
状に形成する工程を示す工程図である。FIGS. 1 (a) to 1 (e) show a step of temporarily fixing an LSI chip to a projecting conductor and an adhesive material formed on a film base and forming the film base into a tape according to an embodiment of the present invention. FIG.

【００１１】まず図１（ａ）に示すようにＰＥＴ，ポリ
イミド，テフロン等からなるフィルムベース１１上にＩ
ＴＯ，Ａｕ等からなる導電性金属薄膜電極１２を成膜し
たものを用意し、フッ素樹脂を混入したフォトレジスト
１３をＬＳＩチップの電極位置に穴が開くよう塗布し、
これをめっきマスクとしてＡｕをめっきして突起状導体
１４を形成する。本実施例では導電性金属薄膜電極１２
としてＩＴＯ膜を用いた。図１（ｂ）は突起状導体１４
を形成した様子を示している。First, as shown in FIG. 1A, a film base 11 made of PET, polyimide, Teflon, etc.
A conductive metal thin film electrode 12 made of TO, Au, or the like is formed, and a photoresist 13 mixed with a fluororesin is applied so as to open a hole at an electrode position of the LSI chip.
Using this as a plating mask, Au is plated to form the projecting conductor 14. In this embodiment, the conductive metal thin film electrode 12
Was used as an ITO film. FIG. 1B shows a projection-like conductor 14.
Is formed.

【００１２】さらに、図１（ｃ）に示すように熱可塑、
熱硬化の二反応系を持つ第一の接着剤１５を均一に塗布
する。この接着剤１５としてはこの他熱硬化、ＵＶ硬化
併用接着剤についても実施した。Further, as shown in FIG.
The first adhesive 15 having a thermosetting two-reaction system is uniformly applied. In addition to this, an adhesive 15 used in combination with heat curing and UV curing was also used.

【００１３】次にあらかじめＬＳＩチップ１６のＡｌ電
極上にＡｕの薄膜１７を無電解めっきで形成したものと
突起状導体１４を位置合わせし、図１（ｄ）に示すよう
に約８０に加熱した加圧ツール１８によってＬＳＩチッ
プ１６を加圧する。このとき接着剤１５の熱可塑反応に
より接着剤１５が仮硬化し、ＬＳＩチップ１６が突起状
導体１４と共にフィルムベース１１上に仮固着される。
このフィルムベース１１をテープ形状にすることにより
図１（ｅ）のようにＬＳＩチップをテーピング部品とし
て取り扱うことが可能となり、搬送や量産機への応用が
容易となる。Next, an Au thin film 17 formed on an Al electrode of an LSI chip 16 by electroless plating and the protruding conductor 14 were aligned and heated to about 80 as shown in FIG. 1 (d). The LSI chip 16 is pressed by the pressing tool 18. At this time, the adhesive 15 is temporarily cured by a thermoplastic reaction of the adhesive 15, and the LSI chip 16 is temporarily fixed on the film base 11 together with the projecting conductors 14.
By forming the film base 11 into a tape shape, it becomes possible to handle the LSI chip as a taping component as shown in FIG. 1E, thereby facilitating transportation and application to a mass production machine.

【００１４】次に図２（ａ）〜（ｅ）に本発明の一実施
例におけるＬＳＩチップの実装工程を示す工程断面図を
示す。Next, FIGS. 2A to 2E are sectional views showing the steps of mounting an LSI chip in one embodiment of the present invention.

【００１５】図２（ａ）は図１で説明した工程によって
形成されたＬＳＩチップのテーピング部品をＬＳＩチッ
プ１６の形状に切り込み１９を入れたことを表してい
る。この切り込み１９はフィルムベース１１内部まで切
り込まれているが、フィルムベース１１を切断してはな
らない。ここでＬＳＩチップ１６を個々に切断すると搬
送が効率的に行えないからである。従って図２（ｂ）に
示すようにＬＳＩチップ１６を個別に扱う工程に来たと
ころで、フィルムベース１１をめくり取るようにしてＬ
ＳＩチップ１６を引きはがし分離する。このとき接着剤
１５は仮硬化してＬＳＩチップ１６と突起状導体１４と
フィルムベース１１を仮固着しているが、フィルムベー
ス１１上に塗布したフッ素樹脂を混入したフォトレジス
ト１３の効果により、接着剤１５とフォトレジスト１３
の界面は接着力が弱くなるため、ＬＳＩチップ１６は必
ず接着剤１５と突起状導体１４を伴ってフィルムベース
１１からはがれる。またＩＴＯで形成した導電性金属薄
膜電極１２と突起状導体１４の界面も密着力が弱いの
で、突起状導体１４がフィルムベース１１側に残ること
はない。FIG. 2A shows that the taping component of the LSI chip formed by the process described with reference to FIG. The cut 19 is cut into the film base 11, but the film base 11 must not be cut. This is because if the LSI chips 16 are individually cut, transport cannot be performed efficiently. Therefore, as shown in FIG. 2B, when the process for handling the LSI chips 16 has been individually performed, the film base 11 is turned over so that
The SI chip 16 is peeled off and separated. At this time, the adhesive 15 is temporarily cured to temporarily fix the LSI chip 16, the projecting conductor 14, and the film base 11, but due to the effect of the photoresist 13 mixed with the fluororesin applied on the film base 11, the bonding is performed. Agent 15 and photoresist 13
Since the bonding force of the interface becomes weak, the LSI chip 16 always comes off the film base 11 together with the adhesive 15 and the protruding conductor 14. Also, since the interface between the conductive metal thin film electrode 12 formed of ITO and the protruding conductor 14 has a weak adhesion, the protruding conductor 14 does not remain on the film base 11 side.

【００１６】一方で、Ａｕ，Ａｌ，Ｃｕ等からなる導体
配線２０を形成したガラスやセラミック、シリコン等か
らなる基板２１を用意し、図２（ｃ）に示すように接着
剤１５と突起状導体１４を伴うＬＳＩチップ１６の突起
状導体１４と導体配線２０とを位置合わせし、図２
（ｄ）に示すように約２００℃に加熱された加圧ツール
２２によってＬＳＩチップ１６を加圧する。このとき接
着剤１５は一時流動性を持ち同時に突起状導体１４が押
しつぶされることにより、ＬＳＩチップ１６の電極と突
起状導体１４及び突起状導体１４と導体配線２０の界面
に存在する接着剤１５を排出し、その直後接着剤１５が
熱硬化することにより、ＬＳＩチップ１６と導体配線２
０が電気的に接続される（図２（ｅ））。On the other hand, a substrate 21 made of glass, ceramic, silicon or the like on which a conductor wiring 20 made of Au, Al, Cu or the like is formed is prepared, and as shown in FIG. 2A and 2B, the projecting conductor 14 of the LSI chip 16 with the conductor 14 and the conductor wiring 20 are aligned.
As shown in (d), the LSI chip 16 is pressed by the pressing tool 22 heated to about 200 ° C. At this time, the adhesive 15 has a temporary fluidity and simultaneously squeezes the projecting conductor 14, thereby causing the adhesive 15 existing at the interface between the electrode of the LSI chip 16 and the projecting conductor 14 and the interface between the projecting conductor 14 and the conductor wiring 20. The LSI 15 is discharged, and the adhesive 15 is thermally cured immediately thereafter.
0 is electrically connected (FIG. 2E).

【００１７】本発明の半導体装置に不良が発生した場
合、ＬＳＩチップ１６に約１３０℃の温度と同時にせん
断力をかけることにより、ＬＳＩチップ１６は容易に取
り外すことができる。これは約１３０℃に加熱すること
により接着剤１５の熱可塑特性が現れ基板２１との密着
力が弱くなるからである。また基板２１に残った接着剤
１５の残査はトルエンを用いて湿布洗浄することにより
取り除くことができる。従って再度同一の方法でＬＳＩ
チップの実装が可能となる。If a defect occurs in the semiconductor device of the present invention, the LSI chip 16 can be easily removed by applying a shearing force to the LSI chip 16 at a temperature of about 130 ° C. This is because the thermoplastic property of the adhesive 15 appears by heating to about 130 ° C., and the adhesion to the substrate 21 is weakened. The residue of the adhesive 15 remaining on the substrate 21 can be removed by washing with a compress using toluene. Therefore, the LSI is again implemented in the same manner.
Chip mounting becomes possible.

【００１８】[0018]

【発明の効果】以上のように本発明によれば、確実に突
起状導体と接着材料を半導体素子に転写することができ
るとともに、突起状導体と接着材料が転写された半導体
素子の搬送を容易にし、連続して配線基板への実装を行
うことができる。 As described above, according to the present invention, it is possible to surely
Can transfer imprinted conductor and adhesive material to semiconductor device
As well as semiconductors on which the protruding conductor and adhesive material are transferred
It facilitates the transport of elements and continuously mounts them on a wiring board.
I can.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ）〜（ｅ）は本発明の一実施例におけるテ
ープ状のフィルムベース上に半導体素子を仮固定するた
めの工程図FIGS. 1A to 1E are process diagrams for temporarily fixing a semiconductor element on a tape-like film base in one embodiment of the present invention.

【図２】（ａ）〜（ｅ）は本発明の一実施例における半
導体装置の製造方法を説明するための工程図FIGS. 2A to 2E are process diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention;

【図３】（ａ）〜（ｇ）は従来の半導体装置の製造方法
を説明するための工程図FIGS. 3A to 3G are process diagrams illustrating a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

１１ フィルムベース １２ 導電性金属薄膜電極 １３ フッ素樹脂を混入したフォトレジスト １４ 突起状導体 １５ 接着剤 １６ ＬＳＩチップ １７ Ａｕ薄膜 ２０ 導体配線 ２１ 基板 DESCRIPTION OF SYMBOLS 11 Film base 12 Conductive metal thin film electrode 13 Photoresist mixed with fluorocarbon resin 14 Protruding conductor 15 Adhesive 16 LSI chip 17 Au thin film 20 Conductor wiring 21 Substrate

フロントページの続き (72)発明者 福井 康晴 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 昭61−198738（ＪＰ，Ａ) 特開 平２−140945（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 Continuation of the front page (72) Inventor Yasuharu Fukui 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-61-198738 (JP, A) JP-A-2-140945 (JP) , A) (58) Fields surveyed (Int. Cl. 7 , DB name) H01L 21/60

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 フィルムベース上に半導体素子の電極位
置に合わせて穴が開くように絶縁層を形成する工程と、
前記穴に突起状導体を形成しそれを覆うように絶縁性の
接着層を形成して接着シートを形成する工程と、あらか
じめ非酸化性の金属導体がその表面に形成された半導体
素子の電極と前記突起状導体との位置合わせを行い前記
接着層を仮硬化して仮固定する工程と、前記半導体素子
から前記絶縁層を含む前記フィルムベースを剥離する工
程と、前記半導体素子側に仮固定された前記突起状導体
と配線基板の電極との位置合わせを行い、前記半導体素
子の電極と前記突起状導体、および前記突起状導体と前
記配線基板の電極とがそれぞれの間に存在する前記接着
層を排出して電気的な接続が図られまで加圧するととも
に、同時に前記接着層を本硬化して前記半導体素子を前
記配線基板に本固定する工程とを有する半導体装置の製
造方法。 An electrode position of a semiconductor device on a film base.
Forming an insulating layer so that a hole is opened according to the position,
Form a projecting conductor in the hole and insulate it so as to cover it
A step of forming an adhesive sheet by forming an adhesive layer;
A semiconductor with a non-oxidizable metal conductor formed on its surface
Align the electrode of the element and the projecting conductor and perform
Temporarily curing and temporarily fixing the adhesive layer; and
For removing the film base including the insulating layer from
And the protruding conductor temporarily fixed to the semiconductor element side.
And the electrodes of the wiring board are aligned.
And the protruding conductor, and the protruding conductor and
The bonding between the electrodes of the wiring board and the electrodes
The layer is discharged and pressurized until electrical connection is achieved.
At the same time, the adhesive layer is fully cured to bring the semiconductor element forward.
A method of manufacturing a semiconductor device, the method comprising: 【請求項２】 絶縁層がフッ素樹脂を含むフォトレジス
トからなることを特徴とする請求項１記載の半導体装置
の製造方法。2. A photoresist in which the insulating layer contains a fluororesin.
2. The method for manufacturing a semiconductor device according to claim 1, comprising: 【請求項３】 接着シートをテープ状に形成し、半導体
素子をそのテープ上に仮固定して整列させたことを特徴
とする請求項１記載の半導体装置の製造方法。3. An adhesive sheet is formed in a tape shape, and a semiconductor
The element is temporarily fixed on the tape and aligned.
2. The method of manufacturing a semiconductor device according to claim 1, wherein 【請求項４】 硬化反応性の異なる少なくとも熱可塑性
接着剤、熱硬化性接着剤、光硬化性接着剤のいずれか２
種類の接着材料を組み合わせて接着シートを形成するこ
とを特徴とする請求項１記載の半導体装置の製造方法。4. Any one of at least a thermoplastic adhesive, a thermosetting adhesive, and a photocurable adhesive having different curing reactivity.
2. The method for manufacturing a semiconductor device according to claim 1, wherein an adhesive sheet is formed by combining different kinds of adhesive materials.
JP22560492A 1992-08-25 1992-08-25 Method for manufacturing semiconductor device Expired - Fee Related JP3186236B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22560492A JP3186236B2 (en) 1992-08-25 1992-08-25 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22560492A JP3186236B2 (en) 1992-08-25 1992-08-25 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0677282A JPH0677282A (en) 1994-03-18
JP3186236B2 true JP3186236B2 (en) 2001-07-11

Family

ID=16831934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22560492A Expired - Fee Related JP3186236B2 (en) 1992-08-25 1992-08-25 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3186236B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3565319B2 (en) * 1999-04-14 2004-09-15 シャープ株式会社 Semiconductor device and manufacturing method thereof
US6872635B2 (en) 2001-04-11 2005-03-29 Sony Corporation Device transferring method, and device arraying method and image display unit fabricating method using the same

Also Published As

Publication number Publication date
JPH0677282A (en) 1994-03-18

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