JP3170758B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor integrated circuit. In particular, in a semiconductor integrated circuit in which block circuits are connected to each other to form a boundary chain structure, if there is a failure point such as a conduction failure or a short circuit near the pad, it is necessary to contact the probe to all pads. However, the present invention relates to an improvement that makes it possible to easily find the failure location.

[0002]

2. Description of the Related Art A conventional semiconductor device pad for an input / output circuit will be described. 8 and 9, reference numeral 1 denotes a field insulating film, 11 denotes a lower conductor layer extending on the field insulating film 1 and serving as input / output wiring, 12 denotes an insulating film, and 13 denotes an insulating film. An upper conductor layer 14 is a surface stabilizing film.

In the prior art, as shown in FIG.
The pads 2 as shown in FIG. 8 are arranged in a line around the semiconductor chip 5. In order to test the above-described semiconductor device according to the related art, a test circuit as shown in FIG. 10 has been used. Reference numeral 2 in FIG. 10 denotes pads, which transmit and receive signals to and from the semiconductor device.

Reference numeral 21 denotes a boundary scan FF, which is connected to a scan-in terminal SI connected to a scan-out terminal of a boundary scan FF adjacent to one side and a scan-in terminal of a boundary scan FF adjacent to the other side. It has a scan-out terminal SO, a data terminal D for taking in data into the boundary scan FF, a terminal CK for inputting a clock signal of a system circuit, and a test clock terminal TCK. 22 is a selector. 23 is an output circuit, which outputs a signal output from the logic circuit shown with a L _1. 24 is an input circuit, for inputting a signal to be inputted to the logic circuit illustrated with a L _2.

To perform a function test of a semiconductor device using such a circuit, it is necessary to bring a probe (not shown) into contact with all the pads 2 as long as a boundary scan chain is established. Not reachable.

However, in order to check the continuity or short-circuit of the portion indicated by A in FIG. 10, the probe must be in contact with all the pads 2. This is because even if there is a defect in this part, a boundary scan chain is established.

[0007]

Next, since it is desirable that the number of pads provided on the semiconductor device is large, it is difficult to arrange them in a line along the periphery of the semiconductor chip as shown in FIG. Instead, it is desired that the pads are arranged in two rows along the periphery of the semiconductor chip, and that pads are dispersedly arranged over the entire surface of the semiconductor chip.

However, as described above, in order to check the continuity or short-circuit of the portion indicated by A in FIG.
Has to be brought into contact with the whole number of the semiconductor chips, so that there is a disadvantage that pads cannot be arranged over a wide area of the semiconductor chip as described above.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks. In a semiconductor integrated circuit in which block circuits are connected to each other to form a boundary chain structure, an area near a pad has poor conduction or short-circuit. An object of the present invention is to provide an improved semiconductor integrated circuit that can easily find a fault location without having to contact a probe with all pads when the fault location exists.

[0010]

An object of the present invention is to provide a semiconductor device having a first data input terminal, a second data input terminal, and a data output terminal, wherein the first and second data input terminals are connected to each other in response to a clock signal. A data output circuit that outputs an output signal corresponding to any one of the data input terminals from the data output terminal; and a first lower conductive layer connected to the second data input terminal. Short-circuiting the first lower conductive layer and the second lower conductive layer when an external signal is input to the second lower conductive layer connected to the data output terminal; A semiconductor integrated circuit in which a plurality of block circuits each having an upper conductive layer are arranged, and in the two adjacent block circuits, the data output circuit included in one of the block circuits is provided. A first data input terminal of It is achieved by a semiconductor integrated circuit which is able ゝ connects the data output terminal of the data output circuit included in the other of the block circuit each other.

In the above structure, the upper conductive layer may be a bump, may be arranged along the periphery of the semiconductor chip, may be plurally arranged on the semiconductor chip, and may be a semiconductor chip. A plurality of them may be arranged in a matrix.

[0012]

In the pad according to the prior art, since the boundary scan chain is established without the interposition of the pad, the area inside the pad or immediately adjacent to the pad is removed from the boundary scan chain. The function test can be performed even if the probe is not in contact with all of the pads, and as a reflection effect, even if there is a conduction failure or short circuit in the pad or in the immediate area of the pad, it can be easily overlooked. was there. However, in the pad according to the present invention, since the boundary scan chain is established only via the pad, if there is a conduction failure, short circuit, or the like in the area immediately adjacent to the pad, the boundary scan chain is not established, and immediately Be discovered.

As a reflection effect, the pad according to the present invention can be densely arranged not only around the semiconductor chip but also in any area.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device pad and a semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. First Embodiment Lower Conductive Layers (31) and (32) Connected to Two Logic Circuits
And an upper / lower conductor layer (34) for shortening the two lower conductor layers (31) and (32) and a pad for a semiconductor device for an input / output circuit (corresponding to claim 1). 1 is a field insulating film, and 31 and 32 are
Each is a lower conductive layer connected to a different logic circuit. 33 is an insulating film, 34 is a lower conductive layer 31
An upper conductor layer for short-circuiting 32, and a surface stabilizing film 35.

A method for testing a semiconductor device on which the pad is mounted will be described. Reference numeral 4 in FIG. 2 denotes a pad according to the present invention, which transmits and receives signals to and from the semiconductor device.

Reference numeral 21 denotes a boundary scan FF, which is connected to a scan-in SI terminal connected to a scan-out terminal of a boundary scan FF adjacent to one side and a scan-in terminal of a boundary scan FF adjacent to the other side. It has a scan-out terminal SO, a data terminal D for taking in data into the boundary scan FF, a terminal CK for inputting a clock signal of a system circuit, and a test clock terminal TCK. 22 is a selector. 23 is an output circuit, which outputs a signal output from the logic circuit shown with a L _1. 24 is an input circuit, for inputting a signal to be inputted to the logic circuit illustrated with a L _2.

In order to show a functional test of a semiconductor device using such a circuit, it is necessary to connect probes (not shown) to all pads 2 as long as a boundary scan chain is established. Not reachable.

In addition, since the boundary scan chain passes through the pad 4, if there is a conduction failure or short circuit in the pad or in the area immediately adjacent to the pad 4, the boundary scan chain is not established. Can be found immediately.

The test process will be described in more detail. I. By taking some means, the data of “1” is set in an arbitrary boundary scan FF via the boundary scan chain (via the terminal SI). B. When the set data is output through the output circuit 23, the data is input through the pad 4 and the input circuit 24, and the data is taken into the boundary scan FF. C. Via the boundary scan chain (terminal SI
Next, the data read into the boundary scan FF is read by setting the data of "0".

At this time, if a non-connection state exists in the pad 4 or in a region immediately adjacent to the pad 4, the input circuit 24
Is fixed to either "1" or "0" and becomes immobile, and the defect is immediately found.

As described above, in the semiconductor integrated circuit in which the pad according to the present embodiment is used, it is not necessary to bring the probe into contact with all the pads in order to test the continuity in the pad or in the area immediately adjacent to the pad. Therefore, the pads can be densely distributed on the semiconductor chip in an arbitrary arrangement.

Second Embodiment A pad for a semiconductor device for an input / output circuit according to claim 1, wherein the upper conductor layer (34) is a bump (36) (corresponding to claim 2). , 1 is a field insulating film, and 31 and 32 are
Each is a lower conductive layer connected to a different logic circuit. 33 is an insulating film, 36 is a lower conductive layer 31
This is a bump that shorts 32.

The function of this embodiment is exactly the same as that of the first embodiment. Third Embodiment A pad for a semiconductor device for an input / output circuit according to claim 1 or 2 which is connected to a plurality of input / output wirings (corresponding to claim 3). Field insulation film, 37, 38, 39
Reference numeral 40 denotes wiring connected to different logic circuits. 31 and 32 are lower conductor layers according to the gist of the present invention, and 34 is an upper conductor layer according to the gist of the present invention, and short-circuits the lower conductor layers 31 and 32. 35 is a surface stabilizing film.

There is no particular difference from the above embodiment, except that an external signal can be selectively input to a large number of logic circuits and a signal can be selectively output to the outside from a large number of logic circuits. The functions according to the gist of the present invention (a conductive test inside the pad or a region near the pad can be performed without connecting the probe to the pad) are exactly the same.

Fourth Embodiment A semiconductor integrated circuit in which a plurality of pads for an input / output circuit semiconductor device according to claim 1, 2 or 3 are dispersedly arranged on a semiconductor chip 5. Circuit (corresponding to claim 4) See FIG. 5 When the above pad 4 is used, it is not necessary to contact the probe with all of the pads for the test, so that the pad spacing can be freely selected as far as bonding is possible. Therefore, the semiconductor chip surface can be used freely as shown in the figure.

Fifth Embodiment A plurality of pads for a semiconductor device for an input / output circuit according to claims (1), (2) or (3) are formed in a matrix on a semiconductor chip (5). Semiconductor Integrated Circuit (Corresponding to Claim 5) See FIG. 6 In the fifth embodiment, it is reasonable to arrange the pads 4 in a matrix as shown.

Sixth Embodiment A lower conductive layer (31) (32) for a pad for a semiconductor device for an input / output circuit according to the above (1), (2) or (3).
The input circuit (24) and the protection circuit (25) are connected to one of them, and the output circuit (23) is connected to the other of the lower conductive layers (31) and (32).
And a protection circuit (25) connected to the semiconductor integrated circuit (corresponding to claim 6). Referring to FIG. 7, in the drawing, reference numeral 25 denotes a protection circuit, and a logic circuit or the like (not shown) is provided for preventing intrusion from the outside. To protect. Also in the semiconductor integrated circuit according to the present embodiment, it is not necessary to contact the probe with all of the pads in order to conduct a continuity test or the like in or immediately adjacent to the pad. Needless to say, the layout can be made as appropriate.

[0028]

As described above, in a semiconductor integrated circuit according to the present invention, in a semiconductor integrated circuit in which block circuits are connected to each other to form a boundary chain structure, a region near a pad has poor conduction or poor conduction. When there is a fault location such as a short circuit, the fault location can be easily found without having to contact the probe to all pads.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device pad according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a test circuit of an input / output circuit having a pad for a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device pad according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device pad according to a third embodiment of the present invention.

FIG. 5 is a plan view of a semiconductor device pad according to a fourth embodiment of the present invention.

FIG. 6 is a plan view of a semiconductor device pad according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram of a pad for a semiconductor device according to a sixth embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device pad according to the related art.

FIG. 9 is a plan view of a semiconductor device according to the related art.

FIG. 10 is a block diagram of a test circuit of an input / output circuit having a pad for a semiconductor device according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Field insulating film 11 Lower conductive layer according to conventional technology 12 Insulating film 13 Upper conductive layer according to conventional technology 14 Surface stabilizing film 2 Pad according to conventional technology 21 Boundary scan FF 22 Selector 23 Output circuit 24 Input circuit 31 Lower conductor film according to the present invention 32 Lower conductor layer according to the present invention 33 Insulating film 34/36 Upper conductor layer according to the present invention 35 Surface stabilizing film 4 Pad according to the present invention 37/38/39/40 Wiring 5 Semiconductor chip

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/06 311 H01L 27/04 T (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/60 H01L 21 / 66

Claims (5)

(57) [Claims] A first data input terminal, a second data input terminal, and a data output terminal, wherein the first and second data input terminals are received from the data output terminal in response to a clock signal. A data output circuit that outputs an output signal corresponding to any one of the following input signals: a first lower conductive layer connected to the second data input terminal; and a second lower conductor layer connected to the data output terminal. A plurality of block circuits each including: a lower conductive layer; and an upper conductive layer that short-circuits the first lower conductive layer and the second lower conductive layer when an external signal is input. A semiconductor integrated circuit arranged, wherein, in two adjacent block circuits, the first one of the data output circuits included in one of the block circuits
And a data input terminal of the other block circuit and the data output terminal of the data output circuit included in the other block circuit are connected to each other. 2. The semiconductor integrated circuit according to claim 1, wherein said upper conductor layer is a bump. 3. The semiconductor integrated circuit according to claim 1, wherein said upper conductive layer is disposed along a periphery of a semiconductor chip. 4. The semiconductor device according to claim 1, wherein a plurality of said upper conductive layers are dispersedly arranged on a semiconductor chip.
A semiconductor integrated circuit as described in the above. 5. The semiconductor integrated circuit according to claim 1, wherein a plurality of said upper conductive layers are arranged in a matrix on a semiconductor chip.