JP3159178B2 - Jitter absorption circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator, an LP
F (low-pass filter) and VCO (voltage controlled oscillator)
More particularly, the present invention relates to a method of absorbing jitter superimposed on a transmission line clock and a method of monitoring a reproduction clock frequency.

[0002]

2. Description of the Related Art Since a radio base station for mobile communication is required to have high-precision radio frequency stability, it is necessary to provide an oscillator internally for generating a high-precision radio frequency. In addition, since various compensating means are provided to stabilize the frequency, the apparatus becomes large and expensive.

Therefore, for miniaturization and simplification, a high-precision transmission line clock is extracted from transmission line data without having such a high-precision oscillator inside, and a clock synchronized with this clock is wirelessly transmitted. A method is used in which a signal is reproduced inside a base station and used as a reference clock of a radio frequency.

In this case, jitter is generally superimposed on the transmission line clock. Therefore, in order to obtain a highly accurate clock, it is necessary to remove the influence of the jitter on the frequency stability of the reproduced clock. .

FIG. 4 is a block diagram showing an example of a conventionally used jitter absorbing circuit. In this conventional example,
VCO 33 and reference clock extracted from transmission line data
The reproduced clock generated in is input to the phase comparator 31. Generally, the reference clock is obtained by superimposing jitter on a clock having high frequency stability.

[0006] After the output of the phase comparator 31 is smoothed by the LPF 32, it is input to the VCO 33, and a reproduced clock is generated from the VCO 33 in accordance with the input level.
That is, in this example, the fluctuation due to the jitter superimposed on the reference clock is removed by the LPF 32.

[0007]

In the above conventional example, the frequency component of the jitter sufficiently higher than the cutoff frequency of the LPF 32 can be absorbed, but the lower frequency component of the jitter passes through the LPF 33 and thus cannot be removed. Without
There is a problem that the gradual frequency fluctuation appears as it is in the frequency fluctuation of the reproduced clock.

In order to remove the lower frequency component of the jitter, it is necessary to lower the cutoff frequency of the LPF 32. However, if the cutoff frequency of the LPF 32 is lowered, the time until the initial synchronization with the reference clock is obtained. Since the time becomes long, the cutoff frequency cannot be set too low.

Further, in this conventional example, there is a problem that even if a reproduced clock has a frequency fluctuation exceeding an allowable amount, a maintenance person cannot know the fact.

In view of the above problems, an object of the present invention is to provide a jitter elimination system capable of absorbing a low-frequency jitter and a fluctuation due to a long-period wander while keeping the clock initial pull-in time short. It is in.

Another object of the present invention is to provide a method for generating an alarm when the fluctuation of the reproduction clock frequency exceeds an allowable value.

[0012]

SUMMARY OF THE INVENTION The present invention provides a phase comparator,
In a clock synchronization circuit that outputs a reproduction clock synchronized with a transmission line clock using an LPF and a VCO, the output of the LPF is statistically monitored, and reproduction using jitter or a long-period wander component below the cutoff frequency of the LPF is performed. It is characterized in that control means for providing a control signal to the VCO for removing fluctuations of the clock frequency is provided.

[0013] More specifically, the control means is configured to control the LPF.
An A / D converter for converting the output into digital data, and inputting the digital data, and statistically monitoring the LPF output to detect low frequency jitter and wander components, and to remove these jitter and wander components. CPU that outputs control data for removal (Central Proces
sing unit (central processing unit) and a D / A converter for converting the control data into an analog signal and supplying the analog signal to the VCO.

In the present invention, the output level of the LPF is determined by the CPU.
When a long-period wander fluctuation that cannot be absorbed by the LPF is detected, the wander fluctuation is removed by outputting the average level to the VCO. That is, LPF and C
Since the PU is used in combination, it is not necessary to lower the cutoff frequency of the LPF in order to remove the long-period wander component.
It can be removed by monitoring with U and outputting the monitoring result as a control signal to the VCO.

At the time of initial clock pull-in, such as when the power is turned on, the CPU keeps the output level of the LPF unchanged by the CPU.
By outputting to the CPU, a relatively short initial pull-in time determined by the cut-off frequency of the LPF can be maintained.
By giving the average value of the values set to the CO as the initial value, it is possible to reduce the redrawing time.

Further, the CPU monitors the fluctuation of the level of the control signal output to the VCO. If the fluctuation width exceeds the allowable value, the CPU notifies the alarm generator of the abnormal fluctuation of the reproduction clock frequency. Thus, the maintenance person is notified of the abnormal fluctuation of the reproduction clock frequency.

[0017]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a reference clock extracted from transmission path data and a reproduced clock generated by the VCO 6 are input to a phase comparator 1. Generally, jitter may be superimposed on the reference clock.

The output of the phase comparator 1 is smoothed by the LPF 2 and converted into digital data by the A / D converter 3. The CPU 4 reads the digital data and outputs control data according to the level. Here, the component that changes in the short cycle of the jitter is absorbed by the LPF 2, and the long cycle jitter or the wander component that cannot be absorbed is absorbed by the CPU 4.

From the CPU 4, a level from which short- and long-period jitter fluctuation has been removed, that is, an average value of the fluctuation width, is output as control data, converted into an analog signal by the D / A converter 5, and input to the VCO 6. . The VCO 6 generates a reproduced clock having a frequency corresponding to the input level.

At the time of initial pull-in of the reference clock,
The CPU 4 inputs the output level of the LPF 2 to the VCO 6 as it is, and achieves a short initial pull-in time by the LPF 2 alone. Also, at the time of re-pulling, the CPU 4 previously outputs V
By giving the average value of the values set to CO6 as the initial value, the redrawing time is reduced.

The CPU 4 sets L from the end of the initial pull-in.
Monitoring of the PF2 output at a certain sampling period is started. The sampling period is set to such an extent that the minimum period fluctuation of the jitter fluctuation that cannot be absorbed only by the LPF 2 can be sufficiently monitored. Therefore, there is no need for the CPU 4 to monitor following the fast jitter fluctuation that can be absorbed by the LPF 2,
Since the level monitoring and averaging may be performed at relatively long time intervals, the processing load on the CPU 4 does not become heavy.

At the same time, the CPU 4 monitors the level of the control signal to the VCO 6, and if the level fluctuation is larger than the allowable value, that is, if the reproduction clock frequency fluctuation exceeds the allowable value, the CPU 4 notifies the alarm generating unit 7 and issues an alarm. The maintenance person can recognize the abnormality by the alarm from the generating unit 7.

Next, the operation of the present invention will be described with reference to FIG. 1 and an example of the LPF output level in FIG.

First, during the initial pull-in time Ts of the reference clock such as when the power is turned on, the CPU 4 monitors the output level of the LPF 2 at a sufficiently short sampling interval T0 and sequentially inputs a level equal to the read level to the VCO 6. Go. Therefore, during this period, the circuit of FIG.
An operation equivalent to a circuit in which the output of the LPF 2 is directly input directly to the VCO 6 without the / A converter and the CPU is performed, and the pull-in is completed in a short time determined by the relatively high cutoff frequency of the LPF 2.

The optimum time Ts up to the end of the pull-in can be obtained by, for example, an experiment, and an appropriate sampling period T0 can also be determined by an experiment. Also, at the time of re-attachment after synchronization is once lost, VC
As the initial value of the control signal level to O6, the average value of the control signal level given by the CPU 4 when the synchronization was previously maintained is used, thereby shortening the re-pulling time.

Next, the initial pull-in or re-pulling time T
After s has elapsed, the CPU 4 monitors the output level of the LPF 2 at a sampling interval T1 longer than T0, for example,
The average value of a plurality of sampling values is sequentially obtained and VCO 6
Outputs control data to In addition, the LPF is provided at intervals longer than a certain time T, for example, at intervals shown by Ta and Tb in FIG.
2. When a peak-to-peak appears at the output level and the fluctuation range exceeds an allowable fluctuation range D, for example, in the case of Da and Db in FIG. . That is, La +
It outputs the level of Da / 2 and Lb + Db / 2.

As a result, it is possible to suppress fluctuations in the control output level to the VCO 6, that is, fluctuations in the reproduction clock frequency. The sampling interval T1 is determined by an experiment using a circuit in which the output of the LPF 2 is directly connected to the input of the VCO 6, for example.
It can be determined by measuring the minimum jitter fluctuation period that cannot be absorbed by the LPF 2 alone, and the allowable maximum fluctuation width D can be determined from the allowable frequency fluctuation width of the reproduced clock.

The CPU 4 simultaneously performs the above operation and the VC
The control output level fluctuation to O6 is monitored, and when the fluctuation amount exceeds a certain allowable value, that is, when the fluctuation of the frequency of the reproduced clock output from the VCO 6 exceeds a predetermined value, the fact is notified to the alarm generation unit 7. Notice. The alarm generator 7 informs the maintenance person of the abnormality by an appropriate method, for example, by displaying a message on a maintenance terminal.

FIG. 3 is a block diagram showing another embodiment of the present invention. In this embodiment, the output levels from a plurality of LPFs are monitored by parallel processing of the same CPU, and the levels after jitter fluctuation absorption are input to a plurality of VCOs to obtain a plurality of reproduced clocks simultaneously. Is also applied.

That is, the phase comparator 11, the LPF 12,
Clock Synchronization Circuit Consisting of VCO 13 and Phase Comparator 1
The control data for the clock synchronization circuit including the LPF 20, the LPF 20, and the VCO 21 are processed in parallel by the same CPU 15 and output to the respective clock synchronization circuits.
The specific control method is the same as that of the embodiment of FIG. 1, and the description thereof is omitted.

[0031]

According to the present invention, since the average value of the fluctuation is calculated by the CPU and input to the VCO, jitter having a long fluctuation period which cannot be absorbed by the LPF can be absorbed.

Also, since the CPU only needs to monitor the long-period jitter component that cannot be absorbed by the LPF, the sampling interval can be made relatively long, and the CPU processing load does not become heavy. L
By directly inputting the output level of the PF to the VCO and using the average value of the previous control signal levels as the initial value at the time of re-pulling, a short pull-in time can be maintained.

Further, according to the above configuration, the CPU can monitor the fluctuation of the reproduction clock at the same time as suppressing the fluctuation of the reproduction clock, so that the maintenance person can be easily notified of the abnormal fluctuation of the reproduction clock frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 11, 19, 31 Phase comparator 2, 12, 20, 32 LPF (low-pass filter) 3, 14, 17 A / D converter 4, 15 CPU 5, 16, 18 D / A converter 6, 13, 21, 33 VCO (Voltage Controlled Oscillator) 7, 22 Alarm generator

Claims (6)

(57) [Claims] 1. A clock synchronization circuit for outputting a reproduction clock synchronized with a transmission line clock using a phase comparator, an LPF and a VCO, wherein the A / D converter converts the LPF output into digital data.
And the LPF output by inputting the digital data.
Monitor the power level and calculate the average
A CPU that outputs the control data as an analog signal
And a D / A converter for converting the voltage to
Jitter circuit characterized in that there. 2. The method according to claim 1, wherein the CPU is adapted to execute a clock initial pull-in operation.
Is to use the output level of the LPF as control data
To the VCO, and at the time of re-pulling, the CPU
From the average value of the value previously set to the VCO
2. The jitter absorbing circuit according to claim 1, further comprising means for giving value data . 3. The system according to claim 1 , wherein said CPU controls output to said VCO.
Monitor the fluctuation of the control signal level, and the fluctuation range exceeds the allowable value.
The alarm clock, the recovered clock frequency
2. The jitter absorbing circuit according to claim 1, further comprising means for notifying an abnormal fluctuation of the jitter. (4)Each is a phase comparator, LPF and VCO
The playback clock synchronized with each transmission line clock is provided.
In a plurality of clock synchronous circuits that output respectively, Each of the plurality of LPF outputs is converted into digital data.
A plurality of A / D converters to be converted, and the plurality of digital data
Data, and output the plurality of LPF output levels by parallel processing.
Monitor each bell and calculate its average sequentially
A common CPU that outputs the control data as
The control data is converted into analog signals, and
Equipped with a plurality of D / A converters for supplying CO
To A jitter absorbing circuit characterized by the above. 5. The CPU according to claim 1, further comprising:
Is the control data without changing the output levels of the plurality of LPFs.
Output to each of the multiple VCOs as a
At the time of setting, the CPU previously set each VCO
The average value of the values was used as the initial value data for each VCO.
5. A method according to claim 4, further comprising:
The jitter absorbing circuit as described. 6. The CPU outputs to the plurality of VCOs.
Monitor the control signal level fluctuations
If the width exceeds the allowable value, play back the alarm
The jitter absorbing circuit according to claim 4, further comprising means for notifying an abnormal change in a clock frequency .