GB2360152A

GB2360152A - Control circuit arrangements

Info

Publication number: GB2360152A
Application number: GB0005620A
Authority: GB
Inventors: Kevin Trevor Talbot
Original assignee: Bayerische Motoren Werke AG; MG Rover Group Ltd
Current assignee: Bayerische Motoren Werke AG; MG Rover Group Ltd
Priority date: 2000-03-10
Filing date: 2000-03-10
Publication date: 2001-09-12
Also published as: GB0005620D0

Abstract

A control circuit 100 includes a receiving means arranged in use to receive a message signal. A method is provided for synchronising a clock signal of a clock means (VCO) 180 with the frequency of the message signal. The method includes receiving the message signal (data bus) and comparing the frequency of the VCO 180 with the frequency at which the message signal was sent. An error signal Se is produced which is indicative of the difference between the frequencies and a correction Vc is then applied to the VCO 180 so as to bring its frequency towards the frequency of the message signal. The method further includes recognising the message signal as valid by measuring the width of the pulses of the received signal and by filtering out implausible messages. The clock means runs in an open loop arrangement until the message signal has been received and the associated signal derived.

Description

2360152 Control Circuit Arrangements This invention relates to control

circuits and in particular to a control circuit which includes a receiving means arranged in use to receive a message signal.

It is known to provide a control circuit in which clock synchronisation is required. Examples of prior art arrangements in this general field can be seen in US 3,806,822 and US 5,502,75 1.

It is an object of this invention to provide an improved control circuit.

Accordingly, the invention provides, in a control circuit that includes a receiving means arranged in use to receive message signals, a method of synchronising a clock frequency of a clock means of said receiving means with a clock frequency of a said message signal, the method including the steps of.

a) receiving a said message signal; b) comparing the substantially instant frequency of said clock means with the frequency of said received message signal so as to produce an error signal which is indicative of a difference in frequency therebetween; and c) applying as necessary a correction to said clock means in such a manner that said correction reduces said difference in frequency, said correction being based on said error signal.

The method may include running said clock means in an open loop arrangement until a said message signal has been received and an associated said 20 error signal derived.

The method may include reducing said difference in frequency in an iterative process using substantially successive message signals to derive substantially successive error signals.

The method may include deriving a scaling factor which is indicative of said difference in frequency.

The method may include using said scaling factor to provide compensation for drift in either or both of said frequencies.

The method may include recognising a said message signal as a valid said message signal by measuring the width of the pulses of received messages and by 10 filtering out implausible message signals.

The method may include providing one or more synchronisation messages to said receiving means, such synchronisation messages being arranged to provide to the receiving means an indication of a said clock frequency of a said message signal so that associated said error signals can be produced in order to place andlor maintain the clock frequencies in synchronisation. A said synchronisation message may comprise a dummy message signal and may comprise a substantially continuous series of bits of a predetermined format, such as a string of ones and zeros.

The invention also provides a control circuit that includes a receiving means arranged in use to receive message signals, the control circuit being arranged to synchronise, in accordance with the method of the invention, a clock frequency of a clock means of said receiving means with a clock frequency of a said message signal. Said clock means may comprise a voltage controlled oscillator (VCO).

The invention will now be described by way of example only and with reference to the accompanying drawings, in which:

Figure 1 is a schematic diagram of a basic circuit of a phase locked loop (PLL); Figure 2 illustrates a modification to the circuit of Figure 1; Figure 3 is a schematic diagram of a control circuit arrangement according to an embodiment of the invention; and Figure 4 is a more detailed schematic diagram of part of the control circuit of Figure 3.

Referring first to Figures 1 and 2, in an example of the basic circuit of a phase locked loop (PLL) 10, the reference signal may be for example at 100 kHz and the signal out at 16 MHz. A frequency divider 12 divides by 160 so that the divided output signal which is fed into a phase detector 14 is at the same frequency as the reference signal when the loop is locked.

The phase detector 14 produces a voltage V,. which is representative of any phase error between the reference signal and the signal out. The error voltage signal Ve produced by the phase detector 14 is passed through a low pass filter 16 into a voltage controlled oscillator (VCO) 18.

It can be seen that if the WO 18 starts to run too quickly, the phase of the reference signal will lag behind it and the output V, of the phase detector 14 will fall. This will cause the frequency of the WO 18 to drop. It will be appreciated that the opposite occurs if the WO 18 starts to slow down. Arrangements simflar to the one shown in Figure 1 are believed to be used in connection with some prior art micro-controllers.

Referring now in particular to Figure 2, it would be possible to disconnect the output of the phase detector 14 for a short period, during which time the capacitors C of the RC low pass filter 16 will hold the control voltage, and to later reconnect the phase detector 14 before the drift has exceeded predetermined 5 limits.

Referring now also to Figures 3 and 4, this invention uses the principles of the arrangement mentioned above in relation to Figures 1 and 2, but uses them in a digital form. This makes the control circuit particularly suitable for use in a slave unit 20 which communicates with a master unit 30 along a bus 40, which bus 40 10 may comprise for example a controller area network (CAN) bus.

The master unit 30 includes an external resonator 32, which provides it with its timing information. The slave unit 20, however, is not provided with such an external resonator 32 and calibrates all of its timing. functions using a voltage controlled oscillator (VCO) 180 of its phase lock loop (PLL) 100.

The micro-controller (not shown further) of the slave unit 20 initiates itself with the WO 180 running open loop and producing a processor clock signal in a default mode, in which a default voltage Vdf is applied to the WO 180. The default mode is maintained until an analogue correction voltage V, is applied to the default voltage Vdf.

Take now the case of a recognisable message signal being received on the data bus 40. This message, in the form of bus data, is recognised using pulse width measurement, which measures the width of all signals arriving along the data bus.

The pulse width measured data is filtered by selectively switching it using a hardware and/or software function 110. This function 110 filters out non- interacting data by, for example, identifying the preamble leading up to bits which are to be used by the error calculation (see below).

The error calculation is performed by comparing the pulse width measured bus data with the substantially instant frequency of the W0 180. If there is a frequency misfit between the message signal and the current processor clock frequency as derived from the WO 180, e.g. the message appears to be too short or too long, the error calculation produces an error signal Se which indicates that the frequency of the WO 180 should be increased or reduced as necessary to produce a fit.

The error signal & is in the form of a digital representation of the analogue error which exists between the frequency of the WO 180 and the frequency at which the bus data was clocked on its transmission. The error signal S, then passes through a digital-to- analogue converter 120 and is converted into the analogue correction voltage M:.

In this manner, it can be seen that initially the slave 20 runs open loop off the WO 180 and waits for a bus message (bus data). It calibrates its WO clock by measuring bits of the received message. It can thus be seen that, over a number of received bits, the correct frequency is achieved in an iterative process and the scaling of the WO control voltage against message frequency is found. The scaling factor thus derived can also be used to correctly compensate future drift measured against the timing of the master 30.

One advantage of this invention is that it is possible to successfully synchronise a slave 20 to the timing of a master 30 without needing to know the clock frequency of the master 30. This means, for example, that it is possible to save the expense which might otherwise prove necessary to provide a slave 20 with its own resonator.

ln a variation of the invention, it would also be possible to provide a synchronisation signal to the slave 20 in such a manner that it is put into synchronisation with the master 30 before a message signal is received, or if already synchronised is maintained in that condition. Such a synchronisation signal might comprise for example a dummy message and/or a string of ones and zeros which might be continuous. ln this manner, error signals are generated often enough to achieve and/or maintain synchronisation of clock frequencies. 10 This might save synchronisation time.

Claims

1. In a control circuit that includes a receiving means arranged in use to receive message signals, a method of synchronising a clock frequency of a clock means of said receiving means with a clock frequency of a said message signal, the method including the steps of..

a) receiving a said message signal; b) comparing the substantially instant frequency of said clock means with the frequency of said received message signal so as to produce an error signal which is indicative of a difference in frequency therebetween; and c) applying as necessary a correction to said clock means in such a manner that said correction reduces said difference in frequency, said correction being based on said error signal-

2. A method according to Claim 1, including running said clock means in an open loop arrangement until a said message signal has been received and an associated said error signal derived.

3. A method according to Claim 1 or Claim 2, including reducing said difference in frequency in an iterative process using substantially successive message signals to derive substantially successive error signals.

4. A method according to any preceding claim, including deriving a scaling factor which is indicative of said difference in frequency.

5. A method according to Claim 4, including using said scaling factor to provide compensation for frequency drift.

6. A method according to any preceding claim, including recognising a said message signal as a valid said message signal by measuring the width of the pulses of received messages and by filtering out implausible message signals.

A method according to any preceding claim, including providing one or more synchronisation messages to said receiving means, such synchronisation messages being arranged to provide to the receiving means an indication of a said clock frequency of a said message signal so that associated said error signals can be produced in order to place andlor maintain the clock frequencies in synchronisation.

8. A method according to Claim 7, a said synchronisation message comprising a dummy message signal.

9. A method according to Claim 7 or Claim 8, a said synchronisation message comprising a substantially continuous series of bits of a predetermined format.

10. A method of synchronising a clock frequency substantially as described herein and with reference to the accompanying drawings.

11. A control circuit that includes a receiving means arranged in use to receive message signals, the control circuit being arranged to synchronise, in accordance with the method of any preceding claim, a clock frequency of a clock means of said receiving means with a clock frequency of a said message signal.

12. A control circuit according to Claim 10, said clock means comprising a voltage controlled oscillator (VCO).

13. A control circuit substantially as described herein and with reference to the accompanying drawings.