JP3156780B2 - Semiconductor inspection apparatus and inspection method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor inspection apparatus and an inspection method thereof.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional semiconductor inspection device.

The pass signal 11 and the fail signal 12 output from the test result transmitting unit 4 are output based on the test result.
Is input to the device classification control unit 8 of the handler 5.
The device classification controller 8 receives the pass signal 11 and the fail signal 12 and classifies the device into a non-defective product and a defective product.

[0004]

According to the above-mentioned prior art, the device classification control unit receives a pass signal and a fail signal and classifies the device into a non-defective product or a defective product, but the pass signal and the fail signal malfunction due to some trouble. In this case, there is a disadvantage that misclassification occurs in the handler.

An object of the present invention is to provide a semiconductor inspection apparatus and an inspection method thereof for preventing erroneous classification of LSI.

[0006]

A semiconductor inspection apparatus according to the present invention comprises a tester and a handler. The tester receives a test start signal from the handler and controls the entire tester. The test result sending unit that receives the test result and outputs the test result to the outside, and compares the test result of the tester control unit with the output signal of the test result sending unit, and outputs an error signal if they do not match. A handler control unit for controlling the entire handler in response to a test end signal and an error signal of the tester, and a device classification control for classifying devices based on a pass signal and a fail signal of the tester And a part.

[0007] The handler is means for transporting the LSI from the storage tray to the tester by an operator's test start operation, and stores the tested LSI in the error storage tray when an error signal is received to notify the operator and temporarily suspend the operation. The handler control unit has means for outputting a test start signal to the tester control unit at a predetermined time, and the tester control unit starts the LSI test in response to the test start signal, Means for outputting a test end signal indicating the end of the test at the time of the test, and when the test is interrupted by receiving the error signal, the operator checks the tester, performs necessary trouble-shooting, performs a test start operation, and performs a predetermined time. Receives the test start signal and clears the error signal by the control signal.
Means for restarting the test, wherein the test result sending unit comprises:
The tester control unit includes means for receiving a control signal from the tester control unit and outputting a pass signal for a pass or a fail signal for a fail at a predetermined time to the device classification control unit at a predetermined time according to an LSI test result. The control signal may be compared with the pass signal and the fail signal, and if the test results do not match, an error signal may be output to the handler control unit to request the interruption of the test.

[0008] Further, it is composed of a tester and a handler,
The tester has a tester control unit that controls the entire tester in response to a test start signal of the handler, a test result sending unit that receives the test result of the tester control unit and outputs the test result to the outside, and a test result comparison unit. The handler has a handler control unit that controls the entire handler in response to the test end signal and the error signal of the tester, and a device classification control unit that classifies devices based on the pass signal and the fail signal of the tester. The test result comparison unit compares the test result of the tester control unit with the pass signal and the fail signal of the tester output from the device classification control unit, and outputs an error signal when they do not match. Is also good.

According to the inspection method of the semiconductor inspection apparatus of the present invention, the tester control section controls the entire tester by receiving a test start signal of the handler, and the test result transmission section receives the test result of the tester control section. A step of outputting test results to the outside, a step of classifying devices based on a pass signal and a fail signal of the tester by a device classification control unit, and a test result of the tester control unit and a test result by a test result comparison unit. The method includes a step of comparing the output signal of the sending section and outputting an error signal when they do not match, and a step of controlling the entire handler by receiving the error signal and the test end signal of the tester by the handler control section.

A step of transferring the LSI from the storage tray to the tester by the handler by a test start operation by the operator; a step of outputting a test start signal to the tester control section at a predetermined time by the handler control section; Receiving a test start signal by the unit, starting a test of the LSI, and receiving a control signal of the tester control unit by the test result sending unit, and based on the test result of the LSI, a pass signal if a pass and a fail signal if a fail. At the time of outputting to the device classification control unit, and comparing the control signal of the tester control unit with the pass signal and the fail signal by the test result comparison unit. If the test results do not match, the error signal is handled by the handler. Output to the control unit to request the test to be interrupted. After the test LSI is stored in the error storage tray, the operator is notified and the operation is temporarily stopped, and when the test is interrupted by receiving the error signal, the operator checks the tester and performs necessary trouble-shooting. Performing a test start operation, receiving a test start signal at a predetermined time by a tester control unit, clearing an error signal by a control signal, and restarting the test, and terminating the test at a predetermined time by the tester control unit. And outputting a test end signal.

The tester control section controls the entire tester in response to a test start signal of the handler, and the test result sending section receives the test result of the tester control section and outputs the test result to the outside. A step of classifying devices based on the pass signal and the fail signal of the tester by the device classification control unit, and a test result comparison unit and the test result of the tester control unit and the path of the tester output from the device classification control unit. Comparing the signal and the fail signal, and when they do not match, outputting an error signal, and controlling the entire handler by receiving the error signal and the test end signal of the tester by the handler control unit. Is also good.

A semiconductor inspection apparatus according to the present invention checks whether a pass signal and a fail signal indicating test results are correctly output, and prevents erroneous classification of LSI.

The pass signal and the fail signal are input to the test result comparing unit, and it is checked whether the correct pass signal and the fail signal are output from the test result transmitting unit. Thereby, if the test result does not match, an error signal is output and the test can be interrupted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment of the Invention) A first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a tester 1 includes a handler 5
A tester control unit 2 that receives the test start signal 9 and controls the entire tester; a test result sending unit 4 that receives the test result of the tester control unit 2 and outputs the test result to the outside;
It has a test result comparison unit 14 that compares the test result of the tester control unit 2 with the output signal of the test result sending unit 4 and outputs an error signal 13 when they do not match.

The handler 5 receives the test end signal 10 and the error signal 13 from the tester 1 and controls the entire handler, and classifies the devices based on the pass signal 11 and the fail signal 12 of the tester 1. It has a device classification control unit 8 for performing.

First, the operation of this embodiment will be described with reference to the block diagram of FIG. 1 and the timing chart of FIG.
Handler 5 is set to LSI by operator's test start operation
Is transferred from the storage tray to the tester (not shown), and the handler controller 6 outputs a test start signal 9 to the tester controller 2 at time T0 in FIG.

The tester control unit 2 receiving the test start signal 9 starts the test of the LSI, and outputs a test end signal 10 indicating the end of the test at time T1.

The test result sending unit 4 receives the control signal 3 from the tester control unit 2 and outputs a pass signal 11 for a pass and a fail signal 12 for a fail at time T based on the test result of the LSI.
At 1, it outputs to the device classification control unit 8 of the handler 5.

At time T1 in FIG. 4, if a failure occurs in the test result sending unit 4 and the signals of the pass signal 11 (broken line) and the fail signal 12 (broken line) are interchanged and output, the test result comparing unit 14 Then, the control signal 3 of the tester control unit 2 is compared with the pass signal 11 and the fail signal 12, and if the test results do not match, an error signal 13 (dashed line) is output to the handler control unit 6. , Requesting test suspension.

Upon receiving the error signal 13, the handler 5 stores the tested LSI in the error storage tray, notifies the operator with a buzzer or the like, and suspends the operation.
(Not shown) The operator checks the tester and performs necessary trouble handling, and then performs a test start operation.

Referring to FIG. 4, a test start signal 9 is output at time T2, the tester control unit 2 clears the error signal 13 by the control signal 3, and the test is restarted.

(Second Embodiment of the Invention) The second embodiment of the present invention
An embodiment will be described with reference to the drawings.

In FIG. 2, the device classification control unit 8
The pass signal 11 and the fail signal 12 output from the test result sending unit 4 are directly used as the test result comparing unit 14 of the tester 1.
And outputs the pass signal 16 and the fail signal 15.

In this embodiment, the signal received by the tester is received by the handler, and the received signal is returned to the original state for confirmation. Even defects can be detected.

[0026]

As described above, according to the present invention, the pass signal and the fail signal are inputted to the test result comparing section, and it is checked whether or not the correct pass signal and the fail signal are outputted from the test result transmitting section. Therefore, even if the pass signal and the fail signal output to the erroneous operation malfunction due to some trouble, the erroneous classification in the handler can be prevented.

The reason is that a comparison circuit for confirming the output pass signal and fail signal is provided, and if a failure occurs, an error signal is output and the handler is stopped.

The device classification control section outputs the pass signal and the fail signal output from the test result sending section to the test result comparing section of the tester as it is as a pass signal and a fail signal, thereby converting the signal output by the tester. Since the handler receives and returns the received signal and confirms it, it is possible to detect not only the failure of the test result sending unit but also the failure of the cable and the connector between the equipment.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor inspection device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a semiconductor inspection device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional semiconductor inspection apparatus.

FIG. 4 is a timing chart of an inspection method of the semiconductor inspection device according to the first embodiment of the present invention.

[Explanation of symbols]

 1 Tester 2 Tester control unit 3, 7 Control signal 4 Test result sending unit 5 Handler 6 Handler control unit 8 Device classification control unit 9 Test start signal 10 Test end signal 11, 16 Pass signal 12, 15 Fail signal 13 Error signal 14 Test Result comparison section

Claims (2)

(57) [Claims] 1. A tester comprising a tester and a handler, wherein the tester receives a test start signal of the handler and controls the entire tester, and receives a test result of the tester control unit to obtain a test result. A test result sending unit that outputs the test result to the outside, and a test result comparing unit that compares the test result of the tester control unit with the output signal of the test result sending unit and outputs an error signal when they do not match. A handler control unit that receives the test end signal and the error signal of the tester and controls the entire handler, and a device classification that classifies devices based on a pass signal and a fail signal of the tester. A test method for a semiconductor test apparatus having a control unit, wherein the test is performed by an
Transferring the LSI from the storage tray to the tester
And the handler control unit controls the text at a predetermined time.
Outputting a test start signal to the tester control unit
When, by the tester controller, the test start signal receiving
Starting the test of the LSI and controlling the tester control unit by the test result sending unit.
If the signal is received and the pass is determined by the LSI test result,
If the pass signal is a fail, the fail signal is
Outputting to the device classification control unit at a time; and the test result comparison unit,
Comparison of a control signal with the pass signal and the fail signal
If the test results do not match,
A signal is output to the handler control unit to interrupt the test.
Requesting, and upon receiving the error signal, the handler
The LSI is stored in the error storage tray, and the
Notifying the operator and suspending the operation; and, when the test is interrupted in response to the error signal, the
Check the tester with a perlator and take the necessary
After performing the test, a test start operation is performed, and the tester
Receives the test start signal at a predetermined time.
The error signal is cleared by the control signal ,
Restarting the test, and the tester control unit ending the test at a predetermined time.
Outputting the test end signal indicating completion of the test.
Inspection method for semiconductor inspection equipment . 2. A tester comprising: a tester and a handler, wherein the tester receives a test start signal of the handler and controls the entire tester, and receives a test result of the tester control unit to receive a test result. A test result sending unit that outputs a test result to the outside, and a test result comparing unit, wherein the handler is a handler control unit that receives the test end signal and the error signal of the tester and controls the entire handler, and the tester A device classification control unit that performs device classification based on the pass signal and the fail signal of the test result, wherein the test result comparison unit outputs the test result of the tester control unit and the device classification control unit. The pass signal and the fail signal of the tester are compared, and if they do not match, a test of a semiconductor test apparatus having a means for outputting an error signal is performed. The test is performed by the handler by an operator's test start operation.
Transferring the LSI from the storage tray to the tester
And the handler control unit controls the text at a predetermined time.
Outputting a test start signal to the tester control unit
When, by the tester controller, the test start signal receiving
Starting the test of the LSI and controlling the tester control unit by the test result sending unit.
If the signal is received and the pass is determined by the LSI test result,
If the pass signal is a fail, the fail signal is
Outputting to the device classification control unit at a time; and the test result comparison unit,
The control signal and the device output from the device classification control unit.
The pass signal and the fail signal are compared and tested.
If the results do not match, the error signal is
Outputting to the driver control unit and requesting the interruption of the test;
The LSI is stored in the error storage tray, and the
Notifying the operator and suspending the operation; and, when the test is interrupted in response to the error signal, the
Check the tester with a perlator and take the necessary
After performing the test, a test start operation is performed, and the tester
Receives the test start signal at a predetermined time.
The error signal is cleared by the control signal,
Restarting the test, and the tester control unit ending the test at a predetermined time.
Outputting the test end signal indicating completion of the test.
Inspection method for semiconductor inspection equipment .