JP3150871B2 - Method of manufacturing build-up multilayer printed wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a build-up multilayer printed wiring board in which an interlayer insulating layer is formed on an inner substrate having an inner layer conductor pattern and an outer layer conductor pattern is formed on the interlayer insulating layer. Things.

[0002]

2. Description of the Related Art FIGS. 11 to 13 show a conventional build-up multilayer printed wiring board 30. FIG. This type of multilayer printed wiring board 30 is manufactured through, for example, the following additive process.

[0003] First, a resin varnish is applied on an inner substrate 32 having an inner conductor pattern 31 and cured to form an inner conductor pattern 3 as shown in FIG.
1 is formed to cover the entirety of the resin layer 33. Next, an adhesive layer 34 is formed on the resin layer 33 by applying and curing another resin varnish. In the resin varnish for forming the adhesive layer, a resin filler soluble in the roughening agent is dispersed. Next, the resin layer 33 and the adhesive layer 3
After forming the via hole forming hole 36 by exposing and developing the interlayer insulating layer 35 made of No. 4, a roughening treatment is performed using a roughening agent. As a result, as shown in FIG. 12, the resin filler in the adhesive layer 34 is dissolved, and a roughened surface 34a is formed on the outermost layer of the interlayer insulating layer 35. Thereafter, catalyst nuclei are provided, a permanent resist 37 is formed, and electroless copper plating is performed. Then, copper plating is deposited on the inner wall surface of the via hole forming hole 36 and the upper surface of the interlayer insulating layer 35. As a result, as shown in FIG. 13, via holes 38 and outer layer conductor patterns 39 are formed.

[0004]

However, when a resin varnish is applied and cured in the above-described manufacturing method, the interlayer insulating layer 35 falls down in the non-pattern forming region, and as a result, the surface thereof becomes uneven. I will. Therefore, the flatness of the outer layer conductor pattern 39 formed on the upper surface of the interlayer insulating layer 35 is also deteriorated accordingly. Also, even if an attempt is made to use a part of such an outer conductor pattern 39 as a bonding pad, it is difficult to reliably hit a bonding wire due to the unevenness.
Therefore, bonding failure is likely to occur.

As a countermeasure for eliminating the unevenness of the interlayer insulating layer 35, for example, the following method can be considered. First, a resin varnish for forming the resin layer 33 is thickly applied on the inner substrate 32 and cured. Next, the surface of the cured resin layer 33 is flattened by polishing it by a predetermined amount. Next, after forming the adhesive layer 34 on the upper surface of the flattened resin layer 33, the outer conductor pattern 39 is further formed on the upper surface.

However, it is expected that it would be difficult in practice to implement this method because sophisticated techniques and equipment are required to uniformly polish the resin layer 33. Also,
During the surface polishing, stress is easily applied to the inner layer substrate 32, and the inner layer substrate 32 may be bent. Then, a crack is formed in the interface between the side wall of the inner conductor pattern 31 and the resin layer 33, and as a result, the interlayer insulating layer 35 is easily peeled. Therefore, high insulation reliability cannot be ensured, and the build-up multilayer printed wiring board 3 that can withstand practical use
It was expected that achieving zero would also be difficult. From the above, there has been a demand for another measure for eliminating the unevenness of the interlayer insulating layer 35 without relying on the surface polishing of the resin layer 33.

[0007] The present invention has been made to solve the above problems, its object is a superior build-up multilayer printed circuit board easily and reliably to the flatness and insulation reliability of the interlayer insulating layer surface An object of the present invention is to provide a method of manufacturing a build-up multilayer printed wiring board that can be manufactured.

[0008]

[0009]

Means for Solving the Problems To solve the above problems,
According to a first aspect of the present invention, a first resin layer is formed in a pattern non-formation region on an inner layer substrate having an inner layer conductor pattern while maintaining a predetermined clearance between the pattern and a side surface of the inner layer conductor pattern. Then, a coating layer for filling the clearance and covering the inner conductor pattern and the first resin layer is formed by applying and curing a resin varnish, and then a build-up multilayer for forming an outer conductor pattern on the coating layer. The gist is a method for manufacturing a printed wiring board.

[0010] According to a second aspect of the invention, according to claim 1, wherein the first resin varnish for forming the resin layer, are dispersed sparingly soluble inorganic filler roughening agent. According to a third aspect of the present invention, in the first or second aspect , the coating layer is formed by applying and curing the same resin varnish as a resin varnish for forming the first resin layer. It has a two-layer structure including a resin layer and an adhesive layer formed on the second resin layer by applying and curing a resin varnish in which a resin filler soluble in a roughening agent is dispersed.

[0011]

According to the first to third aspects of the present invention, the formation of the first insulating layer makes the height of the pattern formation region substantially equal to the height of the non-pattern formation region. For this reason, the partial depression of the interlayer insulating layer is reliably eliminated, and the surface thereof is unlikely to have irregularities. Also, since there is no need to perform surface polishing when forming the interlayer insulating layer,
The implementation is easy and the bending of the inner layer substrate is less likely to occur. Further, since a predetermined clearance is maintained between the side wall of the inner conductor pattern and the first resin layer, cracks are less likely to occur at the interface even if bending occurs.

According to the second and third aspects of the present invention, since a resin varnish in which an inorganic filler hardly soluble in a roughening agent is dispersed is used, the first resin layer and the second resin layer to be formed are formed. Has a small thermal expansion coefficient.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in a build-up multilayer printed wiring board and a method for manufacturing the same will be described in detail with reference to FIGS.

FIG. 1 shows a build-up multilayer printed wiring board 1 of this embodiment. The multilayer printed wiring board 1 is a so-called four-layer board having conductor circuits in four layers. An inner conductor pattern 3 is formed on both front and back surfaces of an inner board 2 constituting the multilayer printed wiring board 1. On the inner layer substrate 2, an interlayer insulating layer 4 that entirely covers the inner layer conductor pattern 3 is formed. This interlayer insulating layer 4
A permanent resist 5 and an outer conductor pattern 6 are formed thereon. Via holes 7 are formed in predetermined portions of the interlayer insulating layer 4. These via holes 7 electrically connect the inner conductor pattern 3 and the outer conductor pattern 6. Further, the multilayer printed wiring board 1 is also provided with a plated through hole (not shown) for electrical connection of each layer.

As shown in FIG. 1, the interlayer insulating layer 4 in the present embodiment comprises a lowermost first resin layer 8 and a coating layer 9 (second resin layer 10 and adhesive Tier 1
1). The first resin layer 8 is formed in a region where the inner conductor pattern 3 is not formed on the front and back surfaces of the inner substrate 2 (hereinafter, referred to as a pattern non-formation region R1). A clearance C1 having a predetermined width w1 is held between the side wall of the first resin layer 8 and the side wall of the inner conductor pattern 3 adjacent thereto.

The graph of FIG. 9 shows the relationship between the pattern interval w2 of the adjacent inner conductor pattern 3 and the width w3 of the first resin layer 8. The hatched area in the graph is a range where the width w3 of the first resin layer 8 can be taken. As is clear from this graph,
The first resin layer 8 is provided at a position where the pattern interval w2 is 120 μm or more. If the pattern interval w2 is smaller than 120 μm, the drop of the second resin layer 10 is not so remarkable. Therefore, no large irregularities are formed on the surface of the interlayer insulating layer 4, and the necessity of forming the first resin layer 8 is poor.

For example, when the pattern interval w2 is 120 μm
m, the possible range of the width w3 of the first resin layer 8 is 5
It is 0 μm to 100 μm. Further, the pattern interval w
When 2 is 200 μm, the possible range of the width w3 of the first resin layer 8 is 50 μm to 180 μm. That is, it is preferable that the width w1 of the clearance C1 is at least 10 μm or more, particularly, about 20 μm to 30 μm. If the width w1 is too small, the resin varnish for forming the second resin layer 10 cannot completely enter the clearance C1, causing voids and the like. Further, it becomes difficult to form the first resin layer 8 at a desired position by exposure and development. on the other hand,
If the width w1 is too large, the second resin layer 10 falls into the clearance C1, and the surface of the interlayer insulating layer 4 cannot be sufficiently flattened.

The second resin layer 10 is formed so as to fill the clearance C1 and to entirely cover the inner conductor pattern 3 and the first resin layer 8. The adhesive layer 11 is formed so as to entirely cover the second resin layer 10.

Next, the procedure for manufacturing the build-up multilayer printed wiring board 1 will be described in the order of steps with reference to FIGS. First, using a FR-4 grade copper-clad laminate (copper foil surface is a roughened copper foil, thickness 35 μm) as a starting material, etching was performed according to a conventionally known subtractive method. As a result, as shown in FIG. 2, the inner substrate 2 having the inner conductor patterns 3 on the front and back surfaces of the base material 12 was produced.

Next, 60 parts by weight of cresol novolak type epoxy resin (manufactured by Kyoeisha), 40 parts by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell), 5 parts by weight of imidazole type curing agent (manufactured by Shikoku Chemicals), photosensitive monomer 5 parts by weight (manufactured by Kyoeisha Co., Ltd.), 5 parts by weight of photoinitiator (manufactured by Kanto Kagaku), 0.5 parts by weight of photosensitizer, fine ceramic powder (manufactured by Tatsumori, trade name: Admafine, average particle size about 2 μm) A mixture consisting of 30% by weight was prepared. Then, while adding diethylene glycol diethyl ether to this mixture, the viscosity was adjusted by a homodisper (500 ps in this embodiment), and kneading was performed by a three-roll mill. Thus, first, a resin varnish RW1 for forming the first resin layer 8 and the second resin layer 10 was prepared.

The ceramic fine powder dispersed in the resin varnish RW1 is replaced with epoxy fine powder (manufactured by Toray Industries, Inc.).
(Trade name: Trepearl, average particle size: about 3 μm) to prepare a resin varnish RW2 for forming the adhesive layer 11. In this example, the viscosity of the resin varnish RW2 was adjusted to 800 ps.

Next, as shown in FIG. 3, a resin varnish RW1 for forming the first resin layer 8 was applied to the inner substrate 2 using a roll coater. Thereafter, the applied resin varnish RW1 was dried at 80 ° C. for 15 minutes (touch drying). The term "touch-drying" as used herein means that when the application surface is touched with a finger, the solvent is volatilized until the resin varnish RW1 does not adhere to the finger.

Next, a positive type film as a mask was brought into close contact with both surfaces of the inner layer substrate 2 and exposed at a dose of 400 mJ using a parallel exposure machine (Oak Seisakusho, trade name: 401B type). Thereafter, development was performed using a developer "Etana IR" (manufactured by Asahi Kasei Kogyo). As a result, as shown in FIG. 4, a first resin layer 8 having a thickness of about 30 .mu.m was formed in the non-pattern forming region R1. The first resin layer 8 thus formed has a predetermined clearance C1 between itself and the side wall of the inner conductor pattern 3.

It is desirable that the thickness t 1 of the first resin layer 8 is substantially equal to the thickness of the surrounding inner layer conductor pattern 3. More specifically, for example, the inner conductor pattern 3
Is 35 μm, the thickness t1 is 25 μm or less.
It is preferably 45 μm (30 μm as described above in this embodiment). The thickness of the inner conductor pattern 3 is about 18
In the case of μm, the thickness t1 is preferably 10 μm to 30 μm. Further, when the thickness of the inner conductor pattern 3 is about 70 μm, the thickness t1 is 60 μm to 80 μm.
It is good to be. If the thickness t1 is within the above range, the surface of the interlayer insulating layer 4 can be more reliably flattened.

After washing and drying,
As shown in the above, the resin varnish RW1 was again applied by a roll coater. Then, the applied resin varnish RW1 was touch-dried at 80 ° C. for 30 minutes to form a second resin layer 10. At this time, the clearance C1 is defined by the second resin layer 10.
Is filled, and the inner-layer conductor pattern 3 and the first resin layer 8 are entirely covered. In addition, the second resin layer 1
The thickness of 0 is preferably 30 μm to 60 μm. When the thickness is within the above range, it is preferable in that the clearance C1 can be completely filled, and it is also preferable from the viewpoint of preventing cost increase and size increase. In consideration of the above, in the present embodiment, the thickness of the second resin layer 10 is set to 40 μm.

Further, a resin varnish RW2 for forming the adhesive layer 11 is applied by a roll coater.
Drying to the touch for 15 minutes at ℃. As a result, an adhesive layer 11 having a thickness of about 20 μm to 40 μm was formed on the upper surface of the second resin layer 10.

Next, a mask for forming a via hole is brought into close contact with both surfaces of the inner layer substrate 2, and the mask is formed by the above parallel exposure machine.
Exposure was performed at a dose of 0 mJ. Thereafter, development was performed using a developer "Etana IR". As a result, as shown in FIG. 6, a predetermined portion of the three-layered interlayer insulating layer 4
Via hole forming holes 13 were formed. Then, the adhesive layer 11 was temporarily cured by irradiating it with ultraviolet rays of 3 J / cm ² using an ultraviolet irradiation apparatus. Such UV
After the curing step, the adhesive layer 11 was fully cured by heating at 100 ° C. for 1 hour and at 150 ° C. for 3 hours.

Next, 800 g / liter of chromic acid (C
The resin filler dispersed in the adhesive layer 11 was selectively dissolved by immersing the inner layer substrate 2 in (r ₂ O ₃ ) for 15 minutes. As a result of such a roughening treatment, as shown in FIG. 7, the outer surface of the interlayer insulating layer 4 was replaced with a roughened surface 4a having a large number of anchor recesses. Thereafter, the inner substrate 2 was washed with water after being immersed in the neutralizing solution.

Next, using a commercially available chemical copper plating catalyst nucleation system (manufactured by Shipley), the roughened surface 4
a and palladium were applied to the inner wall surfaces of the via hole forming holes 13. Then, the applied palladium was fixed by heating the inner layer substrate 2 at 120 ° C. for 40 minutes. Next, a dry film photoresist was laminated on the upper surface of the adhesive layer 11, and an exposure mask was further disposed thereon. After exposure in this state, development was performed using a spray developing machine. The above-mentioned "Etana IR" was used as a developer.

Then, using the above-mentioned ultraviolet irradiation device, 3
After temporary curing was performed by irradiating ultraviolet rays of J / cm ² , main curing was performed by heating at 150 ° C. for 30 minutes. As a result, as shown in FIG. 8, a permanent resist 5 having a thickness of 30 μm is formed at a predetermined position on the upper surface of the interlayer insulating layer 4.
Was formed.

Next, by dipping the inner layer substrate 2 on which the permanent resist 5 was formed in an electroless copper plating bath for additive, a copper plating having a thickness of 25 μm was deposited on a portion where the permanent resist 5 was not formed. . As a result, as shown in FIG. 1, the build-up multilayer printed wiring board 1 including the via holes 7 and the outer layer conductor patterns 6 was obtained.

According to the present embodiment, first, after the first resin layer 8 is formed in the non-pattern forming region R1, the second resin layer 10 and the adhesive layer are formed by applying and curing the resin varnishes RW1, RW2. 11 are formed. For this reason,
The height of the pattern formation region and the height of the pattern non-formation region R1 are substantially equal, and the partial depression of the interlayer insulating layer 4 is reliably eliminated. Therefore, it is difficult for the surface of the interlayer insulating layer 4 to have irregularities, and the flatness is surely improved.
Accordingly, the flatness of the outer conductor pattern 6 formed on the upper surface of the interlayer insulating layer 4 is also improved accordingly. As a result, it is possible to obtain an extremely suitable outer conductor pattern 6 that can be used as a bonding pad.

Further, according to the present embodiment, there is a feature that it is not necessary to perform surface polishing when forming the interlayer insulating layer 6. Therefore, it is easier to carry out as compared with the case where the surface is polished, and the situation in which the inner substrate 2 is bent which causes cracks is less likely to occur. Therefore, the interlayer insulating layer 4
Can be prevented, and the insulation reliability of the build-up multilayer printed wiring board 1 can be reliably improved. Of course, with this manufacturing method, problems such as disconnection of the inner conductor pattern 3 due to a position control error during polishing and the like cannot occur. For this reason, the build-up multilayer printed wiring board 1 can be manufactured more reliably than before. In the case of the present embodiment in which the predetermined clearance C1 is provided, even when the inner substrate 2 is bent,
No crack is generated at the interface between the side wall of the inner conductor pattern 3 and the first resin layer 8.

Further, in this manufacturing method, a resin varnish RW1 for forming the first resin layer 8 in which an inorganic filler hardly soluble in a roughening agent is dispersed is used.
In addition, the second resin layer 10 is formed using the same resin varnish RW1. Therefore, according to this method, the adhesion at the interface between the first resin layer 8 and the second resin layer 10 is smaller than when a different resin varnish (more specifically, a resin varnish having a different coefficient of thermal expansion) is used. Performance can be improved. This contributes to the prevention of peeling of the interlayer insulating layer 4, and also to the improvement of insulation reliability. Of course, not only the adhesion is improved, but also the thermal expansion coefficients of the first resin layer 8 and the second resin layer 10 themselves are reduced, which certainly contributes to the improvement of insulation reliability and the like.

In the manufacturing method of this embodiment, after the second resin layer 10 is formed by applying and curing the resin varnish RW1, the adhesive layer 1 is formed by applying and curing the resin varnish RW2.
1 is formed. Resin varnish RW1
In this method, since a hardly soluble inorganic filler is dispersed in a roughening agent, this method has an advantage that the conditions for roughening can be easily set. This is the second resin layer 1
Since the inorganic filler in 0 is hardly soluble, roughening is caused by stopping on the surface of the second resin layer 10.

The present invention can be modified, for example, as follows. (1) When forming the second resin layer 10, the use of a resin varnish different from the resin varnish RW1 for forming the first resin layer 8 is also allowed. For example, as an inorganic filler hardly soluble in a roughening agent, talc, calcium carbonate,
A material in which sepiolite or the like is dispersed may be used. Further, not limited to the inorganic filler, an organic filler or the like which is hardly soluble in the roughening agent may be dispersed in the resin varnish. When an inorganic filler such as ceramics is used, the thermal expansion coefficient of the second resin layer 10 is reduced, which has the advantage of further improving insulation reliability as described above.

(2) As shown in another example of the build-up multilayer printed wiring board 21 shown in FIG.
0 may be omitted, and the coating layer 9 may be constituted only by the adhesive layer 11. With this configuration, the second resin layer 10
This is advantageous in that the process is simplified because there is no coating / curing step. However, the configuration in which the second resin layer 10 is formed as in the embodiment is advantageous in that the conditions for the roughening treatment can be easily set as described above.

Here, in addition to the technical ideas described in the claims, technical ideas grasped by the above-described embodiment and other examples are listed below together with their effects. (1) In the first to third aspects, the first resin layer is formed at a location where the pattern interval of the inner layer conductor pattern is 120 μm or more, and the clearance held at that time is 20 μm to 30 μm. thing. This facilitates the exposure / development and the flattening of the interlayer insulating layer surface.

The technical terms used in the present specification are defined as follows. “Roughening agent: A chemical that dissolves a specific component in the interlayer insulating layer in the roughening treatment, and refers to a solution of, for example, chromic acid, chromate, sulfuric acid, hydrochloric acid, permanganic acid, etc.”

[0040]

As described above in detail, according to the invention described in the claims, easily and reliably produce flatness and insulation reliability excellent build-up multilayer printed wiring board of the interlayer insulating layer surface can do.

[Brief description of the drawings]

FIG. 1 is a partial schematic cross-sectional view showing a build-up multilayer printed wiring board according to an embodiment.

FIG. 2 is a partial schematic cross-sectional view showing the manufacturing procedure.

FIG. 3 is a partial schematic cross-sectional view showing the manufacturing procedure.

FIG. 4 is a partial schematic cross-sectional view showing the manufacturing procedure.

FIG. 5 is a partial schematic cross-sectional view showing the manufacturing procedure.

FIG. 6 is a partial schematic cross-sectional view showing the manufacturing procedure.

FIG. 7 is a partial schematic cross-sectional view showing the manufacturing procedure.

FIG. 8 is a partial schematic cross-sectional view showing the manufacturing procedure.

FIG. 9 is a graph showing a relationship between a pattern interval and a width of a first resin layer.

FIG. 10 is a partial schematic cross-sectional view showing another example of a build-up multilayer printed wiring board.

FIG. 11 is a partial schematic cross-sectional view showing a manufacturing procedure of a conventional build-up multilayer printed wiring board.

FIG. 12 is a partial schematic cross-sectional view showing the manufacturing procedure.

FIG. 13 is a partial schematic cross-sectional view showing the manufacturing procedure.

[Explanation of symbols]

1, 21: build-up multilayer printed wiring board, 2: inner layer substrate, 3: inner layer conductor pattern, 4: interlayer insulation layer, 6: outer layer conductor pattern, 8: first resin layer, 9: coating layer, 10
... second resin layer, 11 ... adhesive layer, RW1, RW2 ... resin varnish, R1 ... pattern non-formed area, C1 ... clearance.

Claims (3)

(57) [Claims] 1. A in the pattern non-forming region on the inner layer board having inner layer conductor pattern, to form a first resin layer while maintaining a predetermined clearance between the side surface of the inner layer conductor pattern, and then the resin After coating and curing a varnish to form a coating layer that fills the clearance and covers the inner conductor pattern and the first resin layer,
A method of manufacturing a build-up multilayer printed wiring board in which an outer conductor pattern is formed on the covering layer. 2. The method for manufacturing a build-up multilayer printed wiring board according to claim 1 , wherein an inorganic filler hardly soluble in a roughening agent is dispersed in a resin varnish for forming the first resin layer. 3. The coating layer according to claim 1 , wherein said coating layer comprises a second resin layer formed by applying and curing the same resin varnish as said resin varnish for forming said first resin layer. The build-up multilayer printed wiring board according to claim 1 or 2 , which has a two-layer structure including an adhesive layer formed on the second resin layer by applying and curing a resin varnish in which a resin filler is dispersed. Production method.