JP2016219477A - Electronic component built-in wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component built-in wiring board capable of enhancing the connection reliability of a via conductor and an electronic component, by suppressing exfoliation of the via conductor from the electronic component more than conventional, and to provide a manufacturing method therefor.SOLUTION: In the electronic component built-in wiring board 10, a first insulation resin layer 21 has a two-layer structure consisting of a support insulation layer 29 and an underlying covering insulating layer 28. A first conductor layer 22 is formed on the support insulation layer 29, and the covering insulating layer 28 is covering a conductor circuit layer 12 and a MLCC17 on the core substrate 11. The covering insulating layer 28 has a larger percentage content of inorganic filler and a smaller coefficient of thermal expansion than the support insulation layer 29.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic component built-in wiring board in which an electronic component is accommodated in a cavity of a core substrate, and the core substrate is covered with an insulating layer, and a method for manufacturing the same.

  This type of electronic component built-in wiring board is provided with via conductors that penetrate the insulating layer and connect to the electronic component (see, for example, Patent Document 1).

JP 2001-345560 (FIG. 1)

  In the above-described conventional electronic component built-in wiring board, the via conductor may be peeled off from the electronic component due to thermal deformation.

  The present invention has been made in view of the above circumstances, and has an electronic component built-in wiring that can suppress the peeling of the via conductor from the electronic component and improve the reliability of the connection between the via conductor and the electronic component. It aims at providing a board and its manufacturing method.

  The invention according to claim 1, which has been made to achieve the above object, includes a core substrate having a cavity in which an electronic component is accommodated, a covering insulating layer on which no conductor layer is laminated, and an upper surface of the covering insulating layer. And a supporting insulating layer having a conductor layer laminated on the upper surface, and a two-layer insulating layer covering at least one of the front and back surfaces of the core substrate and covering the cavity and the electronic component, and the supporting An electronic component built-in wiring board comprising an element connection via conductor for connecting between the conductor layer on the insulating layer and the electronic component, wherein the covering insulating layer has a smaller coefficient of thermal expansion than the supporting insulating layer. And thicker than the supporting insulating layer.

Side sectional view of the electronic component built-in wiring board according to the first embodiment of the present invention. Cross-sectional view of the electronic component built-in wiring board Side sectional view showing the manufacturing process of the electronic component built-in wiring board Side sectional view showing the manufacturing process of the electronic component built-in wiring board Side sectional view showing the manufacturing process of the electronic component built-in wiring board Side sectional view showing the manufacturing process of the electronic component built-in wiring board Side sectional view showing the manufacturing process of the electronic component built-in wiring board Side sectional view showing the manufacturing process of the electronic component built-in wiring board Side sectional view showing the manufacturing process of the electronic component built-in wiring board Side sectional view showing the manufacturing process of the electronic component built-in wiring board

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the electronic component built-in wiring board 10 of the present embodiment is formed by stacking buildup layers 20 and 20 on both front and back surfaces of a core substrate 11. The core substrate 11 is made of an insulating member, and a conductor circuit layer 12 (corresponding to the “conductor layer” of the present invention) is provided on the F surface 11F which is the front side surface and the S surface 11S which is the back side surface. Is formed. The core substrate 11 is formed with a cavity 16 and a conductive through hole 14.

  The cavity 16 of the core substrate 11 accommodates a multilayer ceramic capacitor 17 (hereinafter referred to as “MLCC 17”) as an “electronic component” of the present invention. The MLCC 17 has a structure in which both ends of a ceramic prismatic body are covered with a pair of electrodes 31, 31, and the planar shape of the MLCC 17 is slightly smaller than the planar shape of the cavity 16. In addition, the thickness of the MLCC 17 (that is, the distance between the first main surface 31F that is one of the front and back surfaces of the electrode 31 of the MLCC 17 and the second main surface 31B that is the other surface) is the core substrate. The first main surfaces 31F and 31F of the electrodes 31 and 31 of the MLCC 17 are flush with the outermost surface of the conductor circuit layer 12 on the F surface 11F side of the core substrate 11, while the MLCC 17 The second main surfaces 31B and 31B of the electrodes 31 and 31 are flush with the outermost surface of the conductor circuit layer 12 on the B surface 11B of the core substrate 11. The element holding resin 16J is filled between the MLCC 17 and the inner surface of the cavity 16, and the MLCC 17 is disposed at a position away from the entire inner surface of the cavity 16.

  The conductive through-holes 14 are formed on the small-diameter side of the tapered holes 14A and 14A that are perforated from both the F surface 11F and the S surface 11S of the core substrate 11 and gradually reduce in diameter as they move away from the F surface 11F and the S surface 11S. It has an intermediate constriction shape with the ends communicating with each other. The through hole 14 for conduction is filled with plating to form a through-hole conductive conductor 15, and the through-hole conductive conductor 15 forms a gap between the conductor circuit layer 12 on the F surface 11 F and the conductor circuit layer 12 on the S surface 11 S. It is connected.

  Both the build-up layer 20 on the F surface 11F side of the core substrate 11 and the build-up layer 20 on the S surface 11S side, in order from the core substrate 11 side, the first insulating resin layer 21, the first conductor layer 22, the second An insulating resin layer 23 and a second conductor layer 24 are laminated, and a solder resist layer 25 is laminated on the second conductor layer 24. The first insulating resin layer 21 and the second insulating resin layer 23 correspond to the “two-layer insulating layer” of the present invention.

  A plurality of pad holes are formed in the solder resist layer 25, and a part of the second conductor layer 24 is located in the pad hole and serves as a pad. On the F surface 10F, which is the front side surface of the electronic component built-in wiring board 10, the plurality of pads are composed of a middle pad 26A group and a small pad 26C group, and the small pads 26C group are arranged in a matrix and around it. The middle pad 26A group is arranged in a frame shape and surrounds it. On the other hand, the pad on the S surface 10S, which is the back surface of the entire electronic component built-in wiring board 10, is a large pad 26B larger than the middle pad 26A.

  A plurality of via holes 21H and 23H are formed in the first insulating resin layer 21 and the second insulating resin layer 23, respectively. In the present embodiment, the via holes 21H and 23H have a tapered shape that is gradually reduced in diameter toward the core substrate 11 side, but may not be a tapered shape. The via holes 21H and 23H are filled with plating to form a plurality of via conductors 21D and 23D. The via conductor 21D of the first insulating resin layer 21 connects between the conductor circuit layer 12 and the first conductor layer 22 and between the MLCC 17 and the first conductor layer 22. The first conductor layer 22 and the second conductor layer 24 are connected by the via conductor 23D. Of the plurality of via conductors 21D and 23D, the connection between the MLCC 17 and the first conductor layer 22 corresponds to the “element connection via conductor” of the present invention, and the conductor circuit layer 12 and the first conductor layer 22 are connected to each other. What connects them corresponds to the “conductor interlayer via conductor” of the present invention. In the first and second conductor layers 22 and 24, the minimum width W of the wiring pattern and the minimum distance H between the wiring patterns are each 15 μm or less (see FIG. 2). In addition, the diameters of the connection portion with the lower conductor circuit layer 12 or the MLCC 17 (so-called via bottom) in the via conductor 21D and the connection portion with the lower first conductor layer 22 in the via conductor 23D are both 50 μm or less. ing.

  As shown in FIG. 1, in the electronic component built-in wiring board 10 of the present embodiment, each of the first insulating resin layer 21 and the second insulating resin layer 23 is thicker than the supporting insulating layer 29 and the supporting insulating layer 29. It has a two-layer structure composed of a covering insulating layer 28. Specifically, the thickness of the supporting insulating layer 29 is 15 to 50% of the thickness of the covering insulating layer 28, and the covering insulating layer on the core substrate 11 side in each of the first and second insulating resin layers 21 and 23. 28 is disposed, and a support insulating layer 29 is disposed outside. The first conductor layer 22 or the second conductor layer 24 is formed on the upper surface of each support insulating layer 29. The upper surfaces of these supporting insulating layers 29 are roughened surfaces. The covering insulating layer 28 of the second insulating resin layer 23 covers the first conductor layer 22 on the support insulating layer 29 of the first insulating resin layer 21, and the covering insulating layer 28 of the first insulating resin layer 21 is The conductor circuit layer 12 and the MLCC 17 on the core substrate 11 are covered, and the element holding resin 16J is formed between the cavity 16 and the MLCC 17.

  Both the covering insulating layer 28 and the supporting insulating layer 29 are made of an insulating resin containing an inorganic filler such as silica, alumina, or mullite. Here, generally in an insulating resin, a thermal expansion coefficient becomes small, so that the content rate of an inorganic filler becomes large. In this embodiment, while the inorganic filler content of the support insulating layer 29 is 42 wt% and the thermal expansion coefficient is 39 ppm / ° C., the inorganic filler content of the covering insulating layer 28 is 77 wt% and the thermal expansion coefficient is The coating insulating layer 28 has a larger inorganic filler content and a smaller thermal expansion coefficient than the supporting insulating layer 29. The thermal expansion coefficient of the conductor is 16.8 ppm / ° C., and the thermal expansion coefficient in the thickness direction of the MLCC 17 is about 9 to 13 ppm / ° C.

  The average particle size of the inorganic filler in the support insulating layer 29 is 0.5 μm, and the dielectric loss tangent tan δ (indicating electric energy loss inside the insulator) of the support insulating layer 29 is 0.017. The average particle diameter of the inorganic filler in the insulating layer 28 is 1.0 μm, and the dielectric loss tangent tan δ of the covering insulating layer 28 is 0.0093. Note that neither the coating insulating layer 28 nor the supporting insulating layer 29 contains glass cloth.

The electronic component built-in wiring board 10 of this embodiment is manufactured as follows.
(1) As shown in FIG. 3 (A), copper foil 11C is formed on both sides of an insulating base material 11K made of a reinforcing material such as epoxy resin or BT (bismaleimide triazine) resin and glass cloth as a core substrate 11. Is prepared.

  (2) As shown in FIG. 3B, the core substrate 11 is irradiated with, for example, CO2 laser from the F surface 11F side to form a tapered hole 14A for forming a conductive through hole 14 (see FIG. 1). The

  (3) As shown in FIG. 3C, CO2 laser is irradiated to a position directly behind the tapered hole 14A on the F surface 11F side in the S surface 11S of the core substrate 11 to drill the tapered hole 14A. The conductive through-hole 14 is formed from the tapered holes 14A and 14A.

  (4) An electroless plating process is performed, and an electroless plating film (not shown) is formed on the copper foil 11 </ b> C and the inner surface of the conductive through hole 14.

  (5) As shown in FIG. 3D, a predetermined pattern of plating resist 33 is formed on the electroless plating film on the copper foil 11C.

  (6) The electrolytic plating process is performed, and as shown in FIG. 4A, the electrolytic plating is filled in the conductive through holes 14 to form the through-hole conductive conductors 15 and the copper foil 11C on the copper foil 11C. An electrolytic plating film 34 is formed on a portion of the electrolytic plating film (not shown) exposed from the plating resist 33.

  (7) The plating resist 33 is peeled off, and the electroless plating film (not shown) and the copper foil 11C below the plating resist 33 are removed. As shown in FIG. The conductor circuit layer 12 is formed on the F surface 11F of the core substrate 11 and the conductor circuit layer 12 is formed on the S surface 11S of the core substrate 11 by the film 34, the electroless plating film, and the copper foil 11C. Then, the conductor circuit layer 12 on the F surface 11F and the conductor circuit layer 12 on the S surface 11S are connected by the through-hole conductive conductor 15.

  (8) As shown in FIG. 4C, the cavity 16 is formed in the core substrate 11 by a router or a CO2 laser.

  (9) As shown in FIG. 4D, a tape 90 made of a PET film is stuck on the F surface 11 </ b> F of the core substrate 11 so that the cavity 16 is closed.

  (10) MLCC 17 is prepared.

  (11) As shown in FIG. 5A, the MLCC 17 is stored in the cavity 16 by a mounter (not shown).

  (12) As shown in FIG. 5B, the covering insulating layer 28 and the supporting insulating layer 29 are integrally formed as the first insulating resin layer 21 on the conductor circuit layer 12 on the S surface 11S of the core substrate 11. The formed insulating sheet 30 is laminated with the covering insulating layer 28 side on the core substrate 11 side, and then heated and pressed. At that time, the space between the conductor circuit layers 12 and 12 on the S surface 11S of the core substrate 11 is filled with the coating insulating layer 28, and the resin exuded from the coating insulating layer 28 is in the gap between the inner surface of the cavity 16 and the MLCC 17 Filled.

  (13) As shown in FIG. 5C, the tape 90 is removed.

  (14) As shown in FIG. 6A, the insulating sheet 30 as the first insulating resin layer 21 is laminated on the conductor circuit layer 12 on the F surface 11F of the core substrate 11 with the covering insulating layer 28 side down. Then, it is heated and pressed. At that time, the space between the conductor circuit layers 12 and 12 on the F surface 11F of the core substrate 11 is filled with the coating insulating layer 28, and the thermosetting resin exuded from the coating insulating layer 28 is formed on the inner surface of the cavity 16 and the MLCC 17. The gap is filled. In addition, the element holding resin 16J is formed of a thermosetting resin that oozes out from the coating insulating layer 28 on the F surface 11F side and the S surface 11S side of the core substrate 11 and fills a gap between the inner surface of the cavity 16 and the MLCC 17. .

  (15) The upper surface of the support insulating layer 29 is roughened by the chemical solution.

  (16) As shown in FIG. 6B, the first insulating resin layers 21 and 21 on both sides of the front and back of the core substrate 11 are irradiated with CO2 laser to form a plurality of via holes 21H. Some of the via holes 21H of the plurality of via holes 21H are arranged on the conductor circuit layer 12, and the other part of the via holes 21H are arranged on the electrodes 31 and 31 of the MLCC 17.

  (17) An electroless plating process is performed to form an electroless plating film (not shown) on the first insulating resin layers 21 and 21 and in the via holes 21H and 21H.

  (18) As shown in FIG. 6C, a plating resist 40 having a predetermined pattern is formed on the electroless plating film.

  (19) The electrolytic plating process is performed, and as shown in FIG. 7A, the plating is filled in the via holes 21H and 21H to form the via conductors 21D and 21D. Further, the first insulating resin layer 21 and Electrolytic plating films 39 and 39 are formed on portions of the electroless plating film (not shown) 21 that are exposed from the plating resist 40.

  (20) The plating resist 40 is peeled off and the electroless plating film (not shown) below the plating resist 40 is removed. As shown in FIG. The first conductor layer 22 is formed on each first insulating resin layer 21 on the front and back of the core substrate 11 by the electrolytic plating film. A part of each first conductor layer 22 on the front and back sides of the core substrate 11 and the conductor circuit layer 12 are connected by the via conductor 21D, and another part of each first conductor layer 22 and the MLCC 17 are connected to the via conductor. It will be in the state connected by 21D.

  (21) By the same processing as the above (12) to (20), the second insulating resin layer 23 and the second conductor layer are formed on the first conductor layers 22 on the front and back of the core substrate 11 as shown in FIG. 24 and a part of each second conductor layer 24 and the first conductor layer 22 are connected by the via conductor 23D.

  (22) As shown in FIG. 9, solder resist layers 25, 25 are laminated on the second conductor layers 24 on the front and back sides of the core substrate 11.

  (23) As shown in FIG. 10, tapered pad holes are formed at predetermined locations of the solder resist layers 25, 25 on the front and back of the core substrate 11, and each of the second conductor layers 24 on the front and back of the core substrate 11 The portion exposed from the pad hole becomes the pad 26.

  (24) On the pad 26, for example, a nickel layer, a palladium layer, and a gold layer are laminated in this order to form the metal film 41 shown in FIG. The metal film 41 may be a Sn, Ni / Au layer, or the like. Further, an OSP film may be used instead of the metal film 41. Thus, the electronic component built-in wiring board 10 is completed.

  This completes the description of the structure and manufacturing method of the electronic component built-in wiring board 10 of the present embodiment. Next, usage examples and operational effects of the electronic component built-in wiring board 10 will be described. The wiring board 10 with a built-in electronic component of this embodiment is used by forming solder bumps (not shown) on the pads 26 and mounting a CPU or the like on the solder bumps. At this time, the CPU pad is connected to each of the electrodes 31 and 31 of the MLCC 17 via the via conductors 21D and 23D.

  Here, if the thermal expansion coefficient of the first insulating resin layer 21 is large (the difference between the thermal expansion coefficient of the first insulating resin layer 21 and the thermal expansion coefficient of the conductor is large), the via conductor 21D (particularly the via having the minimum diameter). It is considered that there is a problem that the thermal stress applied to the bottom portion is increased and the via conductor 21D is easily peeled off from the MLCC 17. In contrast, in the electronic component built-in wiring board 10 of the present embodiment, the thermal expansion of the covering insulating layer 28 of the first insulating resin layer 21, that is, the portion covering the upper surface of the MLCC 17 and the periphery of the via bottom of the via conductor 21D. Since the rate is small (the difference between the thermal expansion coefficient of the covering insulating layer 28 and the thermal expansion coefficient of the conductor is small), the via conductor 21D is peeled off from the MLCC 17 by the influence of the thermal expansion of the first insulating resin layer 21. Therefore, the reliability of connection between the via conductor 21D and the MLCC 17 can be improved. Similar to the reliability of the connection between the via conductor 21D and the MLCC 17, the reliability of the connection between the conductor circuit layer 12 and the via conductor 21D on the core substrate 11 and the reliability of the connection between the first conductor layer 22 and the via conductor 23D. Will also improve.

  In addition, since the difference between the thermal expansion coefficient of the covering insulating layer 28 in the first insulating resin layer 21 and the thermal expansion coefficient of the MLCC 17 is small, stress concentration in the via conductor 21D is prevented, and the via conductor 21D is separated from the MLCC 17. Peeling is more prevented. Furthermore, since the inorganic filler content of the element holding resin 16J formed by the covering insulating layer 28 oozing out between the cavity 16 and the MLCC 17 is large, the MLCC 17 is restricted from moving in the cavity 16, and the via conductor 21D The reliability of connection with the MLCC 17 is further improved.

  By the way, if the first and second insulating resin layers 21 and 23 are formed only by the covering insulating layer 28 having a small coefficient of thermal expansion, the inclusion of the inorganic filler over the entire first and second insulating resin layers 21 and 23. The rate increases. In this case, a large amount of inorganic filler is also present on the surfaces of the first and second insulating resin layers 21 and 23. However, since the plating resist 40 is difficult to adhere on the inorganic filler, the first and second It becomes difficult to make the plating resist 40 on the insulating resin layers 21 and 23 dense, and the wiring pattern cannot be made fine.

  On the other hand, in the electronic component built-in wiring board 10 according to the present embodiment, the first insulating resin layer 21 and the second insulating resin layer 23 have a relatively small thermal expansion coefficient (a large content of the inorganic filler). 28 and a support insulating layer 29 having a relatively large thermal expansion coefficient (small content of inorganic filler). And since the conductor layers 22 and 24 are formed in the support insulating layer 29 with a small content of the inorganic filler among them, an anchor effect is obtained when the plating resist 40 is formed, and the plating resist 40 can be made dense. The wiring pattern can be made fine. Thereby, the minimum width W of the wiring pattern and the minimum distance H between the wiring patterns in the first and second conductor layers 22 and 24 can be set to 15 μm or less, respectively.

  Further, since the average particle size of the inorganic filler in the support insulating layer 29 is smaller than the average particle size of the inorganic filler in the covering insulating layer 28, the first and second insulating resin layers 21 of the plating resist 40, The adhesion to 23 can be further increased. Furthermore, since the upper surface of the support insulating layer 29 is a roughened surface, the anchor effect is further enhanced when the plating resist 40 is formed, and it becomes easy to make the plating resist 40 dense. Further, the fixing strength of the conductor layers 22 and 24 to the support insulating layer 29 is also increased.

  Moreover, if the first and second insulating resin layers 21 and 23 have a large coefficient of thermal expansion, it is considered that the entire electronic component built-in wiring board 10 is warped due to expansion due to heating and contraction due to cooling. Since the second insulating resin layers 21 and 23 have the coating insulating layer 28 having a relatively low thermal expansion coefficient, the thermal expansion coefficient of the entire first and second insulating resin layers 21 and 23 is reduced, Warpage of the entire electronic component built-in wiring board 10 can also be suppressed.

  Further, in the electronic component built-in wiring board 10 of the present embodiment, the wiring pattern is covered from the upper surface and the side surface with the covering insulating layer 28 having a smaller dielectric loss tangent tan δ than the supporting insulating layer 29. Electric energy loss can be reduced as compared with the configuration covered only by the above.

  In the present embodiment, since the covering insulating layer 28 is relatively thick and the supporting insulating layer 29 is relatively thin, the connection between the via conductor 21D and the MLCC 17 and the like while ensuring the fineness of the wiring pattern, etc. Compared with the case where the supporting insulating layer 29 and the covering insulating layer 28 have the same thickness, while improving the reliability of the electronic component and suppressing the warpage of the electronic component built-in wiring board 10 as a whole, the electronic component The built-in wiring board 10 can be made thin.

[Other Embodiments]
The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various modifications are possible within the scope of the invention other than the following. It can be changed and implemented.

  (1) In the above embodiment, the thermal conductivity differs depending on the inorganic filler content. For example, the inorganic filler content is the same, and the thermal conductivity varies depending on the type of resin. It may be a configuration.

  (2) In the above embodiment, the insulating sheet 30 in which the covering insulating layer 28 and the supporting insulating layer 29 are integrated is laminated. However, the covering insulating layer 28 and the supporting insulating layer 29 are separately provided one by one. The structure which laminates | stacks may be sufficient.

  (3) In the above embodiment, the inorganic filler content of the covering insulating layer 28 is 77 wt%, and the inorganic filler content of the supporting insulating layer 29 is 42 wt%. However, the present invention is not limited to this. In addition, it is preferable that the inorganic filler content rate of the coating insulating layer 28 is 65 to 85 wt%, and the inorganic filler content rate of the support insulating layer 29 is 30 to 50 wt%.

  (4) In the above embodiment, the insulating resin layers laminated on the front and back of the core substrate 11 are two layers each, but may be one layer each, or may be three layers or more. .

  (5) In the above embodiment, the second insulating resin layer 23 has a two-layer structure including the covering insulating layer 28 and the supporting insulating layer 29 as in the case of the first insulating resin layer 21. The structure which consists only of may be sufficient.

  (6) In the above embodiment, both the first insulating resin layers 21 on the front and back sides of the core substrate 11 have a two-layer structure, but only one first insulating resin layer 21 has a two-layer structure. It may be.

  (7) In the above embodiment, only the MLCC 17 is built in the electronic component built-in wiring board 10. However, for example, a metal block may be built together with the MLCC 17.

  (8) In the above embodiment, the “electronic component” of the present invention is the MLCC 17. However, for example, it may be a passive component such as a capacitor, a resistor, a thermistor, or a coil, or an active component such as an IC circuit.

10 Wiring board with built-in electronic components 11 Core substrate 12 Conductor circuit layer (conductor layer)
16 Cavity 17 MLCC (Multilayer Ceramic Capacitor, Electronic Components)
21 First insulating resin layer (two-layer insulating layer)
21D via conductor (element connection via conductor, conductor interlayer via conductor)
22 First conductor layer (conductor layer)
23 Second insulating resin layer (two-layer insulating layer)
28 Insulating layer 29 Support insulating layer

Claims (15)

A core substrate having a cavity in which an electronic component is accommodated;
A covering insulating layer in which no conductor layer is laminated on the upper surface, and a supporting insulating layer laminated on the covering insulating layer and having a conductor layer laminated on the upper surface, at least one surface of the front and back surfaces of the core substrate A two-layer insulating layer overlaid on and covering the cavity and the electronic component;
An electronic component built-in wiring board comprising: an element connection via conductor connecting between the conductive layer on the support insulating layer and the electronic component;
The covering insulating layer has a smaller coefficient of thermal expansion than the supporting insulating layer and is thicker than the supporting insulating layer. The electronic component built-in wiring board according to claim 1,
The two-layer insulating layer is provided on both the front side and the back side of the core substrate. The electronic component built-in wiring board according to claim 2,
The element connection via conductor is provided on both the front side and the back side of the core substrate. The electronic component built-in wiring board according to any one of claims 1 to 3,
A conductor layer is laminated on the surface of the core substrate covered with the covering insulating layer,
A conductor interlayer via conductor connecting between the conductor layer on the core substrate and the conductor layer on the supporting insulating layer; An electronic component built-in wiring board according to any one of claims 1 to 4,
The two-layer insulating layer is laminated in a state where the covering insulating layer and the supporting insulating layer are integrally formed in a film shape. An electronic component built-in wiring board according to any one of claims 1 to 5,
Both the covering insulating layer and the supporting insulating layer contain an inorganic filler,
The content of the inorganic filler in the covering insulating layer is greater than the content of the inorganic filler in the supporting insulating layer. The electronic component built-in wiring board according to any one of claims 1 to 6,
The covering insulating layer and the supporting insulating layer do not contain glass cloth. The electronic component built-in wiring board according to any one of claims 1 to 7,
The electronic component is a multilayer ceramic capacitor. A wiring board according to any one of claims 1 to 8,
A gap between the cavity and the electronic component is filled with an insulating material having the same component as the covering insulating layer. A wiring board according to any one of claims 1 to 9,
The element connection via conductor is gradually reduced in diameter toward the electronic component. Housing electronic components in the core substrate cavity;
Laminating a two-layer insulating layer composed of the covering insulating layer and the supporting insulating layer on one surface of the front and back of the core substrate, and covering the cavity and the electronic component by the covering insulating layer;
Laminating a conductor layer on the upper surface of the supporting insulating layer;
Connecting the conductor layer on the support insulating layer and the electronic component by an element connection via conductor, and a method of manufacturing an electronic component built-in wiring board,
The covering insulating layer has a smaller coefficient of thermal expansion than the supporting insulating layer and is thicker than the supporting insulating layer. It is a manufacturing method of the electronic component built-in wiring board according to claim 11,
The two-layer insulating layer is provided on both the front side and the back side of the core substrate. It is a manufacturing method of the electronic component built-in wiring board according to claim 12,
The element connection via conductor is provided on both the front side and the back side of the core substrate. A method for manufacturing an electronic component built-in wiring board according to any one of claims 11 to 13,
Laminating a conductor layer on the surface of the core substrate covered with the covering insulating layer;
The conductor layer on the core substrate and the conductor layer on the support insulating layer are connected by a conductor interlayer via conductor. A method for manufacturing an electronic component built-in wiring board according to any one of claims 11 to 14,
The two-layer insulating layer is laminated by laminating an insulating sheet in which the covering insulating layer and the supporting insulating layer are integrally formed in a film shape.

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