JP3149036B2 - Thin film memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film memory device which can be used in, for example, an electrically writable and erasable nonvolatile memory and which operates at a high speed by increasing a read current value.

[0002]

2. Description of the Related Art A conventional NAND type EEPROM has to use an expensive single crystal Si substrate.

On the other hand, it has been studied to form a similar NAND-type EEPROM using thin film transistors which are formed without a substrate electrode. That is, as shown in FIG. 3, n ^{+ serving as a} source and a drain are formed on the insulating substrate. Polysilicon 1 and channel polysilicon 2 are formed, and a gate electrode G is formed at a position corresponding to channel polysilicon 2 with a gate insulating film interposed. In FIG. 3, the first select transistor TRS1 and the second select transistor TR
The memory transistors TRM1 to TRM4 are formed in series between the memory transistors S2 and S2, and n ⁺ which becomes the drain of the first selection transistor TRS1 The polysilicon 1 is connected to the power supply Vdd via the bit line, and the second selection transistor TR
N ^{+ which} is the source of S2 The polysilicon 1 is grounded (GN
D).

That is, if the memory transistors TRM1 to TRM4 sandwiched between the first select transistor TRS1 and the second select transistor TRS2 are in a state where a current flows, the memory transistors TRM1 to TRM4 should be designed to have sufficient depletion. , The first selection transistor TRS1
Since only the two selection transistors TRS2 and TRS2 need to be considered, as shown in FIG. 4A, the first selection transistor TRS1 and the second selection transistor TRS1 excluding the memory transistors TRM1 to TRM4 are simplified for simplicity. The case of the transistor TRS2 will be described as an example. Here, assuming that the gate potential is Vi and the connection portion potential is Vo, the first
The operation of the select transistor TRS1 is performed with the power supply potential Vdd,
Determined from the relationship between the gate potential Vi and the connection portion potential Vo. If the transistor characteristics of the common source (GND) are to be corresponded, the drain-source voltage is Vds, the gate-source voltage is Vgs, and Vds = V
dd−Vo, Vgs = Vi−Vo. Since the gate potential Vi is equal to Vdd when reading the memory, the first selection transistor TRS1 as shown in FIG.
The operation region of is the drain-source voltage Vds = Vdd-
Vo, the gate-source voltage Vgs = Vdd−Vo, which is equal to the transistor characteristic of Vgs = Vds.
On the other hand, in the second selection transistor TRS2, with the same treatment, as shown in FIG. 4C, the drain-source voltage Vds = Vo and the gate-source voltage Vgs = Vd
d, Operation when source voltage Vs = 0 (GND), which always satisfies Vo ≦ Vdd. Thus, each of the first select transistor TRS1 and the second select transistor TRS2 has an n-channel enhancement (E
If the memory is read out (gate potential Vi = Vdd), the first select transistor TRS1 operates in the saturation region, and the second select transistor TRS1 operates in the saturation region.
Select transistor TRS2 operates in a linear region.

[0005]

As described above, when transistors are arranged in series by thin film transistors, there is no substrate potential, and the effective gate of the first select transistor TRS1 on the power supply side increases with the increase in the potential between the series transistors. There is a disadvantage that the voltage is reduced by the back gate bias effect, the drain current which is a read current value is reduced, and the read operation speed is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a thin film memory device capable of improving a reading operation speed by obtaining a large reading current value.

[0007]

According to the present invention, there is provided a first selection transistor comprising a depletion type thin film transistor having a drain region connected to a power supply via a bit line, and A second selection transistor including one enhancement-type thin film transistor whose source region is grounded;
And a memory element connected between the first select transistor and the first select transistor.
By forming the selection transistor in the depletion type, a large drain current, which is a read current value, can be obtained, and the read operation speed can be improved.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a thin film transistor constitutes a NAND type EEPROM. That is,
N ^{+ serving as a} source and a drain on an insulating substrate Polysilicon 111-117 and channel polysilicon 121-1
26 are alternately formed, and the channel polysilicon 12
Gate insulating films 132 made of a tunnel oxide film and a silicon nitride film are provided at upper positions corresponding to 2 to 125, respectively.
To 135, gate electrodes G2 to G5 are formed. Gate electrodes G1 and G6 are formed on channel polysilicon 121 and 126 with gate insulating films 131 and 136 made of only a silicon nitride film without a tunnel oxide film interposed therebetween. N ⁺ Polysilicon 111,
112, channel polysilicon 121 and gate electrode G
1, a depletion type first select transistor TRS11 is formed, and the n ⁺
Polysilicon 116, 117, channel polysilicon 1
26 and the gate electrode G6.
second selection transistor TR
S12 is formed. N ⁺ Polysilicon 112-1
16, the channel polysilicon 122 to 125 and the gate electrodes G2 to G5, the memory transistors TRM11 to TRM11.
The TRM 14 is formed. Memory transistor TRM1
1 to TRM 14 capture electrons at the interface between the tunnel oxide film and the silicon nitride film of the gate insulating films 132 to 135, and transfer the electrons by the tunnel effect to the channel polysilicon 122 to 135.
This constitutes an MNOS type EEPROM which discharges the data to the 125. In this case, a single layer of a silicon-rich silicon nitride film can be used as the gate insulating film having a charge trapping action. First selection transistor TRS1
Memory transistors TRM11 to TRM14 are formed in series between the first and second selection transistors TRS12, and n ^{+ which is} the drain of the first selection transistor TRS11 The polysilicon 111 is connected to the power supply Vdd via the bit line, and the second selection transistor TRS12
N ⁺ is the source of The polysilicon 117 is grounded (GN
D). If the memory transistors TRM11 to TRM14 sandwiched between the first select transistor TRS11 and the second select transistor TRS12 are designed to be sufficiently depleted when current flows, the first select transistor TRS11 And only between the two elements of the second selection transistor TRS12.

FIG. 2 shows the first selection transistor TRS11.
And an operating point of a connection portion where the second selection transistor TRS12 and the second selection transistor TRS12 are connected in series. The horizontal axis represents the connection portion potential Vo,
The vertical axis is a characteristic diagram with the drain current Id taken. That is,
Curve A is a depletion type first selection transistor T
The characteristic curve of RS11 (FIG. 1) and the curve B are the characteristic curves of the enhancement-type first selection transistor TRS1 (FIG. 3), and the curve C is the enhancement-type second selection transistor TRS12 (FIG. 1) and TRS2 (FIG. 3). ) Is a characteristic curve. The characteristic curves A and B represent the first selection transistor T
Operating condition of RS11, TRS1 Vgs = Vds = Vdd
The drain current Id measured at −Vo was used. In FIG. 2, since the connection axis potential Vo is plotted on the horizontal axis, the data at Vo = 0 is the drain current Id at Vgs = Vds = Vdd.
Becomes Since the characteristic curve B is the enhancement type field effect transistor in FIG. 4B, the drain current Id sharply decreases as Vo increases. Since the characteristic curve A shows a depletion type, the drain current Id hardly decreases until Vo becomes close to Vdd, but when it exceeds it, it sharply decreases. The characteristic curve C indicates the operating condition Vgs = Vd of the second selection transistors TRS12 and TRS2.
d, The drain current Id value measured at Vds = Vo was used. Since this is an operation in the linear region, the drain current Id increases as Vo increases. At any point on the horizontal axis Vo, the potential difference between the serially connected ends of the first selection transistors TRS11 and TRS1 and the second selection transistors TRS12 and TRS2 becomes Vdd. The intersection of the characteristic curves a and b of the first selection transistors TRS11 and TRS1 and the characteristic curve c of the second selection transistors TRS12 and TRS2 means that both flowing current values are equal and the potential difference Vdd at both ends is satisfied. An operating point. FIG.
, Point A is the operating point of the connection between the enhancement-type first selection transistor TRS1 and the enhancement-type second selection transistor TRS2, and point B is the depletion-type first selection transistor TRS11 and the enhancement-type first selection transistor TRS11. 2 selection transistors TRS1
2 is the operating point of the connection section. First selection transistor T
By making the RS11 depletion type, the drain current Id, that is, the read current value is increased, and the read operation speed is improved.

[0011]

As described above, according to the present invention, by forming the selection transistor on the power supply side in a depletion type, a large drain current, which is a read current value, can be obtained, and the read operation speed can be improved. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration explanatory view showing one embodiment of the present invention.

FIG. 2 is a characteristic diagram showing operation characteristics of one embodiment of the present invention.

FIG. 3 is a configuration explanatory view showing a thin-film memory device that has been studied in the past.

FIG. 4 is a circuit diagram illustrating an operation of the thin film memory device of FIG. 3;

[Explanation of symbols]

111 to 117 ... n ⁺ Polysilicon, 121-126 ...
Channel polysilicon, G1 to G6: gate electrode, TR
S11: depletion type first selection transistor
TRS12: enhancement-type second selection transistor; TRM11 to TRM14: memory transistors.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/786 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] 1. A first selection transistor comprising a depletion type thin film transistor having a drain region connected to a power supply via a bit line, and a second selection transistor comprising a enhancement type thin film transistor having a source region grounded. A thin-film memory device comprising: a selection transistor; and a memory element connected between the second selection transistor and the first selection transistor.