JP2023144706A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device including a nonvolatile memory capable of efficiently applying a voltage during write and erase operations while suppressing an increase in a circuit area.SOLUTION: A nonvolatile memory 1 includes: a transistor 101 configured to non-volatilely store data; and a diode D1 connected between a gate of the transistor 101 and a backgate of the transistor 101. Preferably, the diode D1 includes a transistor 102, and a gate of the transistor 102 and a source of the transistor 102 are connected to each other.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a nonvolatile memory.

For example, as a document disclosing a semiconductor device including a nonvolatile memory, there is Japanese Patent Application Publication No. 2021-190464 (Patent Document 1). In the memory cell included in the semiconductor device disclosed in Patent Document 1, a gate electrode is formed on a p-well region with a gate insulating film interposed therebetween. On the sides of the gate electrode, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked on a variable resistance portion formed on the surface of the p-well region. In this memory cell, writing is performed by injecting hot electrons generated near the drain region into the silicon nitride film, and by applying a negative bias to the gate and positive bias to the source, hot holes are drawn into the silicon nitride film. Erasure is performed.

Japanese Patent Application Publication No. 2021-190464

As mentioned above, in the memory cell included in the semiconductor device disclosed in Patent Document 1, during an erase operation, a bias opposite to that during writing is applied between the source and the well, thereby causing band-to-band tunneling. hot holes are drawn into the silicon nitride film. Therefore, it is possible to erase more efficiently by increasing the reverse bias applied between the source and the well.

While it is necessary to flow a high current during writing, there is no need to flow a high current during erasing. Instead, it is necessary to apply a high voltage during erasing. Since there is no need to flow a high current, it is also possible to apply a high voltage during erasing using a booster circuit such as a charge pump.

However, if the booster circuit used for erasing is also used for writing, a high current needs to flow, so the circuit area of the booster circuit needs to be increased.

Conversely, if the external power supply voltage used for writing is used for erasing without using a booster circuit, the voltage may not be sufficient and the memory cells may not be able to be erased sufficiently.

In other words, it has been difficult to apply voltage efficiently during writing and erasing, and to reduce the circuit area at the same time.

One object of the present disclosure is to provide a semiconductor device including a nonvolatile memory that can efficiently apply voltage during writing and erasing while suppressing an increase in circuit area.

One embodiment of the present disclosure relates to a semiconductor device. The semiconductor device includes a nonvolatile memory. The nonvolatile memory includes a first field effect transistor configured to nonvolatilely store data, and a diode connected between a gate of the first field effect transistor and a back gate of the first field effect transistor. .

According to the present disclosure, voltage can be efficiently applied during writing and erasing of a nonvolatile memory while suppressing an increase in circuit area.

1 is a circuit diagram showing a configuration of a nonvolatile memory 1 installed in a semiconductor device according to a first embodiment. FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1. FIG. FIG. 2 is an enlarged cross-sectional view showing a sidewall structure including a charge storage film of a nonvolatile memory. FIG. 3 is a schematic cross-sectional view for explaining an erase operation on the nonvolatile memory 1. FIG. FIG. 3 is a schematic cross-sectional view for explaining a write operation to the nonvolatile memory 1. FIG. FIG. 2 is a schematic cross-sectional view for explaining a read operation for the nonvolatile memory 1. FIG. FIG. 2 is a circuit diagram showing the configuration of a nonvolatile memory 1A installed in a semiconductor device according to a second embodiment. FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment.

Embodiments of the present disclosure will be described in detail below with reference to the drawings. In addition, the same reference numerals are attached to the same or corresponding parts in the drawings, and the description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a circuit diagram showing the configuration of a nonvolatile memory 1 mounted on a semiconductor device according to the first embodiment. The nonvolatile memory 1 is mounted on a semiconductor device and can store various information, setting values, etc. in a nonvolatile manner.

Nonvolatile memory 1 includes a field effect transistor 101 and a diode D1. Field effect transistors are generally composed of MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Hereinafter, a "field effect transistor" will be simply referred to as a "transistor." Transistor 101 is configured to store data in a non-volatile manner. Diode D1 is connected between the gate of transistor 101 and the back gate of transistor 101.

The diode D1 is connected so that the direction from the back gate to the gate of the transistor 101 is the forward direction. Diode D1 is constituted by a diode-connected transistor.

That is, diode D1 includes transistor 102. The gate, source, and back gate of the transistor 102 and the back gate of the transistor 101 are connected by a wiring L1. The gate of the transistor 101 and the drain of the transistor 102 are connected by a wiring L2.

The nonvolatile memory 1 further includes a transistor 104 for selecting a ground potential. The drain of the transistor 104 and the back gate of the transistor 101 are connected by a wiring L3.

Terminal TG1 is connected to the gate of transistor 101. Terminal TP1 is connected to the drain of transistor 101. Terminal TP2 is connected to the source of transistor 101. Terminal TG2 is connected to the gate of transistor 104. Terminal TP3 is connected to the source of transistor 104. By setting various voltages to the terminals TG1, TG2, and TP1 to TP3, data can be written (programmed), erased, and read from the nonvolatile memory 1.

Note that the terminals TG1, TG2, TP1 to TP3 may be internal nodes of the semiconductor device, or may be connected to a memory cell selection circuit, and the applied potential may be controlled. Transistor 104 may be part of such a selection circuit.

The transistor 102 that operates as a diode may be provided one-to-one with the transistor 101 that stores data, as illustrated in FIG. may be provided.

FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment. In FIG. 2, the detailed structure of the sidewall structure 40, the covering insulating film 51, the interlayer insulating film 65, etc., which will be described later in FIG.

The semiconductor device includes a nonvolatile memory 1 using MOSFETs. The semiconductor device includes a semiconductor layer 2 made of single crystal Si. The semiconductor layer 2 has a first main surface (front surface) and a second main surface (back surface).

The semiconductor device includes an n-type (first conductivity type) epitaxial layer 20 formed on the first main surface of the semiconductor layer 2. Epitaxial layer 20 is formed over the entire semiconductor layer 2 .

A semiconductor device is provided with a trench insulation structure 10 to define a device region in which a MOSFET is formed. Specifically, in the semiconductor device including the nonvolatile memory 1 shown in FIG. 2, a trench 11 and an insulating buried object 12 are provided as the trench insulating structure 10. The trench 11 is formed by digging the first main surface toward the second main surface. The trench 11 is formed in a square ring shape in a plan view (hereinafter simply referred to as "plan view") when viewed from the normal direction Z of the first main surface and the second main surface, and partitions a square device region. There is. Note that the direction in which one side of the device region extends in plan view is defined as direction X. A direction (not shown) perpendicular to both the direction X and the normal direction Z is defined as a direction Y. FIG. 2 shows a direction X parallel to the main surface and a normal direction Z to the main surface.

In this embodiment, the trench 11 is formed in a tapered shape whose opening width narrows toward the bottom wall. The taper angle of trench 11 may be greater than 90° and less than or equal to 125°. The taper angle is preferably greater than 90° and less than 100°. The taper angle of trench 11 is the angle formed between the inner wall of trench 11 and the first main surface in semiconductor layer 2 . Of course, the trench 11 may be formed perpendicularly to the first main surface.

The depth of the trench 11 may be 0.1 μm or more and 1 μm or less. The width of trench 11 is arbitrary. The width of the trench 11 may be 0.1 μm or more and 10 μm or less. The width of trench 11 is defined by the width in a direction perpendicular to the direction in which trench 11 extends in plan view.

The insulating buried object 12 is buried in the trench 11 . The insulator constituting the insulating buried object 12 is arbitrary. Insulating buried material 12 may include at least one of silicon oxide (SiO ₂ ) and silicon nitride (SiN). In this embodiment, the insulating buried object 12 is formed of silicon oxide, for example. The insulating buried object 12 may have a portion protruding from the semiconductor layer 2.

The semiconductor device includes p-type (second conductivity type) well regions 21 and 71 formed in the surface portion of the first main surface in the device region. The p-type impurity concentration of the well regions 21 and 71 exceeds the n-type impurity concentration of the epitaxial layer 20. The p-type impurity concentration of the well regions 21 and 71 is, for example, 10×10 ¹² cm ⁻³ or more and 10×10 ¹⁶ cm ⁻³ or less.

The bottoms of well regions 21 and 71 are electrically connected to epitaxial layer 20. In this embodiment, the well regions 21 and 71 are formed deeper than the trench 11 and partially cover the bottom wall of the trench 11. Of course, unlike this embodiment, the boundary between the well regions 21 and 71 and the epitaxial layer 20 may be located at the same position as the bottom wall of the trench 11.

The transistor 101 includes an n-type (first conductivity type) source region 22S (first region) formed on the surface of the well region 71, and an n-type (first conductivity type) source region 22S (first region) formed on the surface of the well region 71 at a distance from the source region 22S. and an n-type (first conductivity type) drain region 22D (second region). The n-type impurity concentration of the source region 22S and drain region 22D is, for example, 10×10 ¹⁶ cm ⁻³ or more and 10×10 ²⁰ cm ^{−3 or} less.

A channel region 24 of the transistor 101 is formed between the drain region 22D and the source region 22S. Channel region 24 forms a current path along direction X between source region 22S and drain region 22D.

Note that in this specification, the source region 22S and drain region 22D of the transistor 101 indicate regions that become the source and drain of the MOSFET, respectively, when data is read from the memory element. During writing and erasing, the source region 22S and drain region 22D do not necessarily operate as indicated by their names. Note that in this embodiment, the first region is the source region and the second region is the drain region, but the first region may be the drain region and the second region is the source region.

Furthermore, in the case of normal elements such as the transistors 102 and 104, the side including the source region 22S and the side including the drain region 22D have an n-type (n-type) impurity concentration lower than that of the source region 22S and the drain region 22D. 1 conductivity type) LDD (Lightly Doped Drain) regions (N-LDD regions) 23S and 23D are provided overlappingly. However, when used as a memory element, the N-LDD region is not provided as shown in FIG.

Transistor 101 includes a planar gate structure 30 formed on a first main surface opposite channel region 24 . Planar gate structure 30 is located between source region 22S and drain region 22D in plan view.

Each of transistors 102, 104 also includes a planar gate structure 30 formed on a first major surface opposite channel region 24. Planar gate structure 30 is located between source region 22S and drain region 22D corresponding to each of transistors 102 and 104 in plan view.

Each planar gate structure 30 includes a gate insulating film 31 formed on the semiconductor layer 2 and a gate electrode 32 formed on the gate insulating film 31. The gate insulating film 31 is made of an oxide of the semiconductor layer 2. Specifically, the gate insulating film 31 is made of an oxide formed into a film shape by oxidizing the surface portion of the first main surface. That is, the gate insulating film 31 is made of a silicon oxide film (SiO ₂ film) formed along the first main surface. More specifically, the gate insulating film 31 is made of a thermal oxide of the semiconductor layer 2 formed into a film shape by thermally oxidizing the surface portion of the first main surface of the semiconductor layer 2 . That is, the gate insulating film 31 is made of a silicon thermal oxide film (thermal oxide film) formed along the first main surface. The gate insulating film 31 may have a thickness of 7 nm or more and 13 nm or less.

Gate electrode 32 is made of conductive polysilicon. Gate electrode 32 is formed on gate insulating film 31 . The width (gate length) of the gate electrode 32 in the direction X may be 0.13 μm or more and 0.5 μm or less.

FIG. 3 is an enlarged cross-sectional view showing a sidewall structure including a charge storage film of a nonvolatile memory. As shown in FIGS. 2 and 3, in the transistor 101, a sidewall structure 40 including a silicon nitride (SiN) charge storage film 42 is formed on the side of the planar gate structure 30. The sidewall structure 40 is disposed adjacent to the side of the planar gate structure 30 so as to cover the sidewall of the gate electrode 32 . Specifically, the sidewall structure 40 covers the sidewall of the gate electrode 32. In this embodiment, data can be erased, written, and read using the sidewall structure 40, as will be described later with reference to FIGS. 4 to 6. Therefore, the sidewall structure 40 functions as a memory structure including a charge storage film in the nonvolatile memory 1.

The sidewall structure 40 has a rectangular ring shape surrounding the planar gate structure 30 in plan view. Specifically, the sidewall structure 40 includes a portion located between the source region 22S and the planar gate structure 30, a portion located between the drain region 22D and the planar gate structure 30, and a portion not shown in FIG. is formed on the portion located above the insulating buried object 12. The sidewall structure 40 includes an insulating film 41, a charge storage film 42, and an insulating film 43 (insulating spacer).

The semiconductor device further includes a covering insulating film 51 covering the planar gate structure 30 and the sidewall structure 40. The covering insulating film 51 covers the source region 22S and the drain region 22D, and further covers the insulating buried object 12.

The semiconductor device includes an interlayer insulating film 65 covering the first main surface. Interlayer insulating film 65 includes at least one of an oxide film (SiO ₂ film) and a nitride film (SiN film). The interlayer insulating film 65 may have a single layer structure made of an oxide film or a nitride film. The interlayer insulating film 65 may have a stacked structure in which one or more oxide films and one or more nitride films are stacked in any order. Interlayer insulating film 65, which is not shown in FIG. 2, covers trench insulating structure 10, source region 22S, drain region 22D, planar gate structure 30, and sidewall structure 40 on the first main surface.

The semiconductor device includes wiring lines L1 to L3 formed on an interlayer insulating film 65. Each wiring may include at least one of an Al film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film.

A barrier wiring film may be provided between each wiring and the interlayer insulating film 65. The barrier wiring film may have a single layer structure made of a Ti film or a TiN film. The barrier wiring film may have a stacked structure including a Ti film and a TiN film stacked in any order. The barrier wiring film may also be provided on each wiring.

The transistor 101 has been mainly described above. The transistors 102 and 104 differ from the transistor 101 in that they have a P-well region 21 instead of the P-well region 71 and that they are provided with N-LDD regions 23S and 23D, but the other configurations are similar, so the description will be omitted. Don't repeat.

(Operation of semiconductor device)
Next, each operation (erase operation, write operation, and read operation) of the nonvolatile memory 1 will be specifically explained using the drawings.

FIG. 4 is a schematic cross-sectional view for explaining an erase operation on the nonvolatile memory 1. As shown in FIG. At the time of erasing, -5V is applied to the terminal TG1, 4V is applied to the terminal TP1, the terminal TP2 is set in the OPEN state, and 0V is applied to the terminals TG2, TP3, and TP4.

As shown in FIG. 4, by applying a voltage (4V) equivalent to the power supply voltage to the terminal TP1 and applying a voltage of approximately negative bias (-5V) to the terminal TG1, charge storage is injected into the charge storage film of the sidewall structure 40. The erasing operation is achieved by extracting the emitted electrons.

The high voltage required to be applied between the source and the well to erase the information held in the transistor 101 is obtained by applying a negative bias applied to the gate through the diode D1 to the P-well region 71.

By forming the P-well region 71 in the n-type diffusion layer 20 (or in a low concentration n-type substrate), the P-well region 71 can be made electrically floating. By connecting the switch formed by the transistor 104 and the diode formed by the transistor 102 to the P well region 71, the potential of the P well region 71 can be selected from 0V (=GND) or negative bias (-3V).

That is, in the nonvolatile memory 1 of this embodiment, by connecting the diode-connected transistor 102 between the gate of the transistor 101 and the P-well, the negative bias applied to the gate during erasing is also applied to the P-well region 71. becomes possible. If the forward ON voltage of diode D1 is 2V, the voltage of P-well region 71 is −3V as shown in FIG. 4.

By applying a negative bias to the P-well region 71, the reverse bias applied between the source and the well becomes 7V, which is 3V higher than in the conventional case. This increases the rate of hot hole generation, thereby improving the efficiency of erasing the nonvolatile memory 1. By increasing the efficiency of erase operations, memory operations can be performed even at low power supply voltages.

Furthermore, since a lower voltage (4V) than the conventional one, which is equivalent to the power supply voltage, can be used at the terminal TP1 during erasing, the external power supply (4V) used during writing can also be used during erasing. As a result, it is possible to eliminate the charge pump circuit that is conventionally mounted because it requires a high voltage (7V or more), and it is possible to reduce the circuit area occupied on the semiconductor substrate.

FIG. 5 is a schematic cross-sectional view for explaining a write operation to the nonvolatile memory 1. During writing, +5V is applied to the terminal TG1, 4V is applied to the terminal TP1, 0V is applied to the terminal TP2, 5V is applied to the terminal TG2, and 0V is applied to the terminals TP3 and TP4. For example, a voltage from an external power supply is supplied to the terminal TP1.

As shown in the schematic diagram of FIG. 5, the write operation of the nonvolatile memory 1 is achieved by injecting electrons (hot electrons HE) flowing into the source region 22S of the transistor 101 into the charge storage film of the sidewall structure 40.

Specifically, during a write operation, a positive potential (for example, +4 to 5 V) is applied to the terminal TG1 and the terminal TP1, and a reference potential (Vss=0 V) is applied to the terminal TP2. As a result, hot electrons are generated by flowing a high current between the source and drain of the transistor 101, and are drawn into the positive potential of the gate, and the charges are trapped in the charge storage film of the sidewall. The writing time is, for example, 0.1 ms to 100 ms.

The potentials of the terminals TG1 and TP1 in the write operation are not limited to Vpp=+4 to 5V, and may be any potential selected from the range of 3V or more and 8V or less, for example. Note that the larger the potential amount (absolute value) is, the faster the write operation of the nonvolatile memory 1 is.

Due to the negative charges of electrons injected into the charge storage film by the write operation, part of the channel of the channel region 24 disappears, making it difficult for current to flow between the source region 22S and drain region 22D of the transistor 101. That is, the gate threshold voltage Vth increases due to the negative charge of the injected electrons.

Since it is necessary to flow a high current during a write operation, it is desirable that the voltage applied to the terminal TP1 be applied directly from an external power supply voltage without using a booster circuit such as a charge pump. In contrast, in the nonvolatile memory 1 of the present disclosure, due to the circuit configuration, the voltage applied to the terminal TP1 (drain) is the same 4V during the write operation shown in FIG. 5 and during the erase operation shown in FIG. can do. This makes it possible to reduce the number of booster circuits and the like, thereby reducing the circuit area occupied on the semiconductor substrate.

Next, a read operation of the nonvolatile memory 1 will be explained. FIG. 6 is a schematic cross-sectional view for explaining a read operation for the nonvolatile memory 1.

During reading, +2V is applied to the terminal TG1, 1V is applied to the terminal TP1, 0V is applied to the terminal TP2, 5V is applied to the terminal TG2, and 0V is applied to the terminals TP3 and TP4.

In the case of a written transistor, the electric field generated by the gate potential (Vg = 2V) does not reach the channel region due to the influence of the charge injected into the sidewall charge storage film 42 (nitride film), so the channel is interrupted. . Therefore, no current flows through the written transistor 101 even if the gate potential Vg is set to 2V and the drain-source voltage Vgs is set to 1V.

On the other hand, in the case of the unwritten transistor 101, when the gate potential Vg is set to 2V, a channel is formed and the transistor is turned on, so when the drain-source voltage Vgs is set to 1V, a current flows.

Therefore, during a read operation, with a potential applied to the gate electrode 32, it can be determined whether data is written in the memory structure based on the presence or absence of the drain-source current Ids. Therefore, at the time of reading, information written in the sidewall of the transistor 101 can be read by connecting a sense amplifier that detects current to the terminal TP1 or TP3.

[Embodiment 2]
In the first embodiment, diode-connected transistor 102 is connected between the gate and back gate of transistor 101. In this case, there is a voltage drop corresponding to the forward ON voltage of the transistor 102, and the potential difference between the back gate voltage and the gate voltage of the transistor 101 is equal to the voltage drop. Therefore, the potential of the well region 71 during erasing is adjusted by parameters such as the impurity concentration of the well region 21.

In the second embodiment, it is easier to adjust the potential of the well region 71 during erasing. FIG. 7 is a circuit diagram showing the configuration of a nonvolatile memory 1A mounted on a semiconductor device according to the second embodiment. FIG. 8 is a cross-sectional view of the semiconductor device according to the second embodiment.

Nonvolatile memory 1A includes a field effect transistor 101 and a diode D1. Transistor 101 is configured to store data in a non-volatile manner. Diode D1 is connected between the gate of transistor 101 and the back gate of transistor 101.

The diode D1 is connected so that the direction from the back gate to the gate of the transistor 101 is the forward direction. In the second embodiment, diode D1 is composed of two diode-connected transistors.

That is, diode D1 includes transistors 102A and 102B. The gate, source, and back gate of the transistor 102A and the back gate of the transistor 101 are connected by a wiring L1.

The gate, source, and back gate of the transistor 102B and the drain of the transistor 102A are connected by a wiring L2B. The gate of the transistor 101 and the drain of the transistor 102B are connected by a wiring L2A.

The other configuration of the nonvolatile memory 1A is the same as the configuration of the nonvolatile memory 1 shown in FIG. 1, so the description will not be repeated.

Although FIGS. 7 and 8 show an example in which two diode-connected transistors are connected in series, the diode D1 may be configured by three or more diode-connected transistors. In this way, the potential of the well region 71 during erasing can be adjusted by changing the number of transistors connected in series without changing the manufacturing conditions such as the implantation amount that determines the impurity concentration.

The nonvolatile memories of the first and second embodiments described above are used built into microcomputers, gate drivers, and other LSIs that require memory functions.

(summary)
The present embodiment will be summarized below with reference to the drawings again.

The present disclosure relates to a semiconductor device including a nonvolatile memory 1. As shown in FIGS. 1 and 2, the nonvolatile memory 1 includes a transistor 101 configured to nonvolatilely store data, a diode D1 connected between the gate of the transistor 101, and the back gate of the transistor 101. including.

Preferably, diode D1 includes transistor 102. The gate of the transistor 102 and the source of the transistor 102 are connected. That is, the transistor 102 is diode-connected between the gate and back gate of the transistor 101.

More preferably, diodes may be connected in series as shown in FIGS. 7 and 8. That is, diode D1 includes transistors 102A and 102B. The gate of the transistor 102A and the source of the transistor 102A are connected. The gate of the transistor 102B, the source of the transistor 102B, and the drain of the transistor 102A are connected.

As shown in FIG. 2, the semiconductor device preferably includes a semiconductor layer 2 having a main surface. The transistor 101 includes a first well region 71 formed on the surface of the main surface of the semiconductor layer 2, and a first well region 71 formed on the surface of the first well region 71 at intervals in the first direction (X direction). The first region (source region 22S) and the second region (drain region 22D) are provided. The conductivity type of the first region and the second region is the first conductivity type (n type), and the conductivity type of the first well region 71 is the second conductivity type (p type).

The transistor 101 is stacked in a second direction (Z direction) on the main surface of the semiconductor layer 2 so as to face a channel region 24 between a first region (source region 22S) and a second region (drain region 22D). The first planar gate structure 30 including the formed first gate insulating film 31 and first gate electrode 32, and the first direction (X direction) of the first planar gate structure 30 on the first region (source region 22S) side. It further includes a sidewall structure 40 disposed adjacent to the side. As shown in FIG. 3, the sidewall structure 40 includes a first insulating film 41, a second insulating film 43, and a charge storage film 42 disposed between the first insulating film 41 and the second insulating film 43. include.

The first region is the source electrode of the transistor 101, the second region is the drain electrode of the transistor 101, and the first gate electrode 32 is the gate electrode of the transistor 101.

More preferably, as shown in FIG. 2, the diode D1 is formed in the second well region 21 formed in the surface portion of the main surface of the semiconductor layer 2 and in the surface portion of the second well region 21 with a space therebetween. The semiconductor device further includes a third region (source region 22S) and a fourth region (drain region 22D). The conductivity type of the third region and the fourth region is the first conductivity type (n type), and the conductivity type of the second well region 21 is the second conductivity type (p type). The diode D1 is stacked in the second direction (Z direction) on the main surface of the semiconductor layer 2 so as to face the channel region 24 between the third region (source region 22S) and the fourth region (drain region 22D). The second planar gate structure 30 including the formed second gate insulating film 31 and the second gate electrode 32 is connected to the first well region 21, the third region (source region 22S), and the second gate electrode 32. It further includes a wiring L1. The first wiring L1 is further connected to the first well region 71. The semiconductor device further includes a second wiring L2 connecting the first gate electrode 32 and the fourth region (drain region 22D).

More preferably, the nonvolatile memory 1 is configured to inject hot electrons into the charge storage film 42 during the write operation shown in FIG. 5, and draw hot holes into the charge storage film 42 during the erase operation shown in FIG. has been done.

More preferably, as shown in FIG. 3, the thickness of the first insulating film 41 is thinner than the thickness of the second insulating film 43.

More preferably, the charge storage film 42 is made of SiN, and each of the first insulating film 41 and the second insulating film 43 is made of SiO ₂ .

The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims rather than the description of the embodiments described above, and it is intended that all changes within the meaning and range equivalent to the claims are included.

1, 1A non-volatile memory, 2 semiconductor layer, 10 trench insulation structure, 11 trench, 12 insulating buried material, 20 epitaxial layer, 21, 71 well region, 22D drain region, 22S source region, 23D, 23S LDD region, 24 channel region , 30 planar gate structure, 31 gate insulating film, 32 gate electrode, 40 sidewall structure, 41, 43 insulating film, 42 charge storage film, 51 covering insulating film, 65 interlayer insulating film, 101, 102, 102A, 102B, 104 Transistor, D1 diode, L1, L2A, L2, L2B, L3 wiring, TG1, TG2, TP1 to TP4 terminals.

Claims (8)

A semiconductor device, comprising a nonvolatile memory,
The nonvolatile memory is
a first field effect transistor configured to non-volatilely store data;
A semiconductor device including a diode connected between a gate of the first field effect transistor and a back gate of the first field effect transistor. the diode includes a second field effect transistor;
2. The semiconductor device according to claim 1, wherein the gate of the second field effect transistor and the source of the second field effect transistor are connected. The diode further includes a third field effect transistor,
3. The semiconductor device according to claim 2, wherein a gate of the third field effect transistor, a source of the third field effect transistor, and a drain of the second field effect transistor are connected. The semiconductor device includes a semiconductor layer having a main surface,
The first field effect transistor is
a first well region formed in a surface portion of the main surface of the semiconductor layer;
comprising a first region and a second region formed at a distance in a first direction on a surface portion of the first well region;
The conductivity type of the first region and the second region is a first conductivity type,
The conductivity type of the first well region is a second conductivity type,
The first field effect transistor is
A first gate insulating film and a first gate electrode stacked in a second direction on the main surface of the semiconductor layer so as to face a channel region between the first region and the second region. 1 planar gate structure,
further comprising a sidewall structure disposed adjacent to a side in the first direction of the first planar gate structure on the first region side,
The sidewall structure is
a first insulating film and a second insulating film;
a charge storage film disposed between the first insulating film and the second insulating film,
The first region is a source electrode of the first field effect transistor,
The second region is a drain electrode of the first field effect transistor,
The semiconductor device according to claim 1, wherein the first gate electrode is a gate electrode of the first field effect transistor. The diode is
a second well region formed in a surface portion of the main surface of the semiconductor layer;
further comprising a third region and a fourth region formed at a distance from each other on the surface of the second well region,
The conductivity type of the third region and the fourth region is the first conductivity type,
The conductivity type of the second well region is the second conductivity type,
The diode is
a second gate insulating film and a second gate electrode stacked in the second direction on the main surface of the semiconductor layer so as to face a channel region between the third region and the fourth region; a second planar gate structure;
further comprising a first wiring connecting the second well region, the third region and the second gate electrode,
The first wiring is further connected to the first well region,
The semiconductor device includes:
5. The semiconductor device according to claim 4, further comprising a second wiring connecting the first gate electrode and the fourth region. 5. The semiconductor device according to claim 4, wherein the nonvolatile memory is configured to inject hot electrons into the charge storage film during a write operation and draw hot holes into the charge storage film during an erase operation. 5. The semiconductor device according to claim 4, wherein the first insulating film is thinner than the second insulating film. 5. The semiconductor device according to claim 4, wherein the charge storage film is made of SiN, and each of the first insulating film and the second insulating film is made of _SiO2 .

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