JP3144909B2 - Reference power supply circuit for liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display (LC).
More particularly, the present invention relates to a configuration of a reference power supply circuit used for an LCD adapted for multi-gradation display. LCDs are expected to replace conventional CRTs and are expected to develop into large-scale markets. for that reason,
Its technical development is being actively pursued. Among the,
LCDs using thin film transistors (TFTs) are capable of high-quality display in principle and have a high display speed, and are expected to become the mainstream of high-speed and high-quality color display. ing.

[0002]

2. Description of the Related Art In an LCD using a TFT, a TFT is used as a switching element, and an analog voltage signal (information) proportional to the magnitude of an image data signal is written through a TFT corresponding to a liquid crystal capacitance of each pixel. Perform image display. FIG. 9 shows a configuration of an LCD as an example of a conventional type, and FIG. 10 shows a configuration of a main part thereof.

[0003] In the example shown in the figure, the configuration of a TFT LCD using a digital driver system as a display control mode is shown, and the number of pixels is shown as 4x4 for simplicity of explanation. Actually, the number of pixels is typically about 640 × 480, and for color display, it is necessary to have separate pixels for red (R), green (G) and blue (B). It requires twice the number of pixels.

In FIG. 1, reference numeral 10 denotes a liquid crystal display (liquid crystal panel), in which P11 to P44 represent minimum display units called pixels. Each of the pixels P11 to P44 is shown in FIG.
As shown in FIG. 7, a transfer gate is provided at the intersection of a plurality of data lines X1 to X4 and a plurality of gate lines Y1 to Y4, and transmits voltage information on the corresponding data line when the corresponding gate line is selected. And a liquid crystal capacitor for storing information transmitted through the corresponding TFT. In this figure, the arrangement of pixels in the horizontal direction (for example, P11 to P14) is called one line, and data for display on the LCD is written for each line. Make the image look flicker-free.

In FIG. 9, HS is a horizontal synchronizing signal, VS
Is a vertical synchronizing signal, D1 to DN are image data, and CL
K indicates a timing signal (clock) provided in synchronization with the image data. N represents the number of bits for gradation display. The clock CLK can be generated internally by measuring the cycle of the horizontal synchronization signal HS, and is not essentially required as an interface.

Reference numeral 40A denotes a control circuit for controlling the entire LCS, and generates various control signals for writing the image data D1 to DN in response to the horizontal synchronizing signal HS, the vertical synchronizing signal VS and the clock CLK. Reference numeral 50A denotes a reference power supply circuit that generates a plurality of types of reference voltages V1 to VM. Reference numeral 20A denotes a data driver, which includes a shift register 21 and memories 61 to 6 each having a capacity of N bits.
4 and a memory 7 having the same N-bit capacity.
1 to 74 are decoders 81 to 84 and selectors 91 to 9
4 as an integrated circuit in a normal form.
Note that the reference power supply circuit 50A is not normally included in an integrated circuit. This is because the data driver 20A required for the LCD is usually composed of a plurality of ICs, while the reference power supply circuit 50A only needs to be provided in common.

In the data driver 20A, the shift register 21 starts operating in response to a start signal T1 supplied from the control circuit 40A line by line, and advances by a clock CK1 also supplied from the control circuit 40A to produce a timing signal. Generate TS1 to TS4. Memory 6
1 to 64 correspond to the display data DT1 to DTN supplied through the control circuit 40A, respectively.
1 to TS4 and capture (that is, write data). After the data is written to the memories 61 to 64, the memories 71 to 74 transfer the data in the memories 61 to 64 to the control circuit 40A before the data of the next line arrives.
(Data writing) in response to the timing signal T2. Decoders 81 to 84 decode digital data stored in memories 71 to 74, respectively. The selectors 91 to 94 correspond to the corresponding decoders 81 to
Based on the decoding result of 84, one of a plurality of types of reference voltages V1 to VM output from the reference power supply circuit 50A is selectively output. That is, the selectors 91 to 94
It functions as a kind of digital / analog conversion circuit for generating an analog signal corresponding to the digital data stored in 1 to 74. Thus, V1 to V
One of M kinds of M voltages is selected, and the data line X
1 to X4. The relationship between the M kinds of reference voltages V1 to VM and the N-bit data stored in the memories 71 to 74 is represented by M = ^2N when the data is a binary number. For example, when N = 3, M = 8, and when N = 4, M = 16.

Reference numeral 30 denotes a gate driver, which comprises a shift register 31 and drivers DV1 to DV4 provided corresponding to the respective gate lines Y1 to Y4.
The shift register 31 starts operating in response to a start signal T3 supplied from the control circuit 40A, and drives the TFT for each line of the liquid crystal panel 10 by stepping up by a clock CK2 also supplied from the control circuit 40A. Generate signals sequentially. Note that the start signal T3 has the same cycle as the vertical synchronization signal VS, and the clock CK2 has the same cycle as the horizontal synchronization signal HS. Drivers DV1 to DV4
Functions as a binary output circuit that performs level conversion from the output of the shift register 31 to a voltage that can control ON and OFF of the TFT, and outputs the voltage to the corresponding gate lines Y1 to Y4. Thus, the analog switch T
The switch function can be turned on / off by controlling the gate voltage of the FT, and the signal voltage of the image data on the data lines X1 to X4 output from the data driver 20A is set to 1
Data can be written to the liquid crystal capacitor through the TFT for each line.

FIG. 10 shows details of the decoder 81 and the selector 91 in FIG. In the configuration shown in the figure, a decoder 81 decodes digital data D0 to D3 stored in a corresponding memory 71, and based on the decoding result, turns on only one analog switch in a selector 91 to turn on a reference voltage V1 to D3. An example in which one voltage is selected from V16 is shown. That is, this case corresponds to the case where N is four.

In the examples shown in FIGS. 9 and 10, the number of pixels is shown as 4 × 4 for the sake of simplicity of description, but as described above, in an actual LCD, 640 lines in the horizontal direction and 480 lines in the vertical direction. Total of 640 x 480 = 3072
A typical example is to drive 00 pixels, and a very large data driver is required for this purpose. In addition, since it is necessary to have pixels for red (R), green (G), and blue (B) for color display, the total number of pixels is three times this. Further, in order to perform gradation control for bringing color expression closer to full color, it is necessary to increase the number of bits of the data driver described with reference to FIG. For example, in the configuration of FIG. 10, the data driver has 4 bits (D0 to D3) and a voltage value of 16 (V1 to V16). However, in order to express a full color of 640 × 480 pixels, each color is required. And the number of analog switches is required to be 64, and as a result, 64 × 3 ×
640 = 122880 analog switches would be required. Accordingly, 64 types of reference voltages given from outside the data driver are required. Memories 61 to 64 and memory 7 for further increasing the number of gradations
It goes without saying that the scale of digital circuits such as 1 to 74 and decoders 81 to 84 increases.

As described above, the conventional LCD has various problems associated with an increase in the number of gradations of the data driver. In view of this, the present inventor has previously provided a new data driver circuit that solves such a problem. One configuration example is shown in FIG. FIG. 12 shows a configuration of a main part thereof, and FIG. 13 shows an operation timing chart including an example of a voltage waveform on a data line.

Referring first to FIG. 11, in the data driver 20B, the shift register 21 starts operating by a start signal T1 supplied from the control circuit 40B line by line, and a clock CK1 also supplied from the control circuit 40B. And the timing signals TS1 to T
Generate S4. The memories 61 to 64 include the control circuit 40B
N-bit image data DT1 to DTN for one line supplied through
Hold in response to 4. At this time, the image data is written while being divided into upper bit groups DTQ to DTN and lower bit groups DT1 to DTP. Next, the memories 71 to 74
After the data is written to the memories 61 to 64, the data in the memories 61 to 64 is fetched in response to the timing signal T2 from the control circuit 40B before the data of the next line arrives. The decoders 81A to 84A store the upper bit group data DTQ stored in the memories 71 to 74, respectively.
~ DTN is decoded. Next, selectors 91 to 94
Selects and outputs one of four types of reference voltages output from the reference power supply circuit 50B based on the decoding results of the corresponding decoders 81A to 84A. The image data corresponding to the reference voltage selected and output as described above is output to the corresponding data lines X1 to X4 via the analog switches S1 to S4, respectively. At this time, the reference power supply circuit 5
The reference voltages V1A to V4A (see FIG. 12) generated from 0B are DC, and the DC voltage charges the distributed capacitance of each data line. Each switch S1 to S4 is a 1-bit memory B1 to B4 provided for each data line.
, And each of the memories B1 to B4 is 1
At the beginning of the line time, each is set by a timing signal T4 supplied from the control circuit 40B, whereby the switches S1 to S4 are turned on. The operation mode up to this point is the same as the above-described conventional example (see FIGS. 9 and 10), and corresponds to the operation up to time point t1 shown in FIG.

In the example shown in FIGS. 11 to 13, after this time t1, the data transmitted to the data line is further changed using the lower bit group data DT1 to DTP stored in the second memories 71 to 74. I try to make it. For this purpose, a counter 51 and a digital / analog (D / A) conversion circuit 52 are provided in the reference power supply circuit 50B, and the counter 51 is cleared by the timing signal T2 and the clock CK3 is cleared.
To generate a staircase voltage by passing it through the D / A conversion circuit 52, add this staircase voltage to the DC reference voltages VR1 to VR4, and send it to each data line. An example of the waveform in this case is shown in FIG.

The data DT1 to DTP of the lower bit group in the second memories 71 to 74 are input to the corresponding comparison circuits C1 to C4, respectively, and are compared with the output by the counter 51. When the two match based on the comparison result, a match signal is output to the corresponding memories B1 to B4, whereby the memories are reset. At this time, each of the switches S1 to S4 is turned off, the reference voltage at that time is held in the distributed capacitance on the data line, and thereafter, the charge held in the distributed capacitance causes the liquid crystal capacitance to be charged through the TFT. Will be done. Thus, a voltage corresponding to the image data of each data line is applied to the data line. The value of the distributed capacitance on the data line is the sum of the capacitance of the liquid crystal present between the data line and the counter electrode as the dielectric, and the capacitance of the dielectric at the intersection of the data line and the gate line as the dielectric. Is essentially formed by This value is 100 for a 10.4 inch liquid crystal panel with 640 × 480 pixels.
About pF is a typical value. On the other hand, the liquid crystal capacitance is about 1 pF or less, and the change in voltage due to the movement of electric charge does not cause any problem in practical use. This is because, by the time t1, the liquid crystal capacitance has already been charged to a value close to the final value through the TFT, and the remaining voltage may be charged by the electric charge stored in the distribution capacitance of the data line.

FIG. 12 shows details of the decoder 81A, the reference power supply circuit 50B, the selectors 91 to 94, and the liquid crystal panel 10. The illustrated configuration has four types of reference voltages V1A to V4A and four types of selectors 91 to 94.
The case where 16 analog gradations are provided by the number of analog switches is shown. From this configuration, it can be seen that the circuit can be significantly reduced compared to the above-described conventional example (see FIGS. 9 and 10). In particular, when the configuration of the decoder 81A is compared with the configuration of the decoder 81 of FIG. 10, the effect of the reduction can be seen. To make this possible, the reference power supply circuit 50B plays a large role. That is, the reference power supply circuit 50B has the fixed reference voltage value VR1 as described above.
To VR4. Therefore, it is preferable if this reference power supply circuit can be realized with a small number of components.

FIG. 14 shows a configuration of a reference power supply circuit as an example of a conventional type. In the circuit shown in the figure, first, the reference voltage -VA is divided by the resistors R1 to R5 to create four types of reference voltages -VR1 to -VR4, and these voltages are reduced in impedance by the operational amplifiers OP11 to OP14. The staircase wave voltage -VW output from the A conversion circuit DA through the operational amplifier OPA is converted to the operational amplifiers OP21 to OP21.
OP24 and resistors R61 to R64, R71 to R74, and R81 to R84 are added to obtain the signal shown in FIG.
The function of the reference power supply circuit 50B is realized. here,
Each resistor R61-R64, R71-R74 and R81
Generally, R84 has the same resistance value. Further, the operational amplifier OPA and the associated resistors RA and R
B is a reference voltage output V when the staircase voltage -VW is a negative value.
A voltage inverting circuit is configured so that 1A to V4A become positive voltages.

FIG. 15 shows a configuration of a reference power supply circuit as another example of the conventional type. The difference from the circuit shown in FIG. 14 is that the reference voltage is set to a positive voltage of + VA and the D / A
The staircase voltage from the conversion circuit DA is also set to the positive voltage VW, and the reference voltages VR1 to VR4 and the staircase voltage VW are added using the operational amplifiers OP21 to OP24 and the resistors R61 to R64 and R71 to R74. is there. The operational amplifiers OP21 to OP24 at the final stage constitute a non-inverting amplifier circuit that performs voltage amplification to prevent the voltage from attenuating due to the result of the voltage addition. In this case, the gain of each of the operational amplifiers OP21 to OP24 is determined by the resistor R81A.
R84A and resistors R91 to R94.

[0018]

In the above-described conventional configuration, although the form of multi-tone control shown in FIGS. 11 to 13 is an excellent method for expressing full colors,
There is a problem that the scale of the circuit for adding the fixed reference voltage and the staircase voltage in the reference power supply circuit becomes relatively large. This is not preferable because it increases the device scale of the entire LCD, which leads to an increase in cost and an increase in mounting size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device (L
CD) simplifies the configuration of the reference power supply circuit, thereby realizing cost reduction and miniaturization of mounting.

[0020]

According to one aspect of the present invention, as shown in the principle configuration diagram of FIG. 1, a fixed plurality of bits are assigned to an upper bit group of image data. A voltage corresponding to a higher-order bit group is selected from among various kinds of reference voltages, and for the lower-order bit group of the image data, a staircase voltage is added to the plurality of fixed reference voltages to change the reference voltage. In a liquid crystal display device that performs gradation control by selecting a voltage corresponding to a lower bit group from each of the set voltage values and holding the selected reference voltage as an image data voltage in the distribution capacitance of the data line, Resistor R1A to R3A connected in series, and a constant current source IG connected to one end of the resistor string.
And a staircase voltage source DA connected to the other end of the resistor string, and reference voltages V1A to V4A to be supplied to the data lines in response to potentials at connection points of the resistors of the resistor string, respectively. And a plurality of operational amplifiers OP1A to OP4A each of which generates a constant current IB supplied from the constant current source for the upper bit group of the image data. A staircase voltage VW generated from the staircase voltage generator is generated based on a fixed reference voltage obtained by flowing through each resistor, and the lower bit group of the image data is converted to the fixed reference voltage. A reference power supply circuit for a liquid crystal display device is provided, wherein the reference power supply circuit is created by adding.

According to another embodiment of the present invention, as shown in the principle configuration diagram of FIG. 3, the upper bit group of the image data is selected from among a plurality of fixed reference voltages. Is selected, and for the low-order bit group of the image data, a staircase voltage is added to the plurality of fixed reference voltages, and the low-order bit is selected from the respective voltage values obtained by changing the reference voltage. A plurality of resistors R1B to R3B are connected in series in a liquid crystal display device which performs gradation control by selecting a voltage corresponding to a group and holding the selected reference voltage as an image data voltage in a distribution capacitance of a data line. Connected to one end of the resistor string, the staircase voltage generator DA, and a fixed first reference voltage V
Means A1 for adding a staircase voltage VW generated from the staircase voltage generation source to RA, and a second fixed voltage connected to the other end of the resistor string and different from the first reference voltage
Means A2 for adding the staircase voltage to reference voltage VRB
And a plurality of operational amplifiers OP1B to OP4B for respectively generating reference voltages V1B to V4B to be supplied to the data lines in response to the potentials at the connection points of the resistors of the resistor string, respectively. Each of the generated reference voltages is created based on the first and second reference voltages for the upper bit group of the image data, and the staircase voltage is generated for the lower bit group of the image data. A reference power supply circuit for a liquid crystal display device is provided, wherein the reference power supply circuit is created by adding the first reference voltage to the first and second reference voltages.

[0022]

According to the structure shown in FIG. 1, resistors R1A to R3A are connected in series by one less than the required number of fixed reference voltages, one end of which is connected to a constant current source IG, and the other end. Is connected to a staircase voltage source DA, and operational amplifiers OP1A to OP4A are connected to the connection points of the respective resistors to perform low impedance conversion and power enhancement. Therefore, the desired function with fewer components compared to the conventional type,
That is, a function of adding the fixed reference voltage and the staircase wave voltage can be realized. That is, the configuration of the reference power supply circuit can be simplified. This greatly contributes to cost reduction and mounting miniaturization.

The reference voltages V1A to V4A generated from the operational amplifiers OP1A to OP4A are as follows. In this connection, FIG. 2 shows how the reference voltages change over time. V4A = VW V3A = R3A × IB + VW V2A = (R3A + R2A) × IB + VW V1A = (R3A + R2A + R1A) × IB + VW Also, according to the configuration of FIG. 3, the number of resistors R1B is one less than the required number of fixed reference voltages. To R3B are connected in series, and adder circuits A1 and A2 are respectively connected to both ends thereof. Each of the adder circuits has a common output VW of the staircase voltage generator DA and a fixed first and second output. Reference voltage VR
A and VRB are input, and low impedance conversion and power enhancement are performed using the operational amplifiers OP1B to OP4B as in the case of FIG. Therefore, FIG.
As in the case of the first embodiment, the desired function can be realized with a small number of components.

The respective reference voltages V1A to V4A in this case are as follows. FIG. 4 shows how the reference voltages change over time. V4B = VRB + VW V3B = VRB + VW + R3B × (VRA-VRB) /
(R1B + R2B + R3B) V2B = VRA + VW-R1B × (VRA-VRB) /
(R1B + R2B + R3B) V1B = VRA + VW The details of other structural features and operations of the present invention will be described using embodiments described below with reference to the accompanying drawings.

[0025]

FIG. 5 shows an LCD according to a first embodiment of the present invention.
3 shows the configuration of the reference power supply circuit. This embodiment corresponds to the principle configuration of FIG. In comparison with FIG. 1, IG1 corresponds to the constant current source IG, and DA1 corresponds to the staircase voltage generator DA. The constant current source IG1 includes a reference power supply VP, a PNP transistor Q1 having a collector connected to a non-inverting input terminal of an operational amplifier OP1A, a resistor RP1 connected between the base of the transistor and ground, and a It comprises a resistor RP2 connected between the emitter and the reference power supply VP, and a zener diode ZD connected in the opposite direction between the reference power supply VP and the base of the transistor Q1. On the other hand, the staircase voltage generation source DA1 outputs lower bit data D1,
D / A conversion circuit DAC for converting D0 to analog voltage
And an operational amplifier OPA as a voltage follower responsive to the output of the D / A conversion circuit.
Note that this operational amplifier is not essentially required. Other circuit configurations and operations are the same as those in FIG.

In this example, the constant current IB is (VZ-VB
E) Specified by / RP2. Here, VZ is the reverse withstand voltage of the Zener diode ZD, and VBE is the transistor Q
I shows the voltage between the base and the emitter of I. FIG. 6 shows the configuration of a reference power supply circuit according to a second embodiment of the present invention.
This embodiment also corresponds to the principle configuration of FIG. However, the difference from the first embodiment is that a constant current source IG2 is connected to a low voltage side of a plurality of generated reference voltages, and a circuit DA2 for adding a fixed voltage and a staircase voltage is connected to a high voltage side. That is. The constant current source IG2 includes a reference power supply VD and an operational amplifier OPC having a non-inverting input terminal connected to the reference power supply VD.
An NPN transistor Q1A having a base connected to the output terminal of the operational amplifier and an emitter connected to the inverting input terminal of the operational amplifier, and a resistor RQ5 connected between the emitter of the transistor and ground. ing. By inserting the operational amplifier OPC into the feedback circuit in this way, there is an advantage that the operation is not affected by the base-emitter voltage (VBE) of the transistor Q1A. On the other hand, a circuit DA2 that adds the fixed voltage and the staircase voltage includes a D / A conversion circuit DAC that converts the lower bit data D1 and D0 of the image data into an analog voltage, a reference power supply VC,
An operational amplifier OPB, a resistor RQ1 connected between the non-inverting input terminal of the operational amplifier and the reference power supply VC, and a resistor connected between the non-inverting input terminal of the operational amplifier and the output terminal of the D / A conversion circuit DAC RQ2, a resistor RQ3 connected between the output terminal and the inverting input terminal of the operational amplifier, and a resistor RQ4 connected between the resistor and the ground. For other circuit configurations and their operations, see FIG.
The description is omitted because it is the same as in the case of FIG.

FIG. 7 shows a configuration of a reference power supply circuit according to a third embodiment of the present invention. This embodiment corresponds to the principle configuration of FIG. In comparison with FIG. 3, A11
Corresponds to the addition circuit A1, and A21 corresponds to the addition circuit A2. The addition circuit A11 includes an operational amplifier OPD having a non-inverting input terminal grounded, a resistor RE1 connected between the inverting input terminal of the operational amplifier and the negative reference power supply -VE, and a staircase wave connected to the inverting input terminal of the operational amplifier. It comprises a resistor RE2 connected between the output terminals of the voltage source DA, and a resistor RE3 connected between the inverting input terminal and the output terminal of the operational amplifier. Similarly, the adding circuit A21 includes an operational amplifier OPE having a non-inverting input terminal grounded, a resistor RE4 connected between the inverting input terminal of the operational amplifier and the output terminal of the staircase voltage source DA, and It comprises a resistor RE5 connected between the inverting input terminal and the negative reference power supply -VF, and a resistor RE6 connected between the inverting input terminal and the output terminal of the operational amplifier. The other circuit configuration and its operation are the same as those in FIG.

FIG. 8 shows a configuration of a reference power supply circuit according to a fourth embodiment of the present invention. This embodiment also corresponds to the principle configuration of FIG. However, the difference from the third embodiment is that the adders A12 and A22 use reference power supplies VG and VH having positive voltage values as fixed reference voltages, respectively. Therefore, the addition circuit A12 includes an operational amplifier OPF, a resistor RF1 connected between the non-inverting input terminal of the operational amplifier and the positive reference power supply VG, a non-inverting input terminal of the operational amplifier, and the staircase voltage generator DA. , A resistor RF5 connected between the inverting input terminal and the output terminal of the operational amplifier, and a resistor RF6 connected between the resistor and the ground. It is configured. Similarly, the adding circuit A22 includes an operational amplifier OP
G, a non-inverting input terminal of the operational amplifier and a positive reference power supply VH.
And a resistor RF4 connected between the non-inverting input terminal of the operational amplifier and the output terminal of the staircase voltage source DA, and a resistor RF3 connected between the inverting input terminal and the output terminal of the operational amplifier. , And a resistor RF8 connected between the resistor and the ground. The other circuit configuration and its operation are the same as those in FIG.

According to the configuration of each of the above-described embodiments, the desired function, that is, the function of adding the fixed reference voltage and the staircase voltage, can be realized with fewer components compared to the conventional type. In other words, it is possible to simplify the configuration of the reference power supply circuit, thereby reducing costs and mounting.

[0030]

As described above, according to the present invention, it is possible to simplify the structure of a reference power supply circuit in an LCD adapted for multi-tone display, thereby reducing costs and miniaturizing mounting. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of a reference power supply circuit of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the circuit of FIG. 1;

FIG. 3 is a principle configuration diagram of a reference power supply circuit of a liquid crystal display according to another embodiment of the present invention.

FIG. 4 is an operation timing chart of the circuit of FIG. 3;

FIG. 5 is a configuration diagram of a reference power supply circuit according to a first embodiment of the present invention.

FIG. 6 is a configuration diagram of a reference power supply circuit according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a reference power supply circuit according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram of a reference power supply circuit according to a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of an LCD as an example of a conventional type.

FIG. 10 is a configuration diagram of a main part of FIG. 9;

FIG. 11 is a configuration diagram of an LCD as another example of the conventional type.

FIG. 12 is a configuration diagram of a main part of FIG. 11;

FIG. 13 is an operation timing chart of the circuit of FIG. 12;

FIG. 14 is a configuration diagram of a reference power supply circuit as an example of a conventional type.

FIG. 15 is a configuration diagram of a reference power supply circuit as another example of the conventional type.

[Explanation of symbols]

A1, A2: Addition means (addition circuit) R1A to R3A, R1B to R3B: Resistor (resistor string) DA: Staircase voltage generator IG: Constant current source IB: Constant current supplied from constant current source OP1A to OP4A , OP1B to OP4B ... operational amplifiers V1A to V4A, V1B to V4B ... reference voltage generated from a reference power supply circuit VW ... staircase voltage VRA, VRB ... reference voltage generated from staircase voltage generation source

Continuation of the front page (56) References JP-A-3-203778 (JP, A) JP-A-64-78084 (JP, A) JP-A-60-134218 (JP, A) JP-A-5-158446 (JP) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580

Claims (2)

(57) [Claims] 1. A voltage corresponding to an upper bit group is selected from among a plurality of fixed reference voltages for an upper bit group of image data, and the fixed bit voltage is selected for a lower bit group of the image data. A staircase voltage is added to a plurality of types of reference voltages, a voltage corresponding to the lower bit group is selected from each voltage value obtained by changing the reference voltage, and the selected reference voltage is imaged on the distribution capacitance of the data line. In a liquid crystal display device that performs gradation control by holding the data voltage, a resistor string in which a plurality of resistors (R1A to R3A) are connected in series, and a constant current source (IG) connected to one end of the resistor string. )
A staircase voltage source (DA) connected to the other end of the resistor string; and a reference voltage to be supplied to the data line in response to a potential at a connection point of each resistor of the resistor string. V1A to V4A), each of which includes a plurality of operational amplifiers (OP1A to OP4A), and each of the reference voltages generated from the operational amplifiers is supplied from the constant current source to a higher-order bit group of the image data. A staircase voltage generated from the staircase voltage source is generated based on a fixed reference voltage obtained by flowing a constant current (IB) through each of the resistors. A reference power supply circuit for a liquid crystal display device, which is created by adding (VW) to the fixed reference voltage. 2. A voltage corresponding to the upper bit group is selected from a plurality of fixed reference voltages for the upper bit group of the image data, and the fixed bit voltage is selected for the lower bit group of the image data. A staircase voltage is added to a plurality of types of reference voltages, a voltage corresponding to the lower bit group is selected from each voltage value obtained by changing the reference voltage, and the selected reference voltage is imaged on the distribution capacitance of the data line. In a liquid crystal display device that performs gradation control by holding as a data voltage, a resistor string in which a plurality of resistors (R1B to R3B) are connected in series; a staircase voltage generator (DA); Means (A1) connected to one end for adding a staircase voltage (VW) generated from the staircase voltage source to a fixed first reference voltage (VRA); and a means connected to the other end of the resistor string. Means (A2) for adding the staircase voltage to a fixed second reference voltage (VRB) different from the first reference voltage, and a response to a potential at a connection point of each resistor of the resistor string. And a plurality of operational amplifiers (OP1B to OP4B) for respectively generating reference voltages (V1B to V4B) to be supplied to the data lines, wherein each of the reference voltages generated from the operational amplifiers is an upper bit of the image data. For the group, the staircase voltage is created based on the first and second reference voltages, and for the lower-order bit group of the image data, the staircase voltage is added to the first and second reference voltages. A reference power supply circuit for a liquid crystal display device, which is created.