JPH07210119A - Data line driving circuit for multi-level active drive type liquid crystal display device - Google Patents

Abstract

PURPOSE:To perform a display precisely in a device with a large number of gradation related to a 'data line driving circuit for a multi-level display active drive type liquid crystal display device. CONSTITUTION:In the data line driving circuit for a liquid crystal display device provided with a reference power source circuit 50P successively generating a staircase reference voltage adding a voltage corresponding to a low-order bit group to plural kinds of fixed voltages corresponding to an high-order bit group of the image data and an applied voltage selection means 22 selecting so that the reference voltage corresponding to the high-order bit group is applied to a data line and stopping the application of the reference voltage to the data line when the voltage corresponding to the low-order bit group is added, the reference power source circuit 5OP generates the reference voltage changing so as to become the voltage becoming larger in an initial part and the voltage adding the voltage corresponding to the low-order bit group in remaining parts in respective steps of the staircase voltage at every kind.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device (LC
The present invention relates to D) and, more particularly, to a data line driving circuit used in an LCD adapted for multi-gradation display. LCD is expected as a display device that replaces the conventional CRT,
It is expected to develop into a large market. Therefore, the technological development is actively done. Among them, especially thin film transistors (TFTs)
The LCD using r) is capable of high-quality display in principle and has a high display speed, so that it is expected to become the mainstream of high-speed and high-quality color display.

[0002]

2. Description of the Related Art In an LCD using a TFT, the TFT is used as a switching element, and an analog voltage signal (information) proportional to the magnitude of an image data signal is written through the TFT corresponding to the liquid crystal capacity of each pixel. , Display images. FIG. 17 is a diagram showing an entire configuration of a conventional general TFT type LCD, FIG. 18 is a diagram showing in detail the decoder 81, selector 91, and reference power supply circuit 50 shown in FIG. 17, and FIG. It is a figure which shows the structural example of a liquid crystal pixel. In the illustrated example, the number of pixels is shown as 4 × 4,
The system for controlling the display is shown as a so-called digital driver system. P11 to P44 in the figure represent pixels which are the minimum units of image display. A TFT is a transistor switch in each pixel represented by Q11 to Q44 in FIG. 19, and is a liquid crystal capacitance C _{mn of} each pixel.
It plays a role of a switch when writing a signal voltage for display to (m, n = 1 to 4). In this figure, the arrangement of pixels in the horizontal direction is called one line, and the data for display on the LCD is written simultaneously to the pixels in this one line, and this is repeated about 60 times per second, and this is seen by the human eye. Show as a flicker-free image.

The actual number of pixels of the LCD is 4 × in this explanatory diagram.
Much more than 4, 640 horizontally and 48 vertically
Although it is a typical example to have about 0, here, for simplification of description, it is shown as 4 × 4. In the case of color display, red (R), green (G) and blue (B)
Since it is necessary to have another pixel, the number of pixels as a whole is tripled.

The operation of writing image data into each pixel will be described with reference to FIG. In FIG. 17, HS indicates a horizontal synchronizing signal, VS indicates a vertical synchronizing signal, and D1 to DN indicate image data. N represents the number of bits for gradation display. CLK
Is a timing signal (clock) that is given in synchronization with the image data, and gives a timing for writing the image data D1 and D2. The clock signal CLK can be generated internally by measuring the cycle of the horizontal synchronizing signal HS, and is not essentially required as an interface.

Reference numeral 40 denotes a control circuit for controlling the entire LCD, which generates various control signals for writing the image data D1 to DN in response to the horizontal synchronizing signal HS, the vertical synchronizing signal VS and the clock CLK. Reference numeral 50 denotes a reference power supply circuit that generates a plurality of types of reference voltages V1 to VM. Reference numeral 20 denotes a data driver, which is a shift register 21.
And memories 61 to 64 each having an N-bit capacity
And a memory 71 each having a capacity of N bits.
To 74, decoders 81 to 84, and selectors 91 to 94
Have and.

In the data driver 20, the shift register 21 starts its operation for each line by the start signal T1 supplied from the control circuit 40, and advances by the clock CK1 similarly supplied by the control circuit 40 to make a timing signal. Generate TS1 to TS4. Memories 61 to 6
Reference numeral 4 denotes timing data TS1 to TS for displaying data DT1 to DTN supplied through the control circuit 40, respectively.
Captured in response to 4 (that is, writing of data). Further, the memories 71 to 74 respond to the timing signal T2 from the control circuit 40 with the data in the memories 61 to 64 after the data is written in the memories 61 to 64 and before the data of the next line arrives. Capture (write data). The decoders 81 to 84 respectively include the memories 71 to 7
The digital data stored in 4 is decoded. The selectors 91 to 94 select and output any of the plurality of types of reference voltages V1 to VM output from the reference power supply circuit 50 based on the decoding results of the corresponding decoders 81 to 84. That is, the selectors 91 to 94 function as a kind of digital-analog conversion circuit for generating analog signals corresponding to the digital data stored in the memories 71 to 74. In this way, one of the M types of voltages V1 to VM is selected and output to the data lines X1 to X4. M type reference voltages V1 to VM and memories 71 to
The relationship with the N-bit data stored in 74 is represented by M = 2 ^N when the data is a binary number. For example, when N = 3, M = 8, and when N = 4, M = 16.

[0007] The shift register 21 and the memories 61 to
The data driver portion composed of 64, 71 to 74, decoders 81 to 84, and selectors 91 to 94 is normally integrated. However, the reference voltage V
The reference power supply circuit 50 for generating 1 to VM is usually not included in the integrated circuit. This is because the data driver 20 required for the LCD is usually composed of a plurality of ICs, whereas one reference power supply circuit 50 may be provided in common.

In order to write the data voltages X1 to X4 output from the data driver 20 into the liquid crystal capacitance through the TFT, it is necessary to control the data voltage of the TFT which is an analog switch to turn the switch on and off. The gate driver 30 fulfills this function.
The gate driver 30 includes a shift register 31 and a driver DV provided corresponding to each of the gate lines Y1 to Y4.
1 to DV4. Shift register 31
Starts operation by a start signal T3 supplied from the control circuit 40, and advances by a clock CK2 also supplied from the control circuit 40 to turn on the TFT for each line of the liquid crystal panel 10. It occurs sequentially. The start signal T3 has the same cycle as the vertical synchronizing signal VS, and the clock CK2 has the same cycle as the horizontal synchronizing signal HS. The drivers DV1 to DV4 are the shift register 3
A binary value that performs level conversion from the output of 1 to a voltage that can control ON / OFF of the TFT, generates either a voltage that can turn the TFT off or a voltage that can turn it on, and outputs the voltage to the corresponding gate lines Y1 to Y4. Functions as an output circuit. As a result, the gate voltage of the TFT, which is an analog switch, can be controlled to turn on / off the switch function, and the signal voltage of the image data on the data lines X1 to X4 output from the data driver 20 can be set line by line. It is possible to write to the liquid crystal capacitance through the TFT.

FIG. 18 is a diagram showing details of the decoder 81 and the selector 91 in FIG. In the configuration shown in the figure, the decoder 81 decodes the digital data D1 to D4 stored in the corresponding memory 71, and based on the decoding result, only one analog switch in the selector 91 is turned on to turn on the reference voltages V1 to D4. An example of selecting one voltage from V16 is shown. That is, this case corresponds to the case where N is 4 described above.

FIG. 19 is a diagram showing an example of the configuration of the liquid crystal display section 10 of FIG. 17, in which each pixel P11 to P44 includes a plurality of data lines X1 to X4 and a plurality of gate lines Y1 to Y4. From a transfer gate (TFT) arranged at the intersection and transmitting voltage information on the corresponding data line when the corresponding gate line is selected, and a liquid crystal capacitance storing the information transmitted via the corresponding TFT. It is configured. As described above, a simple 4 × 4 configuration is shown here for the sake of simple explanation of the driving method, but in an actual LCD, a total of 640 × 480 = 480 in the horizontal direction and 480 lines in the vertical direction = Generally, there are 307,200 pixels, and the data driver for driving this requires a very large scale. In addition, since it is necessary to have pixels for red (R), green (G) and blue (B) for color display, the total number of pixels is 3
Doubled. Further, in order to perform the gradation control for bringing the color expression closer to the full color, it is necessary to increase the number of bits of the data driver described in FIG. For example, in FIG.
In the configuration of 8, the number of bits is 4 (D1 to D4) and the voltage value is 1
Although the data driver is 6 (V1 to V16), the number of gradations required for each color to express 260,000 colors called full color is 64, and the number of analog switches is 64 for each data line. Required, 6 as a whole
This requires 4 × 3 × 640 = 122880 analog switches. Further, accordingly, 64 types of reference voltages given from the outside of the data driver are required. To further increase the number of gradations, the memories 61 to 6
It goes without saying that the scale of the digital circuits such as 4, the memories 71 to 74, the decoders 81 to 84, etc. becomes large.

As described above, the conventional LCD has various problems as the number of gradations of the data driver increases. In view of this, the applicant of the present application has disclosed a new data driver circuit for solving such a problem in Japanese Patent Application Laid-Open No. 5-158446. That is, the scale of the digital circuit increases with the increase in the number of gray scales, the chip area increases due to the increase in the number of analog switches, the number of signal lines for the reference voltage supplied from the outside to the data driver increases, and This solves the problem of an increase in the number of data signal lines. Although some examples are shown in the above-mentioned publication, a typical example thereof is shown in FIG. FIG. 21 is a diagram for explaining the principle of the invention disclosed in the above publication, FIG. 22 is a diagram showing a configuration of a main part thereof, and FIG. 23 is an operation including an example of a voltage waveform on a data line. It is a figure which shows a timing.

FIG. 20 shows the entire configuration. In the data driver 20A, the shift register 21 has a start signal T supplied from the control circuit 40A for each line.
1 to start the operation, and stepwise by the clock CK1 also supplied from the control circuit 40A, and the timing signal T
S1 to TS4 are generated. The memories 61 to 64 output the N-bit image data DT1 to DTN for one line supplied through the control circuit 40A to the timing signal TS, respectively.
Hold in response to 1 to TS4. First-stage memory 61 to
When the data is gathered in 64, the data in the memories 61 to 64 are transferred to the memories 71 to 74 in the second stage before the data of the next line arrives in response to the timing signal T2 from the control circuit 40B. The memories 61 to 64 are released to hold the image data of the next line. Memory 61
The image data in 64 to 71 and 74 to 74 are high-order bit groups DT.
It is divided into Q to DTN and lower bit groups DT1 to DTP and stored. The data of the upper bit group is the decoder 81A-
84A, and the selector 91 corresponding to the image data
˜94 to convert a single analog switch select signal. Then, one of the analog switches in the selectors 91 to 94 is turned on, one of the reference voltages in the reference power supply circuit 50 is selected, and is output to the corresponding data line X1 to X4. Fixed reference voltages VR1 to VR4 are output as V1A to V4A from the reference power supply circuit 50A. The DC voltage of the reference voltages V1A to V4A charges the distributed capacitance of each data line. Selector 9
Analog switches S1 to S4 in series with 1 to 94 are 1-bit memories B1 to B1 provided for each data line.
B4 controls each memory, and each memory B1 to B4
Are set by the timing signal T4 supplied from the control circuit 40A at the beginning of one line time, whereby the switches S1 to S4 are turned on. The operation mode up to this point is the operation up to the time t1 in FIG. 23, which is the same as the conventional example in FIG. 17 described above, but next, the data of the lower bit group in the second memories 71 to 74 is The characteristic of this conventional example is that the voltage corresponding to the data of the lower bit group is set in a time division manner by further changing the data to be sent to the data line by using the data.

In order to make such a change, the reference power supply circuit 50A has a counter 51 and a digital-analog (D-A) conversion circuit 52, and the counter 51 is cleared by the timing signal T2 and the clock CK3 is used. A staircase wave voltage is generated by stepping it and passing it through the D-A conversion circuit 52, and this staircase wave voltage is used as a DC reference voltage VR.
1 to VR4 are added and sent to each data line.
An example of the waveform in this case is shown in FIG.

On the other hand, the lower bit group data DT1 to DTP in the second memories 71 to 74 are input to the corresponding comparison circuits C1 to C4 and compared with the output of the counter 51. When the two match based on the result of this comparison, a match signal is output to the 1-bit memories B1 to B4 for each corresponding data line, whereby these memories B1 to B4 are reset. At this time, each analog
The switches S1 to S4 are turned off, the reference voltage at that time is held in the distributed capacitance on the data line, and thereafter, the liquid crystal capacitance is charged through the TFT by the charge held in the distributed capacitance. Become. In this way, the voltage corresponding to the image data of each data line is applied to the data line. The value of the distributed capacitance on the data line is the sum of the capacitance of the liquid crystal existing between the data line and the counter electrode as the dielectric and the capacitance of the insulator at the intersection of the data line and the gate line as the dielectric. Are essentially formed by This value is 10.
For a 640 x 480 pixel 4-inch LCD panel, 1
A typical value is about 00 pF. On the other hand, the liquid crystal capacitance is 1 pF
It is not more than a degree, and the change in voltage due to the movement of charges causes no problem in practical use. This is because the liquid crystal capacitance has already been charged to a value close to the final value through the TFT by the time of t1, and the remaining voltage may be charged by the charge accumulated in the distributed capacitance of the data line.

FIG. 21 is a diagram for explaining the principle of the conventional example shown in FIG. 20, where (1) is an equivalent circuit and (2) is an equivalent circuit.
Shows a time chart. In the figure, VA represents a reference voltage obtained by adding a staircase voltage to a fixed reference voltage, and SW is an analog switch in the selectors 91 to 94 for selecting a voltage corresponding to image data from VA. Further, RD represents the equivalent resistance of the data line, and CD is the equivalent capacitance of the data line. Q is a TFT as an analog switch, and CL is a liquid crystal capacitance. Typical values of these in the case of a color liquid crystal panel having a diagonal of 10.4 inches and a number of pixels of 640 × 480 are RD of 10 K ohm, CD of 100 pF, and CL of about 1 pF. The on-resistance of Q, which is a TFT, is designed so that the image voltage can be sufficiently charged within one horizontal synchronizing period. 640x
In the case of a liquid crystal panel with 480 pixels, one horizontal synchronization period is about 3
Since it is 0 microsecond, the writing time to the TFT is 2
It is usually designed to be within 0 microseconds. For example, since the time for charging within 0.1% of error may be 6.9 times the time constant, the on-resistance of the TFT And the equivalent time constant, which is the product of the liquid crystal capacitance, is 20 / 6.9 =
It should be 2.9 microseconds or less. From this value, the TFT
The on-resistance of 1 may be about 2.9 M ohms or less. Then, assuming that the time from t0 to t1 is 8 microseconds and the time of one step of the staircase voltage is 3.0 microseconds in the time chart shown in (2) of FIG. 21, the switch SW from t0 to t3 is When the VR value is 4.2V and the step voltage value for one step is 0.2V, the approximate value of the voltage charged in the liquid crystal capacitance before the switch is turned off is about 4.3V. Further, at the time of t3, the holding voltage on the equivalent distributed capacitance CD on the data line is 4.6V. Therefore, the voltage value by the redistribution of the charge of CD and the charge of CL after the time t3 is expressed by the following equation.

(100 × 4.6 + 1 × 4.3) / (100 + 1) = 4.597V (1) This value has an error of 0.1% or less with respect to an ideal charging voltage value of 4.6V. Is. As described above, the error can be reduced in this way, when the switch SW is turned off, the liquid crystal capacitance CL is already charged with a voltage of about 4.3V, and the voltage difference from the final value is 0.3V. Because it is getting smaller. It should be noted that the time constant of movement of charges for redistributing charges is determined by the liquid crystal capacitance CL and the equivalent capacitance CD of the data line.
Is given as the product of the series combined capacitance of Q and the on resistance of Q,
In the above numerical example, it is about 2.9 microseconds. On the other hand, the time allowed for redistribution of charges is 30−17 = 13 microseconds, which is 4.5 times the time constant of redistribution of charges of 2.9 microseconds. .3V
Is charged up to an error of about 0.3 / EXP (4.5) ≈3.3 mV, and there is no problem.

FIG. 22 shows the decoder 81A shown in FIG.
Of the reference power supply circuit 50A, the selectors 91 to 94, and the liquid crystal panel 10 in detail. The configuration shown in the figure is 16 by four types of reference voltages V1A to V4A and four analog switches in each of the selectors 91 to 94.
The case where the gradation of the value is given is shown. It can be seen that by adopting such a configuration, it is possible to significantly reduce the number of circuits as compared with the conventional example shown in FIG. In particular, the configuration of the decoder 81 shown in FIG. 18 and the decoder 8 shown in FIG.
The effect of the reduction can be seen by comparing with the configuration of 1A.

[0018]

As described above, as shown in FIG.
In the conventional example shown in FIG. 17, compared with the conventional general example shown in FIG. 17, it is possible to significantly reduce the number of circuits, and by adopting this circuit, the driving circuit of the multi-gradation liquid crystal display device can be There is an effect that the cost can be significantly reduced. However, in spite of its excellent method, this conventional example has a limit when increasing the number of stairs to increase the number of gradations. This is because when the resistance value and the capacitance value of the data line are large, the speed of charging the data line in response to the change in the staircase becomes slow, and an error occurs when the charging time becomes short. This problem will be described with reference to FIG. FIG. 24 (1) is a diagram showing an equivalent circuit in the charging operation. The actual data line is a distributed constant circuit, which is different from such a simple model, but can be qualitatively analyzed by the first-order low-pass filter shown here. In the figure, the resistor RD indicates the equivalent resistance value of the data line, and CD indicates the equivalent capacitance. 24 (2) shows a signal source VS that is a staircase wave.
And the output waveform VB are shown.
It is shown as a response waveform when the time T of the stage, the time constant of charging, and RD × CD are equal. When the charging error is calculated as e1, e2, e3, ... For each step wave in this figure, the error can be expressed by the following equation.

EN = ΔVm (1-m ^N ) / (1-m) (2) Here, N represents the step number, and m is EXP (-T /
τ), ΔV is the voltage value of one staircase wave, T is the time of one staircase wave, and τ is the time constant of charging. Specifically, RD × CD
Is. When the error is calculated by applying a specific numerical value in the actual device to this formula, it becomes as shown in Table 1.

[0020]

[Table 1]

In Table 1, m is EXP (-2) = 0.13.
5, EXP (-1) = 0.368, EXP (-0.5)
= 0.607 is shown. As can be seen from this result, when the charging time constant is large, the error increases and the difference becomes large. The error calculated in Table 1 is obtained by dividing the error by ΔV and normalizing it. That is, the error value is 1
Means that the final voltage charged in each staircase wave differs from the true value by exactly one level of voltage value.

The errors shown in Table 1 are large, and when the number of gradations is increased, this error becomes a problem as an error in gradation display. The present invention is intended to solve such a problem, and drives a liquid crystal display device capable of reducing an error in gradation display even when the number of gradations is increased by the simple driving circuit shown in FIG. The purpose is to realize the circuit.

[0023]

FIG. 1 is a diagram showing the principle configuration of the present invention. In the data line drive circuit of the gradation display active drive type liquid crystal display device of the present invention which realizes the above object, the reference power supply circuit 50P outputs the image data to each of a plurality of types of fixed voltages corresponding to the upper bit group of the image data. A plurality of types of reference voltages that change in a staircase waveform to which a voltage corresponding to the lower bit group is added are sequentially generated, and the applied voltage selection unit 22 applies the reference voltage corresponding to the higher bit group of the image data to the data line. When the voltage corresponding to the lower bit group of the image data is applied, the application of the reference voltage to the data line is stopped. Thus, the gradation control is performed by holding the reference voltage at the time of stopping the application in the distributed capacitance of the data line as image data. In such a data line drive circuit, in order to achieve the above object, the reference power supply circuit adds a voltage corresponding to the lower bit group of the image data in the initial portion at each stage of the reference voltage that changes in a staircase waveform. It is characterized in that a voltage whose amount of change is larger than the voltage is output, and a reference voltage that changes so as to become a voltage added with a voltage corresponding to the lower-order bit group of the image data in the remaining portion is generated for each type. .

FIG. 2 shows a driving circuit as described above.
It is a principle block diagram of the present invention which showed the example of the basic composition of the circuit which realizes a standard power supply circuit by the block diagram.
0P is a fixed parallel reference voltage source V that generates a plurality of types of fixed voltages corresponding to the upper bit group of the image data, and a staircase wave generation that sequentially generates a voltage that changes in a staircase waveform corresponding to the lower bit group of the image data. Means S, pulse generation means P for generating a pulse corresponding to the initial portion of each step of the staircase voltage, and addition means A for adding them are characterized.

Another circuit that realizes the reference power supply circuit is a resistor string in which a plurality of resistors are connected in series, a constant current source connected to one end of the resistor string, a staircase voltage generator, and a pulse. Generating means, adding means for adding the output of the staircase voltage generating means and the output of the pulse generating means and connected to the other end of the resistance string, and the potential at the connection point of each resistor of the resistance string, respectively. It can also be realized by providing a plurality of operational amplifiers which respectively generate the reference voltage to be supplied to the data line in response.

[0026]

FIG. 3 is a diagram for explaining the principle of the present invention. (1) shows an equivalent circuit including data lines,
(2) shows the voltage waveform of each part in the equivalent circuit. Figure 3
(1), VP is the output of the pulse generating means P in FIG. 1, VL is the output of the staircase wave generating means S, VR
Is the output of the fixed parallel reference voltage source V. SW is an analog switch in the data driver 20P shown in FIG. 2, which turns off when the data line is charged to a value corresponding to the display data. RD and CD are the equivalent resistance and equivalent capacitance of the data line, respectively. Q is a TFT and CL is a liquid crystal capacitance. VA is the output of the adding means A, VB is the input voltage value to Q of the data voltage passed through the data line, and VC is the charging voltage value to the liquid crystal capacitance.

FIG. 4 shows the state of charging in FIG. 3 when the relationship between the charging time constant τ = RD × CD and the pulse voltage is changed, and it can be seen that the charging voltage waveform differs depending on the conditions. Case 1 is the first pulse voltage VN
Shows the case where the charging voltage VK is smaller than the final voltage VM of the staircase wave, Case 2 shows the case where this value VK is larger than VM, and Case 3 shows the case where VK = VM. VK in charging and the final voltage value VL in charging are represented by the following equation.

VK = VN (1−EXP (−TP / τ)) (3) VL = VM + (VK−VM) EXP (−TQ / τ) (4) The charging error ΔE is expressed by the following equation. It ΔE = VM−VL (5) The condition for Case 3 is obtained by setting VK = VM in Expression (3) and is as shown in the following Expression.

VM = VN (1−EXP (−TP / τ)) (6) By adjusting VN or TP so as to satisfy the expression (6), charging as in case 3 is performed. . For example, if TP = τ, VN may be represented by the following equation. VN = VM (1 / e) = 2.7VM (7) The charging waveform example in FIG. 3 shows the case 2 in FIG.

In any case, by appropriately selecting the pulse conditions, it is possible to reduce the difference between the final charge value and the desired charge value at each stage. FIGS. 3 and 4 show an example in which the voltage value of the staircase wave sequentially increases and the pulse is positive. However, the voltage value of the staircase wave may decrease in order, and in that case, the pulse value becomes negative. You can

[0031]

FIG. 5 is a diagram showing the overall structure of an LCD as a first embodiment of the present invention, in which a grayscale voltage corresponding to the lower bit group shown in FIG. FIG. 2 is an embodiment in which the present invention is applied to an example, and a reference power source is shown in FIG.
It is realized by the configuration shown in the principle configuration diagram of.

The difference between the conventional example shown in FIG. 20 and the present example is that a pulse generator 53 is added to the reference power source 50B as shown in the figure, and the adder has three inputs accordingly. And the pulse generator 53 in the control circuit 40B.
That is, the function of generating a signal for controlling the above is provided, and in the present embodiment, upper 2 bits and lower 2 bits are supplied as image data.

FIG. 6 is a diagram showing an example of the voltage waveform on the data line and an example of the voltage waveform output from the reference power source in this embodiment. The circuit of FIG. 5 outputs four types of reference voltages as shown in (2) of FIG. That is, the fixed reference voltage is 1.8V (VR1), 2.6V (VR
2) 3.4V (VR3) and 4.2V (VR4) are output, and a staircase wave increasing by 0.2V is added to this,
Further, in the first half of each step of the staircase wave, a pulse of a little less than 0.2 V is added, and the changing reference voltage is output as shown.

The voltage waveform on the data line when such a reference voltage is applied to the data line is as shown in (1) of FIG. The corresponding image data is shown on the right side of the figure. For example, when the upper 2 bits are “1,0” and the lower 2 bits are “1,0”, the voltage supply line having the third fixed reference voltage of 3.4 V is selected, and this voltage supply line is 3 The switch is disconnected at the time of the third step when the voltage reaches 0.8V. Here, the case where the voltage value of the pulse is slightly larger than the ideal case and the voltage on the data line overshoots by a small amount as in case 2 of FIG. 3 is shown. By appropriately selecting the conditions, it is possible to obtain a voltage waveform as in case 3 of FIG. In any case, by selecting conditions that approximate such a voltage waveform, the voltage of the data line at the end of each step is approximately equal to the desired fixed reference voltage plus the staircase voltage. Therefore, the error can be reduced.

In the embodiment of FIG. 5, the adder has three inputs,
Although the configuration in which the fixed reference voltage, the staircase wave voltage, and the pulse voltage are added at the same time is used, various modifications that simplify the circuit configuration are possible. FIG. 7 is a diagram showing the first modification of the reference power source 50B in more detail. In FIG. 7, reference numeral 52 denotes an analog / digital converter (D-) that converts the lower bit data D2 and D1 of the image data output from the control circuit 40B into an analog voltage that changes stepwise.
A). Reference numeral 53 is a pulse generator that generates a pulse in the first half of each step of the staircase wave. VR is the reference voltage V
A is divided by resistors R1 to R5 to generate four types of reference voltages VR1 to VR4, and these voltages are set to an operational amplifier OP1.
1 to OP14, which is a portion for reducing the impedance and outputting. The adder for adding the above outputs is a first adder AD1 for adding the output of the D / A converter 52 and the output of the pulse generator 53, the reference voltages VR1 to VR4 and the output of the first adder AD1. It is composed of a second adder AD2 composed of four adders for adding respectively. Second adder AD
Any of the two adders has resistors R61 to R64, R71 to
It is composed of R74 and operational amplifiers OP21 to OP24, and the gain of each adder is resistors R81A to R84A.
And the resistors R91 to R94. By thus adding one 2-input adder, the 3-input adder can have 2 inputs.

Further, the applicant of the present invention filed Japanese Patent Application No. 4-248024.
8 discloses a configuration that simplifies a circuit that adds a voltage that changes in a stepwise manner to a plurality of fixed reference voltages.
Shows a modification of the reference power supply realized by adding a pulse generator to the circuit example disclosed therein. In FIG. 8, IG is a reference power supply VP, a PNP transistor Q1 whose collector is connected to the non-inverting input terminal of the operational amplifier OP1A, a resistor RP1 connected between the base of this transistor and ground, and a transistor Q1. A resistor RP2 connected between the emitter and the reference power supply VP,
It is a constant current source composed of a reference power supply VP and a Zener diode ZD connected in the opposite direction between the base of the transistor Q1. The SPG is a staircase pulse voltage generator that generates a signal obtained by adding a staircase wave signal and a pulse signal, and a DA converter DAC that converts the lower bit data D2 and D1 of the image data into an analog voltage that changes like a staircase wave. , A pulse generator 53 that generates a pulse signal and an adder circuit AD3 that adds those signals, and generates a voltage obtained by adding a staircase wave and a pulse to the first fixed reference voltage. The staircase pulse voltage generator SPG has a constant current source IG and a resistor R1.
Since a voltage obtained by adding a staircase wave and a pulse to a fixed reference voltage is generated in each resistor portion by being connected via A, R2A, and R3A, the operational amplifiers OP1A to OP4A reduce the impedance and output. As is clear from comparison between FIGS. 5 and 7 and FIG. 8, by using the configuration shown in FIG. 8, the number of operational amplifiers and resistors can be reduced and the circuit can be simplified.

In the above example, the addition of pulses is all performed by analog signals. However, after the addition of staircase waves and pulses by digital signals, the added signals are converted into digital signals by a DA converter. It is also possible. FIG. 9 is an example of such a reference power supply circuit. As shown in FIG. 9, the difference between the conventional example shown in FIG. 20 and the reference power supply circuit shown in FIGS. 5, 7 and 8 is that the output of the counter 51 corresponds to the digital signal from the control circuit 40B corresponding to the pulse. The point is that an adder AD4 for adding signals is provided, and the output thereof is converted into an analog signal by the DA converter 52. Therefore, the addition with the fixed reference voltages VR1 to VR4 can be performed by the 2-input adder as in the conventional case.

In the first embodiment, the voltage value of the staircase wave sequentially increases and the pulse is also positive, but it is also possible to use the staircase wave whose voltage value sequentially decreases. In the second embodiment, the voltage value is increased. It is an embodiment to which the present invention is applied when a staircase wave whose value decreases in order is used. FIG. 10 is a diagram showing the structure of the liquid crystal display device of the second embodiment, and FIG. 11 is a diagram showing an example of the voltage waveform on the data line and the waveform of the reference power source in the second embodiment.

The difference between the first embodiment and the second embodiment is that the staircase wave added to the fixed reference power source decreases in sequence as described above. The reference voltages VR1 to VR4 are higher than the reference voltage of FIG. 6 by 2.4V (VR1) and 3.2V (V
R2), 4.0V (VR3), 4.8V (VR4) are generated, and the DA converter 52 converts the output of the counter 51 into a negative analog voltage value and decreases by 0.2V in order. A staircase wave is generated, and the pulse generator 53 also generates a negative pulse of a little less than 0.2V. As a result, the reference power supply waveform as shown in (2) of FIG. 11 is obtained.

The output of the counter 51 is logically inverted and then input to the comparators C1 to C4. Therefore, when the lower bit is "1, 1", it is disconnected at the first step of each reference voltage, that is, when each fixed reference voltage is output, and when it is "1, 0", the voltage of the next step is output. The voltage of the data line is set such that it is disconnected when it is on. Also in this case, since the negative pulse is applied, the voltage at each step of the staircase wave becomes a desired voltage in a short time.

In the first embodiment, since a positive pulse is further added to each reference voltage changing on the staircase wave, the maximum voltage output from the reference power source becomes larger by the amount of the pulse.
Therefore, the voltage input to the selectors 91 to 94 becomes high, and there is a possibility that the voltage level at which the analog switch inside the selector can be turned on and off is exceeded, and it is necessary to increase the operating voltage range of the analog switch accordingly. It was
However, if the configuration of the second embodiment is used, the maximum voltage output from the reference power source does not increase, so there is no such fear, and driving with a higher degree of freedom becomes possible.

Further, in the liquid crystal display device, there is a problem that the liquid crystal material is polarized when an electric field is applied to only one side. In order to prevent such a problem, the voltage applied to the liquid crystal element is alternately switched between positive and negative voltages. In such a case, when applying a positive voltage,
As in the second embodiment, the step wave and the negative pulse that decrease in sequence are added, and when the negative voltage is applied, the step wave and the positive pulse that increase in order are added.

In the first and second embodiments, in order to detect that the voltage of the step wave corresponding to the lower bit of the image data is output, the value of the lower bit and the step wave of each data line are detected. Although the comparator for comparing the value of the counter indicating the step is provided, since the step of the staircase wave changes at a predetermined time, this can be time-controlled.

The third embodiment is an example of controlling the disconnection of the switch when the voltage of the staircase wave corresponding to the lower bit of the image data is output, and the configuration thereof is shown in FIG. As shown in the figure, the difference between the third embodiment and the first embodiment is that the 1-bit memory Bi (i = 1 to 4) for each data line and the comparator Ci (i = 1 to 4) in the first embodiment. ) Instead of the reference time generator TB and the selection circuit Gi (i = 1 to 1).
4) is provided, and other points are the same as the configuration of the first embodiment.

FIG. 13 is a diagram showing a circuit configuration of the reference time generator TB and the selection circuit G1 in the third embodiment. Figure 1
3, the reference time generator TB is composed of 9 inverters, 7 NOR circuits, 3 NAND circuits, and the selection circuit G1 is 2 inverters, 4 NOR circuits, 5 NAND circuits. It is composed of a NAND circuit. FIG. 14 is a time chart of the third embodiment. The operation of the third embodiment will be described with reference to these drawings.

When the signal T2 which activates the pulse generator is "low (L)" and the signal T5 is "L", the circuit is activated and the output TBi (i = i = i) of the reference time generator TB is output.
1 to 4) are all “high (H)”. Output D1 of counter 51 by clock signal CK3A to counter 51
As the C and D0C change, the reference time generator TB
Output TBi (i = 1 to 4) changes as shown in the figure. D
1 and D2 are lower bit data, and one of the outputs TBi is selected by the selection circuit G1 according to this data. For example, if D1 and D2 are "1, 0", TB3
Is selected and TB3 is output as E1. TB3 becomes "L" at the end of the third step, so
The switch S1 is disconnected at this point and the data line X
1 is the voltage immediately before that. In this way, the voltage corresponding to the image data is applied to the data line. Also in the third embodiment, in the first half of each step, a voltage higher than the voltage obtained by adding the staircase to the reference voltage is output from the reference power supply, and in the second half, the voltage obtained by adding the staircase to the reference voltage is output from the reference power supply. Therefore, the voltage of the data line becomes a desired voltage in a short time.

In the first to third embodiments, an analog switch is provided between the selector and the data line, but this analog switch is for disconnecting the reference power supply line and the data line, and By providing such a function, it is possible to omit the analog switch. The fourth embodiment is such an example, and its configuration is shown in FIG. The fourth embodiment, as shown,
Analog switch Si (i = 1 to 4) from the third embodiment
It has a configuration excluding.

FIG. 16 is a diagram showing details of the decoder and selector in the fourth embodiment. Selectors 91-9
4 has a function equivalent to that of the analog switch Si (i = 1 to 4) because it can take a state in which any reference voltage supply line from the reference power source 50B is not connected to the data lines X1 to X4. Therefore, if the selector is not connected while the voltage corresponding to the lower bit is output, the data line becomes the voltage at that time.

The embodiments of the present invention have been described above.
The configurations of the characteristic parts of the third and fourth embodiments are the same as those of the first and second embodiments.
It is obvious that the present invention can be applied to the embodiment, and it is also apparent that the modification of the reference power source described in the first embodiment can be applied to the second to fourth embodiments. .

[0050]

As described above, according to the present invention, it is possible to realize a liquid crystal display device having a large number of gradations with high display accuracy, thereby achieving cost reduction and miniaturization of mounting. it can.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a data line drive circuit of a multi-gradation display active drive type liquid crystal display device of the present invention.

FIG. 2 is a diagram showing a basic configuration example of a reference power supply of the present invention.

FIG. 3 is a diagram for explaining the principle of the present invention.

FIG. 4 is a diagram showing the relationship between the magnitude of the charging voltage and the charging waveform in the present invention.

FIG. 5 is an overall configuration diagram of a first embodiment of the present invention.

FIG. 6 is a time chart showing an example of a voltage waveform on a data line and an example of a waveform of a reference power source in the first embodiment.

FIG. 7 is a circuit diagram showing a modified example (1) of the reference power supply.

FIG. 8 is a circuit diagram showing a modified example (2) of the reference power supply.

FIG. 9 is a circuit diagram showing a modified example (3) of the reference power source.

FIG. 10 is an overall configuration diagram of a second embodiment of the present invention.

FIG. 11 is a time chart showing a voltage waveform example on a data line and a waveform example of a reference power source in the second embodiment.

FIG. 12 is an overall configuration diagram of a third embodiment of the present invention.

FIG. 13 is a circuit diagram showing a reference time generator and a selection circuit in the third embodiment.

FIG. 14 is a time chart showing a voltage waveform example on a data line and a waveform example of a reference power supply in the third embodiment.

FIG. 15 is an overall configuration diagram of a fourth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a decoder and a selector in the fourth embodiment.

FIG. 17 is a diagram showing an overall configuration of a liquid crystal display device as a conventional example.

18 is a circuit diagram showing a decoder, a selector, and a reference power source of the liquid crystal display device of FIG.

FIG. 19 is a diagram showing a configuration example of a liquid crystal display unit.

FIG. 20 is a diagram showing a configuration of a conventional liquid crystal display device that supplies gray scale voltages in a time division manner.

FIG. 21 is an explanatory diagram of the operation principle of the circuit of FIG. 20.

22 is a detailed diagram of the decoder / selector of FIG. 20. FIG.

FIG. 23 is a waveform example and a time chart example on the data line in the conventional example of FIG. 20.

24 is an explanatory diagram of a problem in the conventional example of FIG.

[Explanation of symbols]

 10 ... Liquid crystal panel 22 ... Applied voltage selection means 20i ... Data driver 40i ... Control circuit 50i ... Reference power supply

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroyuki Isogai 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (11)

[Claims] 1. A data line drive circuit of a multi-gradation active drive type liquid crystal display device, wherein each of a plurality of types of fixed voltages corresponding to an upper bit group of image data corresponds to a lower bit group of the image data. A reference power supply circuit (50P) that sequentially generates a plurality of types of reference voltages that change in a staircase waveform to which a voltage is applied, and a reference voltage that corresponds to a higher-order bit group of the image data are selected to be applied to the data line. And an applied voltage selection means (22) for stopping the application of the reference voltage to the data line when the voltage corresponding to the lower bit group of the image data is applied.
In a data line drive circuit of a liquid crystal display device for performing gradation control by holding a reference voltage at the time of stop of application in a distributed capacitance of a data line as image data, the reference power supply circuit (50P) changes in the stepwise waveform. At each stage of the reference voltage, a voltage whose change amount is larger than the voltage added with the voltage corresponding to the lower bit group of the image data is output in the initial portion, and the voltage corresponding to the lower bit group of the image data is output in the remaining portion. A data line drive circuit for a multi-gradation active drive type liquid crystal display device, wherein a reference voltage that changes so as to have a voltage added thereto is generated for each type. 2. The reference power supply circuit (50P) includes a parallel fixed reference power supply (V) that generates a plurality of types of fixed voltages corresponding to the upper bit group of image data, and a staircase corresponding to the lower bit group of the image data. A staircase wave generating means (S) for sequentially generating a wavelike voltage, a pulse generating means (P) for generating a pulse corresponding to an initial portion of each step of the staircase voltage, and an addition for adding them The data line drive circuit of a multi-gradation active drive type liquid crystal display device according to claim 1, further comprising means (A). 3. The reference power supply circuit includes a resistor string (R1A to R3A) in which a plurality of resistors are connected in series,
Constant current source (IG) connected to one end of the resistor string
A staircase voltage generating means (DAC), a pulse generating means (53), and an adding means connected to the other end of the resistor string for adding the output of the staircase voltage generating means and the output of the pulse generating means ( AD3), and a plurality of operational amplifiers (OP1 to OP4) each generating a reference voltage to be supplied to the data line in response to the potential of the connection point of each resistor of the resistor string. The data line drive circuit of the multi-gradation active drive type liquid crystal display device according to claim 1. 4. The applied voltage selection means includes a counter (51) provided commonly to data lines for counting the step position of the staircase voltage, and a high-order bit group of data provided for each data line. A first memory (61 to 64) and a second memory (71 to 71) that respectively store the lower bit group.
74), a decoder (81A to 84A) for decoding the data of the first memory, and a selector (91 to 9) for selecting the plurality of types of reference voltages according to the outputs of the decoder.
4), a comparator (C1 to C4) for comparing the count value of the counter and the stored value of the second memory, and an analog switch (C1 to C4) for switching the connection between the selector and the data line according to the output of the comparator. S1 to S4), and the selected reference voltage when the comparator shows a match is held as image data in the distributed capacitance of the data line. Data line drive circuit of the multi-gradation active drive type liquid crystal display device of. 5. The applied voltage selecting means is provided for each data line, a counter provided for each data line to count the step position of the staircase voltage common to the data lines, and an upper bit group and a lower bit group of the data. First memorize each
A memory, a second memory, a comparator for comparing the count value of the counter with the stored value of the second memory, a decoder for decoding the data of the first memory, and an output of the decoder and an output of the comparator. A selector for selecting one of the plurality of types of reference voltages or for selecting a non-connection state without selecting any of the plurality of reference voltages; and a comparator for comparing the count value of the counter with the stored value of the second memory. 4. The method according to claim 1, further comprising: holding the selected reference voltage in the distributed capacitance of the data line as image data by turning off the selector when the comparator indicates a match. A data line drive circuit of the multi-gradation active drive type liquid crystal display device according to any one of claims. 6. The reference voltage generator for generating a plurality of signals which are in an active state corresponding to the steps of the staircase-shaped voltage, which is provided in common to the data lines, and the applied voltage selection means, and each data line. A first memory and a second memory which are respectively provided to store a high-order bit group and a low-order bit group of data, a decoder which decodes the data of the first memory, and a plurality of types of the references according to the output of the decoder. A first selector for selecting a voltage, a second selector for selecting the output of the reference time generator according to a stored value of the second memory, and a selector and a data line for selecting the output of the second selector according to the output of the second selector. An analog switch for switching the connection is provided, and the voltage when the analog switch of the reference voltage selected corresponding to the upper bit group is disconnected is The data line drive circuit of a multi-gradation active drive type liquid crystal display device according to claim 1, wherein the distributed line capacitance is held as image data. 7. The applied voltage selection means includes a reference time generator provided in common for data lines, which generates a plurality of signals corresponding to the steps of the staircase voltage, and each data line. A first memory and a second memory for storing the upper bit group and the lower bit group of the data, a decoder for decoding the data of the first memory, and the reference time generation according to the stored value of the second memory. A second selector for selecting the output of the converter, and selecting a plurality of types of reference voltages according to the output of the decoder and the output of the second selector, or setting them in a non-connection state without selecting any of them. 1 selector, and the voltage when the first selector of the reference voltage selected corresponding to the higher-order bit group is disconnected is stored in the distributed capacitance of the data line as image data. The data line drive circuit of a multi-gradation active drive type liquid crystal display device according to claim 1, wherein the data line drive circuit is held. 8. The reference power supply circuit generates a staircase-shaped reference voltage whose voltage sequentially increases, and in each stage of the staircase-shaped reference voltage, the initial part is large and the remaining part is a lower bit group of the image data. The data line drive circuit of the multi-gradation active drive type liquid crystal display device according to claim 1, wherein a reference voltage that changes to become a low voltage obtained by adding a voltage corresponding to is generated for each type. 9. The reference power supply circuit generates a staircase-shaped reference voltage whose voltage gradually decreases, and at each stage of the staircase-shaped reference voltage, the initial part is small, and the remaining part is a lower bit group of the image data. The data line drive circuit of the multi-gradation active drive type liquid crystal display device according to claim 1, wherein a reference voltage that changes to become a high voltage added with a voltage corresponding to is generated for each type. 10. The multi-grayscale according to claim 2, wherein the staircase wave generating unit generates a staircase-shaped reference voltage in which the voltage sequentially increases, and the pulse generating unit generates a positive pulse. A data line drive circuit for an active drive type liquid crystal display device. 11. The multi-grayscale according to claim 2, wherein the staircase wave generating unit generates a staircase-shaped reference voltage in which the voltage sequentially decreases, and the pulse generating unit generates a negative pulse. A data line drive circuit for an active drive type liquid crystal display device.