JP3544996B2 - Multi-tone liquid crystal display - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to an improvement in a multi-tone liquid crystal display device. In particular, the present invention relates to an improvement of a TFT (Thin Film Transister) type multi-gradation liquid crystal display device, which is expected to have a high display speed and excellent display quality. More specifically, the present invention relates to an improvement for providing a TFT-type multi-gradation liquid crystal display device of a driving method capable of preventing a data driver from increasing in scale with an increase in the number of gradations.
[0002]
[Prior art]
Hereinafter, a TFT type multi-tone liquid crystal display device according to the related art will be described with reference to the drawings. FIG. 12 is a configuration diagram of the device, and FIG. 13 is a detailed view of the main part thereof. In FIG. 12, for simplicity of explanation, the number of pixels is 2 × 2, and the system for controlling the display is shown as a digital driver system.
[0003]
12 and FIG. 13 In FIG. 12, HS is a horizontal synchronizing signal, and VS is a vertical synchronizing signal. D1 to DN are video signals, and N represents the number of bits for displaying a gray scale. CLK is a clock signal provided in synchronization with the video signals D1 to DN, and gives timing for writing the video signals D1 to DN. CONT is a control means to which the above signals are input. From this control means CONT, a start signal T1 is output to the first shift register SR1 for each line (arrangement of pixels in the horizontal direction). Further, the clock signal CK1 is output from the control means CONT to the first shift register SR1 . The first shift register SR1 is based on the start signal T1 and the clock signal CK1 of the timing signal for writing the video signal DT1~DTN for sequentially displayed in the memory circuit M ₁₁ · M ₁₂ each having a capacity of N bits and outputs the T ₁₁ · T _12. M ₂₁ · M ₂₂ is a memory circuit having a capacity of N bits each, after the signal data has been written to the M ₁₁ · M _12, stored in M ₁₁ · M ₁₂ before the next image signal arrives This is a memory circuit in which data is written by a signal T2. DC ₁ and DC ₂ are decoder circuits that decode signal data written in each of the memory circuits M ₂₁ and M ₂₂ and output corresponding control signals. E ₁ and E ₂ select and turn on one of a plurality of internal analog switches based on a control signal output from the decoder circuits DC ₁ and DC ₂ , and pass the analog switches through the analog switches. Analog voltage selecting means for outputting an analog voltage corresponding to the video signal to the data lines X ₁ and X ₂ (see FIG. 13). VR is a reference voltage source that generates the same number of types of voltages as the number of gradations. The relationship between the number M of types of voltages generated by the reference voltage source VR and the number N of bits is M = 2 ^N when the video signal data is a binary number. Analog switches in the analog voltage selection means E ₁ and E ₂ are individually provided for each of the M types of voltages. The first shift register SR1 of the memory circuit M ₁₁ · M _12, a memory circuit M ₂₁ · M _22, the decoder circuit DC ₁ · DC _2, analog voltage selecting means E ₁ · E _2, summarizes the reference voltage source VR Data driver DD.
[0004]
Analog voltage output from the data driver DD is written to the liquid crystal capacitor _{C 11 · C 12 · C 21} · C 22 via a transistor switch _{Q 11 · Q 12 · Q 21} · Q 22 consisting TFT in each pixel (See FIG. 13). This writing can be a second on-off by the converter circuit DV1, DV2 signals sequentially outputted for each line to the transistor switch Q ₁₁ to Q ₂₂ of the shift register SR2 is a liquid crystal panel to start the operation by the start signal T3 converted into a voltage level, it is to execute the converted voltage is applied to the gate of the transistor switch Q ₁₁ to Q _22. The second shift register SR2 and the conversion circuits DV1 and DV2 are collectively referred to as a gate driver GD.
[0005]
Incidentally, in FIG., P ₁₁ to P ₂₂ is a pixel which is a minimum unit of a display image, LC is a liquid crystal panel configured with the pixels. In FIG. 13, C ₁ and C ₂ are the distribution capacitances of the data lines for each pixel, and r ₁ and r ₂ are the resistances of the data lines for each pixel.
[0006]
[Problems to be solved by the invention]
By the way, the above-mentioned liquid crystal display device has 2 × 2 pixels for simplicity of description, but in an actual liquid crystal device, a total of 640 × 480 = 307200 of 640 lines in the horizontal direction and 480 lines in the vertical direction. The reality is that a pixel is driven, and a data driver for this is required to be very large. In addition, since each pixel requires separate pixels of R (Red), G (Green), and B (Blue) for color display, the total number of pixels is three times this. Further, gradation expression is performed to bring color expression closer to full color. The required number of gradations for each of the R, G, and B colors for expressing 260,000 colors, called full color, is 64, and the number of analog switches is 64, which is 64 × for full color expression of 640 × 480 pixels. This means that 3 × 640 = 122880 analog switches are required, and even if the circuit is divided into several packages, it is difficult to implement a drive circuit in an LSI with a large chip area.
[0007]
As described above, in the multi-tone liquid crystal display device according to the related art, when the number of gradations is increased in order to bring color expression closer to full color, the number of analog switches increases in proportion to the number of gradations, and the data driver However, it has a disadvantage that it is difficult to implement an LSI due to a large scale.
[0008]
SUMMARY OF THE INVENTION It is an object of the present invention to prevent a data driver from increasing in scale with an increase in the number of gradations and to increase the speed of charging a data line. Is to provide.
[0009]
[Means for Solving the Problems]
The above object is achieved by any of the following means.
First means, in a multi-gradation liquid crystal display device having a data driver (DD) for driving data lines of the liquid crystal panel (LC) a (X _n), the data driver (DD) is the upper bits of the video signal correspondingly voltage generating means for generating a plurality of preset voltage and (VG), is set in advance corresponding to the lower bits of the movies image signal, temporally step voltage generated step voltage changes stepwise A generator (DA, DS) , a voltage adder (A) for adding the step voltage to each of the plurality of voltages, and one of a plurality of voltages output from the voltage adder (A) are inputted. and selected based on the upper bits of the video signal to the data line and a voltage selecting means for supplying _{(X n) (E n)} , a selection in the voltage selecting unit (E _n), the lower bits It is a multi-gradation liquid crystal display device to release based on.
[0010]
The second means is provided in correspondence with each of the counter (CT) for counting in synchronization with the step voltage change and each of the data lines (X _n ) in the multi-tone liquid crystal display device. A comparator (CP _n ) for comparing the output of the counter (CT) with the value of the lower bit is further provided, and the release of the selection by the voltage selection means (E _n ) is performed by the comparator (CP _n ) . This is a multi-tone liquid crystal display device that is based on a matching condition.
[0011]
The third means further comprises a subtraction counter (H _n ) for subtracting based on the lower bit in the multi-tone liquid crystal display device, and the selection of the voltage selection means (E _n ) is canceled. , On the condition that the subtraction counter (H _n ) becomes zero.
[0012]
[Action]
In the multi-tone liquid crystal display device according to the present invention, the data driver (DD) cancels the selection by the voltage selection means (E _n ) based on the lower bits, so that the output resistance can be reduced. . As a result, the speed of charging the data line (X _n ) can be increased.
[0013]
【Example】
Hereinafter, with reference to the drawings, a description will be given of a reference example of the present invention and multi-gradation liquid crystal display devices according to first to third embodiments .
[0014]
FIG. 1 is a principle diagram of a multi-tone liquid crystal display device according to a reference example of the present invention. In this reference example, a plurality of liquid crystal pixels (P _xy ) arranged in a matrix , a horizontal synchronizing signal (HS), a vertical synchronizing signal (VS), a video signal (DN) of a plurality of gradations, and a clock signal (CLK) are used. based on bets and control means is inputted to (CONT), said horizontal synchronizing signal (HS) and the vertical synchronization signal (VS) and said plurality gradation of the image signal (DN), the data lines (X _n ), A data driver (DD) for distributing an analog voltage (VN) corresponding to the video signal (DN) of a plurality of gradations, and the horizontal synchronization signal (HS) and the vertical synchronization signal (VS). First, in a multi-tone liquid crystal display device having a gate driver (GD) for sequentially applying a scanning voltage (VY _m ) to each of the scanning lines (Y _m ) , the data driver (DD) includes the data driver (DD). Video signal (D N) a voltage generating means (VG) for generating a plurality of voltages (VN) corresponding to upper bits, and a step-up voltage (VL) for temporally stepping up corresponding to lower bits of the video signal (DN). , A step-up voltage generating means (DA) for generating the following, an analog voltage adding means (A) for analog-adding the step-up voltage (VL) to each of the analog voltages (VN), and the analog voltage (VN), whichever is the data line analog voltage selecting means for selecting as the (X _n) for each value (E _n), the data lines and the analog voltage selecting means (E _n) provided between the (X _n), the step-up voltage determined based on the lower bits of the video signal (DN) (VL) to each of the data lines (X _n) Voltage applying means for pressurizing a (F _n) and the multi-gradation liquid crystal display device having a.
[0015]
In the multi-tone liquid crystal display device according to the reference example , a digital signal as a video signal is divided into an upper bit group (U in FIG. 1) and a lower bit group (L in FIG. 1). An analog voltage VN roughly set based on each upper bit is made to correspond, and for a lower bit group, a step-up voltage VL temporally changing stepwise with a finely set voltage step common to each upper bit. Alternatively, the analog voltage VN roughly set and the step-up voltage VL or the step-down voltage VD are added to correspond to the step-down voltage VD to obtain an analog voltage corresponding to the video signal. A selection means (for example, an analog switch) is provided for each of the coarsely set analog voltages VN, and one of the plurality of selection means is selected to select an analog voltage corresponding to the video signal. To the data line _Xn . Therefore, the number of selecting means (for example, analog switches) for selectively supplying an analog voltage to the data line _Xn may be the same as the number of the types of the analog voltage VN which is roughly set, and is remarkably different from the prior art. Thus, downsizing of the data driver DD is achieved.
[0016]
The details will be described below with reference to FIGS.
Referring to FIGS. 1 and 2, for example, in the example shown in FIG. 1, binary 4 bits are divided into 2 bits, and upper 2 bits are subjected to digital-analog conversion by the same method as in the prior art, and lower 2 bits are converted. Prepares step-up voltage generating means DA having a common digital / analog converter, generates four kinds of voltages, and superimposes a ramp (step-like) waveform voltage thereon. As an example of this voltage value, it means that a voltage of 2 to 5 V is generated by binary 4 bits, and the voltage value of 1 LSB is (5-2) / (2 ⁴ -1) = 200 mV. Thus, the voltages for the upper two bits are 2.0V, 2.8V, 3.6V, and 4.4V for digital codes 0000, 0100, 1000, and 1100, respectively. This is shown in FIG. 1 as V1, V2, V3, and V4, respectively. On the other hand, the ramp voltage changes from 0.0V to 0.2V to 0.4V to 0.6V with respect to time by the step-up voltage generating means DA having a digital / analog converter for the lower two bits. Generated as This is the step-up voltage VL shown in FIG. Then, the analog voltage adding means A adds the step-up voltage VL and each of the voltages V1 to V4 to obtain V11 to V14. The timing at which the addition of the step-up voltage VL in V11 to V14 is started is determined by the clock CK3 provided from the control means CONT. Note that these voltages may not be values proportional to the video signal but may be non-linear values, and so-called gamma correction can also be realized by the non-linear voltage supply.
[0017]
Next, a description will be given of how a voltage value corresponding to a video signal is written to each pixel. For example, if the digital signal, which is a video signal, is 0110, it corresponds to the upper two bits 01 of the digital signal among the analog voltages 2.0V, 2.8V, 3.6V, and 4.4V. 8V is selected by the analog voltage selecting means (e.g., an analog switch) E _n. The step-up voltage VL is added to the analog voltage 2.8V, the voltage value is changed from 3.0V to 3.2V, and immediately before the next 3.4V, the lower 2 bits 10 of the digital signal are added. based stops supplying the voltage to the data line X _n working voltage applying means F _n with. The distribution capacitance of the data line in each pixel is charged by the voltage of 3.2 V immediately before the stop of the voltage supply. Next, the gate signal is supplied for each line to the scanning line Y _m from the gate driver GD, the TFT is turned on in each pixel by the gate signal, charges charged in the distributed capacitance of the flows out through TFT To charge the liquid crystal capacity. As a result, the voltage corresponding to the video signal is correctly written to the corresponding pixel. The total value of the distribution capacitance is about 100 pF in the case of a liquid crystal display device having a diagonal of 10.4 inches, and the liquid crystal capacitance value is about 1 pF. Is small.
[0018]
FIG. 3 is a configuration diagram of a specific example of a multi-tone liquid crystal display device according to a reference example . The following description is made in a manner complementary to the description of the principle diagram of FIG. 1, and the description of the same parts as those of the conventional example is omitted.
[0019]
Referring to FIG. 3, the data memories M ₁₁ and M ₁₂ and M ₂₁ and M ₂₂ in FIG. 3 are divided into an upper bit group and a lower bit group, which are indicated by U and L. The upper bit group is composed of (NP) bits and the lower bit group is composed of P bits, and is composed of a total of N bits of data. Data of the upper bit group are input to the decoder DC ₁ · DC _2, is converted to a signal in which only one bit is turned on at the same time. Then, by turning on only one of the analog switches in each of the analog voltage selection means E ₁ and E ₂ , one of the voltages V1 to V4 in the voltage generation means VG is selected. At this time, the analog switches S ₁ and S ₂ of the output section are on, and the selected voltage is sent to the data lines X ₁ and X ₂ . At this time, the voltages V11 to V14 have the same value as the voltages V1 to V4 because the counter CT is in the reset state and the output of the step-up voltage generating means DA is zero. Also, the reason why the analog switches S ₁ and S ₂ are turned on is that the 1-bit memories B ₁ and B _{2 for} controlling the analog switches S ₁ and S ₂ are set by the signal T4. Next, after a predetermined time, when the clock CK3 is given from the control means CONT, the counter CT starts counting up, and the output of the step voltage generation means DA increases stepwise. Then, the step-up voltage VL is added to the voltages V1 to V4 and output as voltages V11 to V14. On the other hand, the contents of the counter CT are compared with the lower bit group L of the data memories M ₂₁ and M ₂₂ by the comparators CP ₁ and CP ₂ . Then, when they match, a pulse for resetting the memories B ₁ and B ₂ is generated. Then, at that time, the analog switches S ₁ and S ₂ are turned off. Until the analog switches S ₁ and S ₂ are turned off, the voltage obtained by adding the step-up voltage VL to the voltages V 1 to V 4 is written to the liquid crystal capacitance through the TFT while charging the data line. The above counter CT is reset by the signal T2 (signal for writing digital data from the data memory M ₁₁ · M ₁₂ in the data memory M ₂₁ · M _22). Analog voltage corresponding to the digital data stored in the M ₂₁ · M ₂₂ as described above is written to the liquid crystal capacitor by the addition of analog voltages corresponding to the upper bit group and a lower bit group.
[0020]
There are several methods for forming the analog voltage applied to the data lines other than the method shown in FIG. 3, and examples are shown in FIGS.
Voltage forming method shown in FIG. 4 refer to FIG. 4, in which took the method of subtracting rather than adding a method of synthesizing an analog voltage corresponding to the upper bit group and a lower bit group in the memory M ₂₁ · M _22. In the figure, DS is a step-down voltage generating means for generating a step-down voltage VD that steps down in time, corresponding to the lower bits of the video signal. The description of the other symbols is the same as that of FIG.
[0021]
FIG. 5 shows a change with time of each voltage in FIG. The advantage of the scheme shown in FIG. 4 over the scheme shown in FIG. 3 is that the charging time to the liquid crystal capacitance through the TFT is somewhat reduced by first applying a voltage higher than the final value to the data line _Xn. That is what you can do. However, in order to use this method, it is necessary to process the data voltage to an appropriate value in advance.
[0022]
FIG. 6 shows that the digital / analog converter DAC driven by the counter CT is different from the method shown in FIGS. 3 and 4 in which the fixed voltage and the variable voltage are combined using an adding means. The number corresponding to the upper bit group is prepared, and a voltage corresponding to the fixed voltage prepared in FIGS. 3 and 4 is realized by giving preset values N1 to N4 for this counter.
[0023]
FIG. 7 is a block diagram of the first embodiment . The main difference between the present embodiment and the specific example of the multi-tone liquid crystal display device according to the reference example is that the analog switches S ₁ and S ₂ required for the output section of the data driver DD are eliminated. For this purpose, a point in time when the value of the counter CT matches the value of the lower-order bit group of the data memories M ₂₁ and M ₂₂ is detected, and the output L ₁ and L ₂ of the memories B ₁ and B ₂ that hold the state is used as a decoder DCC. all the entire output of ₁ · DCC ₂ off analog switches in the analog voltage selecting means E ₁ · E ₂ is that which is adapted to turn off. As a result, the data driver DD does not output through two continuous analog switches but outputs through one analog switch, so that the output resistance decreases and the data lines X ₁ and X ₂ are charged. Speed can be increased. FIG. 8 shows a circuit example of DCC ₁ and DCC _{2 in} this case.
[0024]
8 See FIG. 8, the terminal a · b is a terminal for each of the upper 2 bits are input, the terminal c is a terminal to which the output L ₁ · L ₂ of the memory B ₁ · B ₂ is input . The output terminals e _{1 to} e ₄ are terminals for outputting signals for controlling the on / off of the analog switches in the analog voltage selecting means E ₁ and E ₂ .
[0025]
FIG. 9 is a block diagram of the second embodiment . That this embodiment differs from the first embodiment, the output L ₁ · L ₂ of the present embodiment the memory B ₁ · B _2, to clear the memory of a group of high-order bits of the data memory M ₂₁ · M ₂₂ Set to zero. Then, by setting the output corresponding to code 0 to zero among the decode outputs of the decoders DCD ₁ and DCD ₂ , all the analog switches of the analog voltage selecting means E ₁ and E ₂ can be turned off. FIG. 10 shows a configuration example of DCD _n in this case. Descriptions of the reference numerals are the same as those in FIG.
[0026]
FIG. 11 is a block diagram of the third embodiment . That this embodiment differs from the second embodiment, in the present embodiment is that instead of the memory corresponding to the lower bit group of the data memory M ₂₁ · M ₂₂ in the second embodiment, the subtraction counter . This is shown as H ₁ · H _{2 in} FIG. The subtraction counters H ₁ and H ₂ preset the values of the lower bit group of the data memories M ₁₁ and M ₁₂ by the signal T 2, subtract by the clock CK 3, and reset the memories B ₁ and B ₂ when they become zero. . When this is reset, all the analog switches of the analog voltage selection means E ₁ and E ₂ are turned off, as in the case of FIG.
[0027]
【The invention's effect】
As described above, in the multi-tone liquid crystal display device according to the present invention, the data driver cancels the selection by the voltage selection means based on the lower bits, so that the output resistance can be reduced, and the data resistance can be reduced. The speed of charging the wire can be increased.
[Brief description of the drawings]
FIG. 1 is a principle diagram of a multi-tone liquid crystal display device according to a reference example of the present invention.
FIG. 2 is an explanatory voltage waveform diagram of FIG. 1;
FIG. 3 is a configuration diagram of a specific example of a multi-tone liquid crystal display device according to a reference example of the invention.
FIG. 4 is an explanatory diagram of another example of the analog voltage forming method.
FIG. 5 is an explanatory voltage waveform diagram of FIG. 4;
FIG. 6 is an explanatory diagram of still another example of the analog voltage forming method.
FIG. 7 is a configuration diagram of a multi-tone liquid crystal display device according to a first embodiment of the present invention.
8 is a diagram illustrating a configuration example of DCC _n illustrated in FIG. 7;
FIG. 9 is a configuration diagram of a multi-tone liquid crystal display device according to a second embodiment of the present invention.
10 is a configuration example diagram of DCD _n illustrated in FIG. 9;
FIG. 11 is a configuration diagram of a multi-tone liquid crystal display device according to a third embodiment of the present invention.
FIG. 12 is a configuration diagram of a multi-tone liquid crystal display device according to the related art.
FIG. 13 is a detailed view of a main part of FIG. 12.
[Explanation of symbols]
HS Horizontal synchronization signal VS Vertical synchronization signal DN Video signal CLK Clock signal CONT Control means T1, T2, T3 Start signal SR1 First shift register SR2 Second shift register CK1, CK2, CK3 Clock signal M _nm Memory T _1n Timing signal DC _n decoder circuits E _n analog voltage selecting means X _n data lines VR reference voltage source DD data driver Q _nm transistor switch C _nm liquid crystal capacitance DV _m voltage level converting circuit GD gate driver P _xy liquid crystal pixels LC liquid crystal panel C _m distributed capacitance VN Analog voltage Y _m Scan line VY _m Scan voltage VG Voltage generating means VL Step-up voltage DA Step-up voltage generating means A Analog voltage adding means F _n Voltage applying means VD Step-down voltage DS Step-down voltage generating means CT Counter CP _n Comparator S _n Na log switch U upper bits L lower bits B _n memory DAC digital / analog converter DCC _n · DCD _n decoder circuits H _n subtraction counter

Claims (3)

In multi-gradation liquid crystal display device having a data driver (DD) for driving the data lines (X _n) of the liquid crystal panel (LC),
The data driver (DD) includes:
Voltage generating means (VG) for generating a plurality of voltages set in advance corresponding to the upper bits of the video signal;
Step voltage generating means (DA, DS) for generating a step voltage which is set in advance corresponding to the lower bits of the video signal and changes stepwise with time;
Voltage adding means (A) for adding the step voltage to each of the plurality of voltages;
Said voltage adding means to one of a plurality of voltage output from (A), selected on the basis of upper bits of the input video signal, the data line voltage selecting means for supplying (X _n) (E _n) And having
A multi-gradation liquid crystal display device, wherein the selection by the voltage selection means (E _n ) is canceled based on the lower bits. A counter (CT) that counts in synchronization with the step voltage change and a data line (X _n ) are provided corresponding to each of the counters, and compare the output of the counter (CT) with the value of the lower bit. And a comparator (CP _n ) .
2. The multi-gradation liquid crystal display device according to claim 1, wherein the release of the selection by said voltage selection means (E _n ) is based on a matching condition of said comparator (CP _n ) . The subtraction counters (H _n) for subtracting based on the lower bits, further comprising,
2. The multi-gradation liquid crystal display device according to claim 1, wherein the selection by said voltage selection means (E _n ) is released on condition that said subtraction counter (H _n ) becomes zero.

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