JP3110795B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3110795B2
JP3110795B2 JP03136291A JP13629191A JP3110795B2 JP 3110795 B2 JP3110795 B2 JP 3110795B2 JP 03136291 A JP03136291 A JP 03136291A JP 13629191 A JP13629191 A JP 13629191A JP 3110795 B2 JP3110795 B2 JP 3110795B2
Authority
JP
Japan
Prior art keywords
metal layer
layer
forming
current path
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03136291A
Other languages
Japanese (ja)
Other versions
JPH04360537A (en
Inventor
敏志 山口
圭司 野坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP03136291A priority Critical patent/JP3110795B2/en
Publication of JPH04360537A publication Critical patent/JPH04360537A/en
Application granted granted Critical
Publication of JP3110795B2 publication Critical patent/JP3110795B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the side etching of a diffusion preventing metal layer due to battery effect by performing the etching of the diffusion preventing metal formed between a wiring and a bump by using a resist layer as a mask. CONSTITUTION:An aluminum layer 2 and a diffusion preventing layer 3 are laminated and formed in order on a semiconductor layer 2, and the aluminum wiring layer 2 covered with the diffusion preventing metal layer 3 is formed by patterning. An aperture 5 is formed. A metal layer 6 for a current path and an adhesion reinforcement metal layer 7 are laminated and formed in order. A resist layer 8 is formed and eliminated from the region except a bump forming region by patterning. The adhesion reinforcement metal layer 7 is eliminated from the region except the bump forming region by etching using aqua regia. The resist layer 8 is eliminated and a resist layer 9 is newly formed. Said layer 9 is patterned and eliminated from the bump forming region. Thus, an aperture 10 is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置のバンプ形
成方法の改良に関する。
The present invention relates to an improvement in a bump forming method for a semiconductor device.

【0002】[0002]

【従来の技術】図3に従来技術に係るバンプの形成工程
図を示す。
2. Description of the Related Art FIG. 3 shows a process diagram of forming a bump according to the prior art.

【0003】同図(a)に示すように、アルミニウム配
線2の形成されている半導体層1上にPSG等の絶縁膜
4を形成し、これをパターニングしてアルミニウム配線
2上から除去して開口5を形成する。
As shown in FIG. 1A, an insulating film 4 such as PSG is formed on a semiconductor layer 1 on which an aluminum wiring 2 is formed, and is patterned and removed from the aluminum wiring 2 to form an opening. 5 is formed.

【0004】同図(b)に示すように、5000Å厚のチタ
ンよりなる拡散防止金属層3と5000Å厚の白金よりなる
密着強化金属層7とをスパッタ法を使用して順次積層形
成する。次に、レジスト層15を形成し、これをパターニ
ングしてバンプ形成領域を除く領域から除去し、次い
で、王水を使用して密着強化金属層7をエッチングして
バンプ形成領域を除く領域から除去する。
As shown in FIG. 1B, a diffusion preventing metal layer 3 made of titanium and having a thickness of 5000 mm and an adhesion strengthening metal layer 7 made of platinum and having a thickness of 5000 mm are sequentially laminated by sputtering. Next, a resist layer 15 is formed, and the resist layer 15 is patterned and removed from the region excluding the bump formation region. Then, the adhesion strengthening metal layer 7 is etched using aqua regia and removed from the region excluding the bump formation region. I do.

【0005】同図(c)に示すように、レジスト層15を
除去して新たにレジスト層16を形成し、これをパターニ
ングしてバンプ形成領域から除去して開口10を形成し、
拡散防止金属層3を電流パスとして金メッキをなし、開
口10内にバンプ11を形成する。
As shown in FIG. 1C, the resist layer 15 is removed to form a new resist layer 16, which is patterned and removed from the bump formation region to form an opening 10,
Gold plating is performed using the diffusion preventing metal layer 3 as a current path, and a bump 11 is formed in the opening 10.

【0006】同図(d)に示すように、レジスト層16を
除去し、密着金属層7をマスクとして、アンモニアと過
酸化水素水との混合液を使用してエッチングをなし、露
出している拡散防止金属層3を除去する。
As shown in FIG. 1D, the resist layer 16 is removed, and etching is performed using a mixed solution of ammonia and hydrogen peroxide with the adhesive metal layer 7 as a mask, thereby exposing the resist layer 16. The diffusion preventing metal layer 3 is removed.

【0007】[0007]

【発明が解決しようとする課題】白金よりなる密着強化
金属層7をマスクとしてチタンよりなる拡散防止金属層
3をエッチングするときに、白金とチタンとの間の電池
効果によって拡散防止金属層3が大きくサイドエッチン
グされ、こゝからエッチング液が侵入することによって
アルミニウム配線2が腐蝕もしくは変質し、さらには、
アルミニウム配線2とバンプ11との間に存在すべき拡散
防止金属層3が消滅してバリア性がなくなり、半導体装
置の信頼性が著しく低下することがある。
When the diffusion preventing metal layer 3 made of titanium is etched using the adhesion strengthening metal layer 7 made of platinum as a mask, the diffusion preventing metal layer 3 is formed by a battery effect between platinum and titanium. The aluminum wiring 2 is corroded or deteriorated due to the large side etching, and the etching liquid penetrates through the side etching.
The diffusion preventing metal layer 3 that should be present between the aluminum wiring 2 and the bump 11 disappears and loses the barrier property, and the reliability of the semiconductor device may be significantly reduced.

【0008】本発明の目的は、この欠点を解消すること
にあり、拡散防止金属層のサイドエッチングを防止して
アルミニウム配線の腐蝕・変質を防ぐとゝもに、アルミ
ニウム配線とバンプとの間のバリア性を確実に保持しう
るようにするバンプの形成方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate this drawback, and to prevent side-etching of the diffusion preventing metal layer to prevent corrosion and deterioration of the aluminum wiring, and to reduce the distance between the aluminum wiring and the bump. An object of the present invention is to provide a method for forming a bump which can surely maintain a barrier property.

【0009】[0009]

【課題を解決するための手段】上記の目的は、下記いず
れの手段によっても達成される。
The above object is achieved by any of the following means.

【0010】第1の手段は、半導体層上にバンプを形成
する半導体装置の製造方法であって前記半導体層上に
金属配線と拡散防止金属層からなる積層体とを形成し、
該積層体上に絶縁膜を形成し、該絶縁膜をパターニング
して前記積層体上から除去して、該積層体上に第1の開
口を形成し、前記絶縁膜と前記第1の開口との上に、前
記拡散防止金属層と実質的に同程度の拡散防止効果を有
する金属よりなる電流パス用金属層を形成し、前記電流
パス用金属層上に密着強化金属層を形成し、該密着強化
金属層をパターニングして、前記バンプの形成領域を除
く領域の前記密着強化金属層を除去し、前記電流パス用
金属層と前記密着強化金属層との上にレジスト層を形成
し、該レジスト層をパターニングし前記バンプの形成領
域のレジスト層を除去して、前記密着強化金属層上に第
2の開口を形成し、前記電流パス用金属層に電流を流す
ことによりメッキを行い、前記密着強化金属層上にバン
プを形成し、該密着強化金属層をマスクとして前記電流
パス用金属層を除去する工程を有する半導体装置の製造
方法である。
[0010] The first means is to form a bump on a semiconductor layer.
A method of manufacturing a semiconductor device , comprising:
Forming a metal wiring and a laminate made of a diffusion preventing metal layer,
Forming an insulating film on the laminate and patterning the insulating film;
To remove from the laminate, and place a first opening on the laminate.
Forming an opening, and forming a port on the insulating film and the first opening;
It has substantially the same diffusion prevention effect as the diffusion prevention metal layer.
Forming a current path metal layer made of metal
Forming an adhesion-enhancing metal layer on the pass metal layer and strengthening the adhesion
Pattern the metal layer to remove the bump formation area.
The metal layer for the current path is removed
Forming a resist layer on the metal layer and the adhesion-enhancing metal layer
And patterning the resist layer to form a bump formation region.
Area of the resist layer is removed, and a second
2 and an electric current is applied to the current path metal layer.
Plating, and a bump is formed on the adhesion strengthening metal layer.
And forming the current through the adhesion-enhancing metal layer as a mask.
It is a method of manufacturing a semiconductor device including a step of removing a pass metal layer .

【0011】第2の手段は、半導体層上にバンプを形成
する半導体装置の製造方法であって、前記半導体層上に
金属配線を形成し、該金属配線上に絶縁膜を形成し、該
絶縁膜をパターニングして前記金属配線上から除去し
て、前記金属配線上に第1の開口を形成し、前記絶縁膜
と前記第1の開口との上に、拡散防止金属層を形成し、
該拡散防止金属層をパターニングして、前記バンプの形
成領域を除く領域の前記拡散防止金属層を除去し、前記
絶縁膜と前記拡散防止金属層との上に、前記拡散防止金
属層と実質的に同程度の拡散防止効果を有する金属より
なる電流パス用金属層を形成し、前記電流パス用金属層
上に密着強化金属層を形成し、該密着強化金属層をパタ
ーニングして、前記バンプの形成領域を除く領域の前記
密着強化金属層を除去し、前記電流パス用金属層と前記
密着強化金属層との上にレジスト層を形成し、該レジス
ト層をパターニングし前記バンプの形成領域のレジスト
層を除去して、前記密着強化金属層上に第2の開口を形
成し、前記電流パス用金属層に電流を流すことによりメ
ッキを行い、前記密着強化金属層上にバンプを形成し、
該密着強化金属層をマスクとして前記電流パス用金属層
を除去する工程を有する半導体装置の製造方法である。
The second means is to form a bump on a semiconductor layer
A method of manufacturing a semiconductor device, comprising:
Forming a metal wiring, forming an insulating film on the metal wiring,
Pattern the insulating film and remove it from above the metal wiring
Forming a first opening on the metal wiring;
Forming a diffusion preventing metal layer on the first opening and the first opening;
The diffusion preventing metal layer is patterned to form the bumps.
Removing the diffusion preventing metal layer in the region excluding the formation region,
On the insulating film and the diffusion preventing metal layer, the diffusion preventing metal
Metals that have substantially the same anti-diffusion effect as the metal layer
Forming a current path metal layer, wherein said current path metal layer
Forming an adhesion reinforcing metal layer thereon, and patterning the adhesion reinforcing metal layer.
To remove the bump forming area
Removing the adhesion strengthening metal layer, the current path metal layer and the
Forming a resist layer on the adhesion-enhancing metal layer;
Patterning the resist layer and forming a resist in the region where the bump is to be formed.
Removing the layer to form a second opening over the adhesion enhancing metal layer;
By flowing a current through the current path metal layer.
Doing a stick, forming a bump on the adhesion strengthening metal layer,
The current path metal layer using the adhesion strengthening metal layer as a mask.
Is a method for manufacturing a semiconductor device having a step of removing a semiconductor device.

【0012】[0012]

【作用】拡散防止金属層のエッチングはレジスト層をマ
スクとしてなされるので電池効果によるサイドエッチン
グは防止され、サイドエッチング量は少なくなる。な
お、サイドエッチング量を考慮してレジストマスクを予
め大きく形成しておけば、所望の形状に拡散防止金属層
を形成することは容易である。
Since the diffusion preventing metal layer is etched using the resist layer as a mask, side etching due to the battery effect is prevented, and the amount of side etching is reduced. If a large resist mask is formed in advance in consideration of the amount of side etching, it is easy to form a diffusion preventing metal layer in a desired shape.

【0013】バンプ形成前に拡散防止金属層3をパター
ニングしてしまうので、拡散防止金属層3を電界メッキ
用電流パスとして使用できなくなるが、その対策として
は新たに電流パス用金属層6を形成することゝした。こ
の電流パス用金属層6はメッキ電流を流すためのみに使
用されるので極めて薄く形成することができる。したが
って、この電流パス用金属層6を密着強化金属層7をマ
スクとしてエッチング除去する場合のサイドエッチング
量は極めて僅かとなり、エッチング液の侵入によってア
ルミニウム配線2が腐蝕もしくは変質したり、または拡
散防止金属層3が消滅してバリア性がなくなるといった
問題は発生しなくなる。
Since the diffusion preventing metal layer 3 is patterned before the bumps are formed, the diffusion preventing metal layer 3 cannot be used as a current path for electroplating. As a countermeasure, a new current path metal layer 6 is formed. I did it. Since the current path metal layer 6 is used only for flowing a plating current, it can be formed extremely thin. Therefore, when the current path metal layer 6 is removed by etching using the adhesion strengthening metal layer 7 as a mask, the amount of side etching is extremely small. The problem that the layer 3 disappears and the barrier property is lost does not occur.

【0014】[0014]

【実施例】以下、図面を参照して、本発明の二つの実施
例に係るバンプの形成方法について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, a method for forming a bump according to two embodiments of the present invention will be described below.

【0015】第1例 図1にバンプの形成工程図を示す。 First Example FIG. 1 shows a process diagram for forming bumps.

【0016】同図(a)に示すように、半導体層1上に
スパッタ法を使用して1〜2μm厚のアルミニウム層2
と5000Å厚のチタンよりなる拡散防止金属層3とを順次
積層形成し、これをパターニングして拡散防止金属層3
で覆われたアルミニウム配線2を形成する。次いでPS
G等の絶縁膜を形成し、これをパターニングして配線2
上から除去して開口5を形成する。
As shown in FIG. 1A, an aluminum layer 2 having a thickness of 1 to 2 μm is formed on a semiconductor layer 1 by sputtering.
And a diffusion preventing metal layer 3 made of titanium having a thickness of 5000 mm are sequentially formed and then patterned to form a diffusion preventing metal layer 3.
The aluminum wiring 2 covered with is formed. Then PS
An insulating film such as G is formed, and is patterned to form a wiring 2
The opening 5 is formed by removing from above.

【0017】同図(b)に示すように、スパッタ法を使
用して100Å厚のチタンよりなる電流パス用金属層6
と5000Å厚の白金よりなる密着強化金属層7とを順次積
層形成する。次に、レジスト層8を形成し、これをパタ
ーニングしてバンプ形成領域を除く領域から除去し、次
いで、王水を使用してエッチングをなし、バンプ形成領
域を除く領域から密着強化金属層7を除去する。
As shown in FIG. 1B, a current path metal layer 6 made of titanium and having a thickness of 100.degree.
And an adhesion strengthening metal layer 7 made of platinum having a thickness of 5000 mm are sequentially laminated. Next, a resist layer 8 is formed, and the resist layer 8 is patterned and removed from the region excluding the bump formation region. Then, etching is performed using aqua regia, and the adhesion reinforcing metal layer 7 is formed from the region excluding the bump formation region. Remove.

【0018】同図(c)に示すように、レジスト層8を
除去し、新たにレジスト層9を形成し、これをパターニ
ングしてバンプ形成領域から除去して開口10を形成す
る。次いで、電流パス用金属層6を電流パスとして使用
して金メッキをなし、開口10内にバンプ11を形成する。
As shown in FIG. 1C, the resist layer 8 is removed, a new resist layer 9 is formed, and the resist layer 9 is patterned and removed from the bump formation region to form an opening 10. Next, gold plating is performed using the current path metal layer 6 as a current path, and a bump 11 is formed in the opening 10.

【0019】同図(d)に示すように、レジスト層9を
除去し、密着強化金属層7をマスクとして、アンモニア
と過酸化水素水との混合液をエッチャントとして使用し
てエッチングをなし、100Å厚の薄い電流パス用金属
層6をエッチング除去する。
As shown in FIG. 1D, the resist layer 9 is removed, and etching is performed using the adhesion strengthening metal layer 7 as a mask and a mixed solution of ammonia and hydrogen peroxide as an etchant. The thin current path metal layer 6 is removed by etching.

【0020】第2例 図2にバンプの形成工程図を示す。 Second Example FIG. 2 shows a process of forming bumps.

【0021】同図(a)に示すように、半導体層1上に
アルミニウム配線2を形成する。次いで、PSG等の絶
縁膜4を形成し、これをパターニングして配線2上から
除去して開口5を形成する。
As shown in FIG. 1A, an aluminum wiring 2 is formed on a semiconductor layer 1. Next, an insulating film 4 such as PSG is formed, and is patterned and removed from the wiring 2 to form an opening 5.

【0022】同図(b)に示すように、スパッタ法を使
用して5000Å厚のチタンよりなる拡散防止金属層3を形
成する。次に、レジスト層12を形成し、これをパターニ
ングしてバンプ形成領域を除く領域から除去し、次い
で、アンモニアと過酸化水素水との混合液を使用してエ
ッチングをなし、バンプ形成領域を除く領域から拡散防
止金属層3を除去する。
As shown in FIG. 1B, a diffusion preventing metal layer 3 made of titanium and having a thickness of 5000 mm is formed by using a sputtering method. Next, a resist layer 12 is formed, and the resist layer 12 is patterned and removed from the region excluding the bump formation region, and then etched using a mixed solution of ammonia and hydrogen peroxide to remove the bump formation region. The diffusion preventing metal layer 3 is removed from the region.

【0023】同図(c)に示すように、レジスト層12を
除去し、スパッタ法を使用して100Å厚のチタンより
なる電流パス用金属層6と5000Å厚の白金より密着強化
金属層7とを順次積層形成する。次に、レジスト層13を
形成し、これをパターニングしてバンプ形成領域を除く
領域から除去し、次いで、王水を使用してエッチングを
なし、バンプ形成領域を除く領域から密着強化金属層7
を除去する。
As shown in FIG. 3C, the resist layer 12 is removed, and a current-pass metal layer 6 made of 100-mm thick titanium and a metal layer 7 made of platinum 5000 mm-thick are strengthened by a sputtering method. Are sequentially laminated. Next, a resist layer 13 is formed, and the resist layer 13 is patterned and removed from the region excluding the bump formation region. Then, etching is performed using aqua regia, and the adhesion reinforcing metal layer 7 is removed from the region excluding the bump formation region.
Is removed.

【0024】同図(d)に示すように、レジスト層13を
除去し、新たにレジスト層14を形成し、これをパターニ
ングしてバンプ形成領域から除去して開口10を形成す
る。次いで、電流パス用金属層6を電流パスとして使用
して金メッキをなし、開口10内にバンプ11を形成する。
As shown in FIG. 1D, the resist layer 13 is removed, a new resist layer 14 is formed, and the resist layer 14 is patterned and removed from the bump formation region to form the opening 10. Next, gold plating is performed using the current path metal layer 6 as a current path, and a bump 11 is formed in the opening 10.

【0025】次に、図示しないが、第1例と同様に密着
強化金属層7をマスクとして100Å厚の薄い電流パス
用金属層6をエッチング除去する。
Next, although not shown, the thin metal layer for current path 6 having a thickness of 100 mm is removed by etching using the adhesion strengthening metal layer 7 as a mask, as in the first example.

【0026】[0026]

【発明の効果】以上説明したとおり、本発明に係る半導
体装置の製造方法においては、電解メッキ法を使用して
バンプを形成するにあたり、配線とバンプとの間に形成
される拡散防止金属層のエッチングをレジスト層をマス
クとして実施しているので、電池効果による拡散防止金
属層のサイドエッチングは防止される。一方、バンプ形
成時の電流パスとして別途形成される電流パス用金属層
は極めて薄く形成されるので、この電流パス用金属層の
エッチング時のサイドエッチングは極めて僅かであり、
エッチング液の侵入によって配線が腐蝕または変質した
り、拡散防止金属層が消滅したりすることが防止され、
半導体装置の信頼性が著しく向上する。
As described above, in the method of manufacturing a semiconductor device according to the present invention, when a bump is formed by using an electrolytic plating method, a diffusion preventing metal layer formed between a wiring and a bump is formed. Since the etching is performed using the resist layer as a mask, side etching of the diffusion preventing metal layer due to the battery effect is prevented. On the other hand, since the current path metal layer separately formed as a current path at the time of forming a bump is formed extremely thin, side etching at the time of etching the current path metal layer is extremely slight,
Prevents the wiring from being corroded or deteriorated by the intrusion of the etchant, and the diffusion prevention metal layer from disappearing.
The reliability of the semiconductor device is significantly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例のバンプ形成工程図であ
る。
FIG. 1 is a diagram showing a bump forming process according to a first embodiment of the present invention.

【図2】本発明の第2実施例のバンプ形成工程図であ
る。
FIG. 2 is a view showing a bump forming process according to a second embodiment of the present invention.

【図3】従来のバンプ形成工程図である。FIG. 3 is a view showing a conventional bump forming process.

【符号の説明】[Explanation of symbols]

1 半導体層 2 金属配線 3 拡散防止金属層 4 絶縁膜 5 開口 6 電流パス用金属層 7 密着強化金属層 10 開口 11 バンプ DESCRIPTION OF SYMBOLS 1 Semiconductor layer 2 Metal wiring 3 Diffusion prevention metal layer 4 Insulating film 5 Opening 6 Metal layer for current path 7 Adhesion strengthening metal layer 10 Opening 11 Bump

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体層上にバンプを形成する半導体装
置の製造方法であって前記半導体層上に金属配線と拡散防止金属層からなる積
層体とを形成し、 該積層体上に絶縁膜を形成し、該絶縁膜をパターニング
して前記積層体上から除去して、該積層体上に第1の開
口を形成し、 前記絶縁膜と前記第1の開口との上に、前記拡散防止金
属層と実質的に同程度の拡散防止効果を有する金属より
なる電流パス用金属層を形成し、 前記電流パス用金属層上に密着強化金属層を形成し、該
密着強化金属層をパターニングして、前記バンプの形成
領域を除く領域の前記密着強化金属層を除去し、 前記電流パス用金属層と前記密着強化金属層との上にレ
ジスト層を形成し、該レジスト層をパターニングし前記
バンプの形成領域のレジスト層を除去して、前記密着強
化金属層上に第2の開口を形成し、 前記電流パス用金属層に電流を流すことによりメッキを
行い、前記密着強化金属層上にバンプを形成し、 該密着強化金属層をマスクとして前記電流パス用金属層
を除去する ことを特徴とする半導体装置の製造方法。
(1)A semiconductor device for forming a bump on a semiconductor layer
Manufacturing method of the,A product comprising a metal wiring and a diffusion preventing metal layer on the semiconductor layer
Forming a layered body, Forming an insulating film on the laminate and patterning the insulating film;
To remove from the laminate, and place a first opening on the laminate.
Form the mouth, The diffusion preventing gold is formed on the insulating film and the first opening.
Metals that have substantially the same anti-diffusion effect as the metal layer
Forming a current path metal layer, Forming an adhesion reinforcing metal layer on the current path metal layer,
Forming the bumps by patterning the adhesion-enhancing metal layer
Removing the adhesion-enhancing metal layer in a region excluding the region, The metal layer for the current path and the adhesion reinforcing metal layer
Forming a dist layer, patterning the resist layer,
By removing the resist layer in the area where the bumps are formed,
Forming a second opening on the metal oxide layer, The plating is performed by passing a current through the current path metal layer.
Performing, forming a bump on the adhesion strengthening metal layer, The current path metal layer using the adhesion strengthening metal layer as a mask.
Remove A method for manufacturing a semiconductor device, comprising:
【請求項2】 半導体層上にバンプを形成する半導体装
置の製造方法であって、 前記半導体層上に金属配線を形成し、 該金属配線上に絶縁膜を形成し、該絶縁膜をパターニン
グして前記金属配線上から除去して、前記金属配線上に
第1の開口を形成し、 前記絶縁膜と前記第1の開口との上に、拡散防止金属層
を形成し、該拡散防止金属層をパターニングして、前記
バンプの形成領域を除く領域の前記拡散防止金属層を除
去し、 前記絶縁膜と前記拡散防止金属層との上に、前記拡散防
止金属層と実質的に同程度の拡散防止効果を有する金属
よりなる電流パス用金属層を形成し、前記電流パス用金
属層上に密着強化金属層を形成し、該密着強化金属層を
パターニングし て、前記バンプの形成領域を除く領域の
前記密着強化金属層を除去し、 前記電流パス用金属層と前記密着強化金属層との上にレ
ジスト層を形成し、該レジスト層をパターニングし前記
バンプの形成領域のレジスト層を除去して、前記密着強
化金属層上に第2の開口を形成し、 前記電流パス用金属層に電流を流すことによりメッキを
行い、前記密着強化金属層上にバンプを形成し、 該密着強化金属層をマスクとして前記電流パス用金属層
を除去する ことを特徴とする半導体装置の製造方法。
(2)A semiconductor device for forming a bump on a semiconductor layer
A method of manufacturing the device, Forming a metal wiring on the semiconductor layer, An insulating film is formed on the metal wiring, and the insulating film is patterned
To remove from the metal wiring,
Forming a first opening, A diffusion preventing metal layer on the insulating film and the first opening;
Is formed, and the diffusion preventing metal layer is patterned,
Excluding the diffusion preventing metal layer in the region except the bump formation region
Leave The diffusion barrier is formed on the insulating film and the diffusion barrier metal layer.
A metal having substantially the same diffusion prevention effect as the metal barrier layer
Forming a current path metal layer comprising:
Forming an adhesion strengthening metal layer on the metal layer,
Patterning The area other than the bump formation area
Removing the adhesion reinforcing metal layer, The metal layer for the current path and the adhesion reinforcing metal layer
Forming a dist layer, patterning the resist layer,
By removing the resist layer in the area where the bumps are formed,
Forming a second opening on the metal oxide layer, The plating is performed by passing a current through the current path metal layer.
Performing, forming a bump on the adhesion strengthening metal layer, The current path metal layer using the adhesion strengthening metal layer as a mask.
Remove A method for manufacturing a semiconductor device, comprising:
JP03136291A 1991-06-07 1991-06-07 Method for manufacturing semiconductor device Expired - Fee Related JP3110795B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03136291A JP3110795B2 (en) 1991-06-07 1991-06-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03136291A JP3110795B2 (en) 1991-06-07 1991-06-07 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04360537A JPH04360537A (en) 1992-12-14
JP3110795B2 true JP3110795B2 (en) 2000-11-20

Family

ID=15171742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03136291A Expired - Fee Related JP3110795B2 (en) 1991-06-07 1991-06-07 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3110795B2 (en)

Also Published As

Publication number Publication date
JPH04360537A (en) 1992-12-14

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